1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 22 #include "xhci.h" 23 #include "xhci-mtk.h" 24 25 /* ip_pw_ctrl0 register */ 26 #define CTRL0_IP_SW_RST BIT(0) 27 28 /* ip_pw_ctrl1 register */ 29 #define CTRL1_IP_HOST_PDN BIT(0) 30 31 /* ip_pw_ctrl2 register */ 32 #define CTRL2_IP_DEV_PDN BIT(0) 33 34 /* ip_pw_sts1 register */ 35 #define STS1_IP_SLEEP_STS BIT(30) 36 #define STS1_U3_MAC_RST BIT(16) 37 #define STS1_XHCI_RST BIT(11) 38 #define STS1_SYS125_RST BIT(10) 39 #define STS1_REF_RST BIT(8) 40 #define STS1_SYSPLL_STABLE BIT(0) 41 42 /* ip_xhci_cap register */ 43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46 /* u3_ctrl_p register */ 47 #define CTRL_U3_PORT_HOST_SEL BIT(2) 48 #define CTRL_U3_PORT_PDN BIT(1) 49 #define CTRL_U3_PORT_DIS BIT(0) 50 51 /* u2_ctrl_p register */ 52 #define CTRL_U2_PORT_HOST_SEL BIT(2) 53 #define CTRL_U2_PORT_PDN BIT(1) 54 #define CTRL_U2_PORT_DIS BIT(0) 55 56 /* u2_phy_pll register */ 57 #define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59 /* xHCI CSR */ 60 #define LS_EOF_CFG 0x930 61 #define LSEOF_OFFSET 0x89 62 63 #define FS_EOF_CFG 0x934 64 #define FSEOF_OFFSET 0x2e 65 66 #define SS_GEN1_EOF_CFG 0x93c 67 #define SSG1EOF_OFFSET 0x78 68 69 #define HFCNTR_CFG 0x944 70 #define ITP_DELTA_CLK (0xa << 1) 71 #define ITP_DELTA_CLK_MASK GENMASK(5, 1) 72 #define FRMCNT_LEV1_RANG (0x12b << 8) 73 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) 74 75 #define SS_GEN2_EOF_CFG 0x990 76 #define SSG2EOF_OFFSET 0x3c 77 78 #define XSEOF_OFFSET_MASK GENMASK(11, 0) 79 80 /* usb remote wakeup registers in syscon */ 81 82 /* mt8173 etc */ 83 #define PERI_WK_CTRL1 0x4 84 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 85 #define WC1_IS_EN BIT(25) 86 #define WC1_IS_P BIT(6) /* polarity for ip sleep */ 87 88 /* mt8183 */ 89 #define PERI_WK_CTRL0 0x0 90 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */ 91 #define WC0_IS_P BIT(12) /* polarity */ 92 #define WC0_IS_EN BIT(6) 93 94 /* mt8192 */ 95 #define WC0_SSUSB0_CDEN BIT(6) 96 #define WC0_IS_SPM_EN BIT(1) 97 98 /* mt2712 etc */ 99 #define PERI_SSUSB_SPM_CTRL 0x0 100 #define SSC_IP_SLEEP_EN BIT(4) 101 #define SSC_SPM_INT_EN BIT(1) 102 103 enum ssusb_uwk_vers { 104 SSUSB_UWK_V1 = 1, 105 SSUSB_UWK_V2, 106 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ 107 SSUSB_UWK_V1_2, /* specific revision 1.2 */ 108 }; 109 110 /* 111 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval 112 * is calculated from the frame counter clock 24M, but in fact, the clock 113 * is 48M, add workaround for it. 114 */ 115 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) 116 { 117 struct device *dev = mtk->dev; 118 struct usb_hcd *hcd = mtk->hcd; 119 u32 value; 120 121 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) 122 return; 123 124 value = readl(hcd->regs + HFCNTR_CFG); 125 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); 126 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); 127 writel(value, hcd->regs + HFCNTR_CFG); 128 129 value = readl(hcd->regs + LS_EOF_CFG); 130 value &= ~XSEOF_OFFSET_MASK; 131 value |= LSEOF_OFFSET; 132 writel(value, hcd->regs + LS_EOF_CFG); 133 134 value = readl(hcd->regs + FS_EOF_CFG); 135 value &= ~XSEOF_OFFSET_MASK; 136 value |= FSEOF_OFFSET; 137 writel(value, hcd->regs + FS_EOF_CFG); 138 139 value = readl(hcd->regs + SS_GEN1_EOF_CFG); 140 value &= ~XSEOF_OFFSET_MASK; 141 value |= SSG1EOF_OFFSET; 142 writel(value, hcd->regs + SS_GEN1_EOF_CFG); 143 144 value = readl(hcd->regs + SS_GEN2_EOF_CFG); 145 value &= ~XSEOF_OFFSET_MASK; 146 value |= SSG2EOF_OFFSET; 147 writel(value, hcd->regs + SS_GEN2_EOF_CFG); 148 } 149 150 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 151 { 152 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 153 u32 value, check_val; 154 int u3_ports_disabled = 0; 155 int ret; 156 int i; 157 158 if (!mtk->has_ippc) 159 return 0; 160 161 /* power on host ip */ 162 value = readl(&ippc->ip_pw_ctr1); 163 value &= ~CTRL1_IP_HOST_PDN; 164 writel(value, &ippc->ip_pw_ctr1); 165 166 /* power on and enable u3 ports except skipped ones */ 167 for (i = 0; i < mtk->num_u3_ports; i++) { 168 if ((0x1 << i) & mtk->u3p_dis_msk) { 169 u3_ports_disabled++; 170 continue; 171 } 172 173 value = readl(&ippc->u3_ctrl_p[i]); 174 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 175 value |= CTRL_U3_PORT_HOST_SEL; 176 writel(value, &ippc->u3_ctrl_p[i]); 177 } 178 179 /* power on and enable all u2 ports except skipped ones */ 180 for (i = 0; i < mtk->num_u2_ports; i++) { 181 if (BIT(i) & mtk->u2p_dis_msk) 182 continue; 183 184 value = readl(&ippc->u2_ctrl_p[i]); 185 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 186 value |= CTRL_U2_PORT_HOST_SEL; 187 writel(value, &ippc->u2_ctrl_p[i]); 188 } 189 190 /* 191 * wait for clocks to be stable, and clock domains reset to 192 * be inactive after power on and enable ports 193 */ 194 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 195 STS1_SYS125_RST | STS1_XHCI_RST; 196 197 if (mtk->num_u3_ports > u3_ports_disabled) 198 check_val |= STS1_U3_MAC_RST; 199 200 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 201 (check_val == (value & check_val)), 100, 20000); 202 if (ret) { 203 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 204 return ret; 205 } 206 207 return 0; 208 } 209 210 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 211 { 212 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 213 u32 value; 214 int ret; 215 int i; 216 217 if (!mtk->has_ippc) 218 return 0; 219 220 /* power down u3 ports except skipped ones */ 221 for (i = 0; i < mtk->num_u3_ports; i++) { 222 if ((0x1 << i) & mtk->u3p_dis_msk) 223 continue; 224 225 value = readl(&ippc->u3_ctrl_p[i]); 226 value |= CTRL_U3_PORT_PDN; 227 writel(value, &ippc->u3_ctrl_p[i]); 228 } 229 230 /* power down all u2 ports except skipped ones */ 231 for (i = 0; i < mtk->num_u2_ports; i++) { 232 if (BIT(i) & mtk->u2p_dis_msk) 233 continue; 234 235 value = readl(&ippc->u2_ctrl_p[i]); 236 value |= CTRL_U2_PORT_PDN; 237 writel(value, &ippc->u2_ctrl_p[i]); 238 } 239 240 /* power down host ip */ 241 value = readl(&ippc->ip_pw_ctr1); 242 value |= CTRL1_IP_HOST_PDN; 243 writel(value, &ippc->ip_pw_ctr1); 244 245 /* wait for host ip to sleep */ 246 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 247 (value & STS1_IP_SLEEP_STS), 100, 100000); 248 if (ret) 249 dev_err(mtk->dev, "ip sleep failed!!!\n"); 250 else /* workaound for platforms using low level latch */ 251 usleep_range(100, 200); 252 253 return ret; 254 } 255 256 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 257 { 258 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 259 u32 value; 260 261 if (!mtk->has_ippc) 262 return 0; 263 264 /* reset whole ip */ 265 value = readl(&ippc->ip_pw_ctr0); 266 value |= CTRL0_IP_SW_RST; 267 writel(value, &ippc->ip_pw_ctr0); 268 udelay(1); 269 value = readl(&ippc->ip_pw_ctr0); 270 value &= ~CTRL0_IP_SW_RST; 271 writel(value, &ippc->ip_pw_ctr0); 272 273 /* 274 * device ip is default power-on in fact 275 * power down device ip, otherwise ip-sleep will fail 276 */ 277 value = readl(&ippc->ip_pw_ctr2); 278 value |= CTRL2_IP_DEV_PDN; 279 writel(value, &ippc->ip_pw_ctr2); 280 281 value = readl(&ippc->ip_xhci_cap); 282 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 283 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 284 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 285 mtk->num_u2_ports, mtk->num_u3_ports); 286 287 return xhci_mtk_host_enable(mtk); 288 } 289 290 /* only clocks can be turn off for ip-sleep wakeup mode */ 291 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 292 { 293 u32 reg, msk, val; 294 295 switch (mtk->uwk_vers) { 296 case SSUSB_UWK_V1: 297 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 298 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 299 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 300 break; 301 case SSUSB_UWK_V1_1: 302 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 303 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P; 304 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0; 305 break; 306 case SSUSB_UWK_V1_2: 307 reg = mtk->uwk_reg_base + PERI_WK_CTRL0; 308 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; 309 val = enable ? msk : 0; 310 break; 311 case SSUSB_UWK_V2: 312 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 313 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 314 val = enable ? msk : 0; 315 break; 316 default: 317 return; 318 } 319 regmap_update_bits(mtk->uwk, reg, msk, val); 320 } 321 322 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 323 struct device_node *dn) 324 { 325 struct of_phandle_args args; 326 int ret; 327 328 /* Wakeup function is optional */ 329 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 330 if (!mtk->uwk_en) 331 return 0; 332 333 ret = of_parse_phandle_with_fixed_args(dn, 334 "mediatek,syscon-wakeup", 2, 0, &args); 335 if (ret) 336 return ret; 337 338 mtk->uwk_reg_base = args.args[0]; 339 mtk->uwk_vers = args.args[1]; 340 mtk->uwk = syscon_node_to_regmap(args.np); 341 of_node_put(args.np); 342 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 343 mtk->uwk_reg_base, mtk->uwk_vers); 344 345 return PTR_ERR_OR_ZERO(mtk->uwk); 346 } 347 348 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 349 { 350 if (mtk->uwk_en) 351 usb_wakeup_ip_sleep_set(mtk, enable); 352 } 353 354 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 355 { 356 struct clk_bulk_data *clks = mtk->clks; 357 358 clks[0].id = "sys_ck"; 359 clks[1].id = "xhci_ck"; 360 clks[2].id = "ref_ck"; 361 clks[3].id = "mcu_ck"; 362 clks[4].id = "dma_ck"; 363 364 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks); 365 } 366 367 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 368 { 369 int ret; 370 371 ret = regulator_enable(mtk->vbus); 372 if (ret) { 373 dev_err(mtk->dev, "failed to enable vbus\n"); 374 return ret; 375 } 376 377 ret = regulator_enable(mtk->vusb33); 378 if (ret) { 379 dev_err(mtk->dev, "failed to enable vusb33\n"); 380 regulator_disable(mtk->vbus); 381 return ret; 382 } 383 return 0; 384 } 385 386 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 387 { 388 regulator_disable(mtk->vbus); 389 regulator_disable(mtk->vusb33); 390 } 391 392 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 393 { 394 struct usb_hcd *hcd = xhci_to_hcd(xhci); 395 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 396 397 /* 398 * As of now platform drivers don't provide MSI support so we ensure 399 * here that the generic code does not try to make a pci_dev from our 400 * dev struct in order to setup MSI 401 */ 402 xhci->quirks |= XHCI_PLAT; 403 xhci->quirks |= XHCI_MTK_HOST; 404 /* 405 * MTK host controller gives a spurious successful event after a 406 * short transfer. Ignore it. 407 */ 408 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 409 if (mtk->lpm_support) 410 xhci->quirks |= XHCI_LPM_SUPPORT; 411 if (mtk->u2_lpm_disable) 412 xhci->quirks |= XHCI_HW_LPM_DISABLE; 413 414 /* 415 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, 416 * and it's 3 when support it. 417 */ 418 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) 419 xhci->quirks |= XHCI_BROKEN_STREAMS; 420 } 421 422 /* called during probe() after chip reset completes */ 423 static int xhci_mtk_setup(struct usb_hcd *hcd) 424 { 425 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 426 int ret; 427 428 if (usb_hcd_is_primary_hcd(hcd)) { 429 ret = xhci_mtk_ssusb_config(mtk); 430 if (ret) 431 return ret; 432 433 /* workaround only for mt8195 */ 434 xhci_mtk_set_frame_interval(mtk); 435 } 436 437 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 438 if (ret) 439 return ret; 440 441 if (usb_hcd_is_primary_hcd(hcd)) 442 ret = xhci_mtk_sch_init(mtk); 443 444 return ret; 445 } 446 447 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 448 .reset = xhci_mtk_setup, 449 .add_endpoint = xhci_mtk_add_ep, 450 .drop_endpoint = xhci_mtk_drop_ep, 451 .check_bandwidth = xhci_mtk_check_bandwidth, 452 .reset_bandwidth = xhci_mtk_reset_bandwidth, 453 }; 454 455 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 456 457 static int xhci_mtk_probe(struct platform_device *pdev) 458 { 459 struct device *dev = &pdev->dev; 460 struct device_node *node = dev->of_node; 461 struct xhci_hcd_mtk *mtk; 462 const struct hc_driver *driver; 463 struct xhci_hcd *xhci; 464 struct resource *res; 465 struct usb_hcd *hcd; 466 int ret = -ENODEV; 467 int wakeup_irq; 468 int irq; 469 470 if (usb_disabled()) 471 return -ENODEV; 472 473 driver = &xhci_mtk_hc_driver; 474 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 475 if (!mtk) 476 return -ENOMEM; 477 478 mtk->dev = dev; 479 mtk->vbus = devm_regulator_get(dev, "vbus"); 480 if (IS_ERR(mtk->vbus)) { 481 dev_err(dev, "fail to get vbus\n"); 482 return PTR_ERR(mtk->vbus); 483 } 484 485 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 486 if (IS_ERR(mtk->vusb33)) { 487 dev_err(dev, "fail to get vusb33\n"); 488 return PTR_ERR(mtk->vusb33); 489 } 490 491 ret = xhci_mtk_clks_get(mtk); 492 if (ret) 493 return ret; 494 495 irq = platform_get_irq_byname_optional(pdev, "host"); 496 if (irq < 0) { 497 if (irq == -EPROBE_DEFER) 498 return irq; 499 500 /* for backward compatibility */ 501 irq = platform_get_irq(pdev, 0); 502 if (irq < 0) 503 return irq; 504 } 505 506 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 507 if (wakeup_irq == -EPROBE_DEFER) 508 return wakeup_irq; 509 510 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 511 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); 512 /* optional property, ignore the error if it does not exist */ 513 of_property_read_u32(node, "mediatek,u3p-dis-msk", 514 &mtk->u3p_dis_msk); 515 of_property_read_u32(node, "mediatek,u2p-dis-msk", 516 &mtk->u2p_dis_msk); 517 518 ret = usb_wakeup_of_property_parse(mtk, node); 519 if (ret) { 520 dev_err(dev, "failed to parse uwk property\n"); 521 return ret; 522 } 523 524 pm_runtime_set_active(dev); 525 pm_runtime_use_autosuspend(dev); 526 pm_runtime_set_autosuspend_delay(dev, 4000); 527 pm_runtime_enable(dev); 528 pm_runtime_get_sync(dev); 529 530 ret = xhci_mtk_ldos_enable(mtk); 531 if (ret) 532 goto disable_pm; 533 534 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 535 if (ret) 536 goto disable_ldos; 537 538 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 539 if (!hcd) { 540 ret = -ENOMEM; 541 goto disable_clk; 542 } 543 544 /* 545 * USB 2.0 roothub is stored in the platform_device. 546 * Swap it with mtk HCD. 547 */ 548 mtk->hcd = platform_get_drvdata(pdev); 549 platform_set_drvdata(pdev, mtk); 550 551 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 552 hcd->regs = devm_ioremap_resource(dev, res); 553 if (IS_ERR(hcd->regs)) { 554 ret = PTR_ERR(hcd->regs); 555 goto put_usb2_hcd; 556 } 557 hcd->rsrc_start = res->start; 558 hcd->rsrc_len = resource_size(res); 559 560 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 561 if (res) { /* ippc register is optional */ 562 mtk->ippc_regs = devm_ioremap_resource(dev, res); 563 if (IS_ERR(mtk->ippc_regs)) { 564 ret = PTR_ERR(mtk->ippc_regs); 565 goto put_usb2_hcd; 566 } 567 mtk->has_ippc = true; 568 } 569 570 device_init_wakeup(dev, true); 571 572 xhci = hcd_to_xhci(hcd); 573 xhci->main_hcd = hcd; 574 575 /* 576 * imod_interval is the interrupt moderation value in nanoseconds. 577 * The increment interval is 8 times as much as that defined in 578 * the xHCI spec on MTK's controller. 579 */ 580 xhci->imod_interval = 5000; 581 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 582 583 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 584 dev_name(dev), hcd); 585 if (!xhci->shared_hcd) { 586 ret = -ENOMEM; 587 goto disable_device_wakeup; 588 } 589 590 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 591 if (ret) 592 goto put_usb3_hcd; 593 594 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && 595 !(xhci->quirks & XHCI_BROKEN_STREAMS)) 596 xhci->shared_hcd->can_do_streams = 1; 597 598 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 599 if (ret) 600 goto dealloc_usb2_hcd; 601 602 if (wakeup_irq > 0) { 603 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq); 604 if (ret) { 605 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq); 606 goto dealloc_usb3_hcd; 607 } 608 dev_info(dev, "wakeup irq %d\n", wakeup_irq); 609 } 610 611 device_enable_async_suspend(dev); 612 pm_runtime_mark_last_busy(dev); 613 pm_runtime_put_autosuspend(dev); 614 pm_runtime_forbid(dev); 615 616 return 0; 617 618 dealloc_usb3_hcd: 619 usb_remove_hcd(xhci->shared_hcd); 620 xhci->shared_hcd = NULL; 621 622 dealloc_usb2_hcd: 623 usb_remove_hcd(hcd); 624 625 put_usb3_hcd: 626 xhci_mtk_sch_exit(mtk); 627 usb_put_hcd(xhci->shared_hcd); 628 629 disable_device_wakeup: 630 device_init_wakeup(dev, false); 631 632 put_usb2_hcd: 633 usb_put_hcd(hcd); 634 635 disable_clk: 636 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 637 638 disable_ldos: 639 xhci_mtk_ldos_disable(mtk); 640 641 disable_pm: 642 pm_runtime_put_noidle(dev); 643 pm_runtime_disable(dev); 644 return ret; 645 } 646 647 static int xhci_mtk_remove(struct platform_device *pdev) 648 { 649 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev); 650 struct usb_hcd *hcd = mtk->hcd; 651 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 652 struct usb_hcd *shared_hcd = xhci->shared_hcd; 653 struct device *dev = &pdev->dev; 654 655 pm_runtime_get_sync(dev); 656 xhci->xhc_state |= XHCI_STATE_REMOVING; 657 dev_pm_clear_wake_irq(dev); 658 device_init_wakeup(dev, false); 659 660 usb_remove_hcd(shared_hcd); 661 xhci->shared_hcd = NULL; 662 usb_remove_hcd(hcd); 663 usb_put_hcd(shared_hcd); 664 usb_put_hcd(hcd); 665 xhci_mtk_sch_exit(mtk); 666 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 667 xhci_mtk_ldos_disable(mtk); 668 669 pm_runtime_disable(dev); 670 pm_runtime_put_noidle(dev); 671 pm_runtime_set_suspended(dev); 672 673 return 0; 674 } 675 676 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 677 { 678 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 679 struct usb_hcd *hcd = mtk->hcd; 680 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 681 int ret; 682 683 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 684 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 685 del_timer_sync(&hcd->rh_timer); 686 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 687 del_timer_sync(&xhci->shared_hcd->rh_timer); 688 689 ret = xhci_mtk_host_disable(mtk); 690 if (ret) 691 goto restart_poll_rh; 692 693 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 694 usb_wakeup_set(mtk, true); 695 return 0; 696 697 restart_poll_rh: 698 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 699 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 700 usb_hcd_poll_rh_status(xhci->shared_hcd); 701 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 702 usb_hcd_poll_rh_status(hcd); 703 return ret; 704 } 705 706 static int __maybe_unused xhci_mtk_resume(struct device *dev) 707 { 708 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 709 struct usb_hcd *hcd = mtk->hcd; 710 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 711 int ret; 712 713 usb_wakeup_set(mtk, false); 714 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks); 715 if (ret) 716 goto enable_wakeup; 717 718 ret = xhci_mtk_host_enable(mtk); 719 if (ret) 720 goto disable_clks; 721 722 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 723 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 724 usb_hcd_poll_rh_status(xhci->shared_hcd); 725 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 726 usb_hcd_poll_rh_status(hcd); 727 return 0; 728 729 disable_clks: 730 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); 731 enable_wakeup: 732 usb_wakeup_set(mtk, true); 733 return ret; 734 } 735 736 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev) 737 { 738 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 739 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 740 int ret = 0; 741 742 if (xhci->xhc_state) 743 return -ESHUTDOWN; 744 745 if (device_may_wakeup(dev)) 746 ret = xhci_mtk_suspend(dev); 747 748 /* -EBUSY: let PM automatically reschedule another autosuspend */ 749 return ret ? -EBUSY : 0; 750 } 751 752 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev) 753 { 754 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 755 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); 756 int ret = 0; 757 758 if (xhci->xhc_state) 759 return -ESHUTDOWN; 760 761 if (device_may_wakeup(dev)) 762 ret = xhci_mtk_resume(dev); 763 764 return ret; 765 } 766 767 static const struct dev_pm_ops xhci_mtk_pm_ops = { 768 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 769 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend, 770 xhci_mtk_runtime_resume, NULL) 771 }; 772 773 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL) 774 775 static const struct of_device_id mtk_xhci_of_match[] = { 776 { .compatible = "mediatek,mt8173-xhci"}, 777 { .compatible = "mediatek,mt8195-xhci"}, 778 { .compatible = "mediatek,mtk-xhci"}, 779 { }, 780 }; 781 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 782 783 static struct platform_driver mtk_xhci_driver = { 784 .probe = xhci_mtk_probe, 785 .remove = xhci_mtk_remove, 786 .driver = { 787 .name = "xhci-mtk", 788 .pm = DEV_PM_OPS, 789 .of_match_table = mtk_xhci_of_match, 790 }, 791 }; 792 793 static int __init xhci_mtk_init(void) 794 { 795 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 796 return platform_driver_register(&mtk_xhci_driver); 797 } 798 module_init(xhci_mtk_init); 799 800 static void __exit xhci_mtk_exit(void) 801 { 802 platform_driver_unregister(&mtk_xhci_driver); 803 } 804 module_exit(xhci_mtk_exit); 805 806 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 807 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 808 MODULE_LICENSE("GPL v2"); 809