1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/usb.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include <linux/dmapool.h> 27 28 #include "xhci.h" 29 30 /* 31 * Allocates a generic ring segment from the ring pool, sets the dma address, 32 * initializes the segment to zero, and sets the private next pointer to NULL. 33 * 34 * Section 4.11.1.1: 35 * "All components of all Command and Transfer TRBs shall be initialized to '0'" 36 */ 37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags) 38 { 39 struct xhci_segment *seg; 40 dma_addr_t dma; 41 42 seg = kzalloc(sizeof *seg, flags); 43 if (!seg) 44 return NULL; 45 xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg); 46 47 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); 48 if (!seg->trbs) { 49 kfree(seg); 50 return NULL; 51 } 52 xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n", 53 seg->trbs, (unsigned long long)dma); 54 55 memset(seg->trbs, 0, SEGMENT_SIZE); 56 seg->dma = dma; 57 seg->next = NULL; 58 59 return seg; 60 } 61 62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) 63 { 64 if (!seg) 65 return; 66 if (seg->trbs) { 67 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n", 68 seg->trbs, (unsigned long long)seg->dma); 69 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); 70 seg->trbs = NULL; 71 } 72 xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg); 73 kfree(seg); 74 } 75 76 /* 77 * Make the prev segment point to the next segment. 78 * 79 * Change the last TRB in the prev segment to be a Link TRB which points to the 80 * DMA address of the next segment. The caller needs to set any Link TRB 81 * related flags, such as End TRB, Toggle Cycle, and no snoop. 82 */ 83 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, 84 struct xhci_segment *next, bool link_trbs) 85 { 86 u32 val; 87 88 if (!prev || !next) 89 return; 90 prev->next = next; 91 if (link_trbs) { 92 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma; 93 94 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ 95 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control; 96 val &= ~TRB_TYPE_BITMASK; 97 val |= TRB_TYPE(TRB_LINK); 98 /* Always set the chain bit with 0.95 hardware */ 99 if (xhci_link_trb_quirk(xhci)) 100 val |= TRB_CHAIN; 101 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val; 102 } 103 xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n", 104 (unsigned long long)prev->dma, 105 (unsigned long long)next->dma); 106 } 107 108 /* XXX: Do we need the hcd structure in all these functions? */ 109 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) 110 { 111 struct xhci_segment *seg; 112 struct xhci_segment *first_seg; 113 114 if (!ring || !ring->first_seg) 115 return; 116 first_seg = ring->first_seg; 117 seg = first_seg->next; 118 xhci_dbg(xhci, "Freeing ring at %p\n", ring); 119 while (seg != first_seg) { 120 struct xhci_segment *next = seg->next; 121 xhci_segment_free(xhci, seg); 122 seg = next; 123 } 124 xhci_segment_free(xhci, first_seg); 125 ring->first_seg = NULL; 126 kfree(ring); 127 } 128 129 static void xhci_initialize_ring_info(struct xhci_ring *ring) 130 { 131 /* The ring is empty, so the enqueue pointer == dequeue pointer */ 132 ring->enqueue = ring->first_seg->trbs; 133 ring->enq_seg = ring->first_seg; 134 ring->dequeue = ring->enqueue; 135 ring->deq_seg = ring->first_seg; 136 /* The ring is initialized to 0. The producer must write 1 to the cycle 137 * bit to handover ownership of the TRB, so PCS = 1. The consumer must 138 * compare CCS to the cycle bit to check ownership, so CCS = 1. 139 */ 140 ring->cycle_state = 1; 141 /* Not necessary for new rings, but needed for re-initialized rings */ 142 ring->enq_updates = 0; 143 ring->deq_updates = 0; 144 } 145 146 /** 147 * Create a new ring with zero or more segments. 148 * 149 * Link each segment together into a ring. 150 * Set the end flag and the cycle toggle bit on the last segment. 151 * See section 4.9.1 and figures 15 and 16. 152 */ 153 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 154 unsigned int num_segs, bool link_trbs, gfp_t flags) 155 { 156 struct xhci_ring *ring; 157 struct xhci_segment *prev; 158 159 ring = kzalloc(sizeof *(ring), flags); 160 xhci_dbg(xhci, "Allocating ring at %p\n", ring); 161 if (!ring) 162 return NULL; 163 164 INIT_LIST_HEAD(&ring->td_list); 165 if (num_segs == 0) 166 return ring; 167 168 ring->first_seg = xhci_segment_alloc(xhci, flags); 169 if (!ring->first_seg) 170 goto fail; 171 num_segs--; 172 173 prev = ring->first_seg; 174 while (num_segs > 0) { 175 struct xhci_segment *next; 176 177 next = xhci_segment_alloc(xhci, flags); 178 if (!next) 179 goto fail; 180 xhci_link_segments(xhci, prev, next, link_trbs); 181 182 prev = next; 183 num_segs--; 184 } 185 xhci_link_segments(xhci, prev, ring->first_seg, link_trbs); 186 187 if (link_trbs) { 188 /* See section 4.9.2.1 and 6.4.4.1 */ 189 prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE); 190 xhci_dbg(xhci, "Wrote link toggle flag to" 191 " segment %p (virtual), 0x%llx (DMA)\n", 192 prev, (unsigned long long)prev->dma); 193 } 194 xhci_initialize_ring_info(ring); 195 return ring; 196 197 fail: 198 xhci_ring_free(xhci, ring); 199 return NULL; 200 } 201 202 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 203 struct xhci_virt_device *virt_dev, 204 unsigned int ep_index) 205 { 206 int rings_cached; 207 208 rings_cached = virt_dev->num_rings_cached; 209 if (rings_cached < XHCI_MAX_RINGS_CACHED) { 210 virt_dev->num_rings_cached++; 211 rings_cached = virt_dev->num_rings_cached; 212 virt_dev->ring_cache[rings_cached] = 213 virt_dev->eps[ep_index].ring; 214 xhci_dbg(xhci, "Cached old ring, " 215 "%d ring%s cached\n", 216 rings_cached, 217 (rings_cached > 1) ? "s" : ""); 218 } else { 219 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); 220 xhci_dbg(xhci, "Ring cache full (%d rings), " 221 "freeing ring\n", 222 virt_dev->num_rings_cached); 223 } 224 virt_dev->eps[ep_index].ring = NULL; 225 } 226 227 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue 228 * pointers to the beginning of the ring. 229 */ 230 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, 231 struct xhci_ring *ring) 232 { 233 struct xhci_segment *seg = ring->first_seg; 234 do { 235 memset(seg->trbs, 0, 236 sizeof(union xhci_trb)*TRBS_PER_SEGMENT); 237 /* All endpoint rings have link TRBs */ 238 xhci_link_segments(xhci, seg, seg->next, 1); 239 seg = seg->next; 240 } while (seg != ring->first_seg); 241 xhci_initialize_ring_info(ring); 242 /* td list should be empty since all URBs have been cancelled, 243 * but just in case... 244 */ 245 INIT_LIST_HEAD(&ring->td_list); 246 } 247 248 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 249 250 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 251 int type, gfp_t flags) 252 { 253 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags); 254 if (!ctx) 255 return NULL; 256 257 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); 258 ctx->type = type; 259 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; 260 if (type == XHCI_CTX_TYPE_INPUT) 261 ctx->size += CTX_SIZE(xhci->hcc_params); 262 263 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); 264 memset(ctx->bytes, 0, ctx->size); 265 return ctx; 266 } 267 268 static void xhci_free_container_ctx(struct xhci_hcd *xhci, 269 struct xhci_container_ctx *ctx) 270 { 271 if (!ctx) 272 return; 273 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); 274 kfree(ctx); 275 } 276 277 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, 278 struct xhci_container_ctx *ctx) 279 { 280 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); 281 return (struct xhci_input_control_ctx *)ctx->bytes; 282 } 283 284 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, 285 struct xhci_container_ctx *ctx) 286 { 287 if (ctx->type == XHCI_CTX_TYPE_DEVICE) 288 return (struct xhci_slot_ctx *)ctx->bytes; 289 290 return (struct xhci_slot_ctx *) 291 (ctx->bytes + CTX_SIZE(xhci->hcc_params)); 292 } 293 294 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, 295 struct xhci_container_ctx *ctx, 296 unsigned int ep_index) 297 { 298 /* increment ep index by offset of start of ep ctx array */ 299 ep_index++; 300 if (ctx->type == XHCI_CTX_TYPE_INPUT) 301 ep_index++; 302 303 return (struct xhci_ep_ctx *) 304 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); 305 } 306 307 308 /***************** Streams structures manipulation *************************/ 309 310 void xhci_free_stream_ctx(struct xhci_hcd *xhci, 311 unsigned int num_stream_ctxs, 312 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) 313 { 314 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 315 316 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) 317 pci_free_consistent(pdev, 318 sizeof(struct xhci_stream_ctx)*num_stream_ctxs, 319 stream_ctx, dma); 320 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) 321 return dma_pool_free(xhci->small_streams_pool, 322 stream_ctx, dma); 323 else 324 return dma_pool_free(xhci->medium_streams_pool, 325 stream_ctx, dma); 326 } 327 328 /* 329 * The stream context array for each endpoint with bulk streams enabled can 330 * vary in size, based on: 331 * - how many streams the endpoint supports, 332 * - the maximum primary stream array size the host controller supports, 333 * - and how many streams the device driver asks for. 334 * 335 * The stream context array must be a power of 2, and can be as small as 336 * 64 bytes or as large as 1MB. 337 */ 338 struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, 339 unsigned int num_stream_ctxs, dma_addr_t *dma, 340 gfp_t mem_flags) 341 { 342 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 343 344 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) 345 return pci_alloc_consistent(pdev, 346 sizeof(struct xhci_stream_ctx)*num_stream_ctxs, 347 dma); 348 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) 349 return dma_pool_alloc(xhci->small_streams_pool, 350 mem_flags, dma); 351 else 352 return dma_pool_alloc(xhci->medium_streams_pool, 353 mem_flags, dma); 354 } 355 356 struct xhci_ring *xhci_dma_to_transfer_ring( 357 struct xhci_virt_ep *ep, 358 u64 address) 359 { 360 if (ep->ep_state & EP_HAS_STREAMS) 361 return radix_tree_lookup(&ep->stream_info->trb_address_map, 362 address >> SEGMENT_SHIFT); 363 return ep->ring; 364 } 365 366 /* Only use this when you know stream_info is valid */ 367 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 368 static struct xhci_ring *dma_to_stream_ring( 369 struct xhci_stream_info *stream_info, 370 u64 address) 371 { 372 return radix_tree_lookup(&stream_info->trb_address_map, 373 address >> SEGMENT_SHIFT); 374 } 375 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ 376 377 struct xhci_ring *xhci_stream_id_to_ring( 378 struct xhci_virt_device *dev, 379 unsigned int ep_index, 380 unsigned int stream_id) 381 { 382 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 383 384 if (stream_id == 0) 385 return ep->ring; 386 if (!ep->stream_info) 387 return NULL; 388 389 if (stream_id > ep->stream_info->num_streams) 390 return NULL; 391 return ep->stream_info->stream_rings[stream_id]; 392 } 393 394 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 395 unsigned int slot_id, unsigned int ep_index, 396 unsigned int stream_id) 397 { 398 struct xhci_virt_ep *ep; 399 400 ep = &xhci->devs[slot_id]->eps[ep_index]; 401 /* Common case: no streams */ 402 if (!(ep->ep_state & EP_HAS_STREAMS)) 403 return ep->ring; 404 405 if (stream_id == 0) { 406 xhci_warn(xhci, 407 "WARN: Slot ID %u, ep index %u has streams, " 408 "but URB has no stream ID.\n", 409 slot_id, ep_index); 410 return NULL; 411 } 412 413 if (stream_id < ep->stream_info->num_streams) 414 return ep->stream_info->stream_rings[stream_id]; 415 416 xhci_warn(xhci, 417 "WARN: Slot ID %u, ep index %u has " 418 "stream IDs 1 to %u allocated, " 419 "but stream ID %u is requested.\n", 420 slot_id, ep_index, 421 ep->stream_info->num_streams - 1, 422 stream_id); 423 return NULL; 424 } 425 426 /* Get the right ring for the given URB. 427 * If the endpoint supports streams, boundary check the URB's stream ID. 428 * If the endpoint doesn't support streams, return the singular endpoint ring. 429 */ 430 struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 431 struct urb *urb) 432 { 433 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 434 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); 435 } 436 437 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING 438 static int xhci_test_radix_tree(struct xhci_hcd *xhci, 439 unsigned int num_streams, 440 struct xhci_stream_info *stream_info) 441 { 442 u32 cur_stream; 443 struct xhci_ring *cur_ring; 444 u64 addr; 445 446 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 447 struct xhci_ring *mapped_ring; 448 int trb_size = sizeof(union xhci_trb); 449 450 cur_ring = stream_info->stream_rings[cur_stream]; 451 for (addr = cur_ring->first_seg->dma; 452 addr < cur_ring->first_seg->dma + SEGMENT_SIZE; 453 addr += trb_size) { 454 mapped_ring = dma_to_stream_ring(stream_info, addr); 455 if (cur_ring != mapped_ring) { 456 xhci_warn(xhci, "WARN: DMA address 0x%08llx " 457 "didn't map to stream ID %u; " 458 "mapped to ring %p\n", 459 (unsigned long long) addr, 460 cur_stream, 461 mapped_ring); 462 return -EINVAL; 463 } 464 } 465 /* One TRB after the end of the ring segment shouldn't return a 466 * pointer to the current ring (although it may be a part of a 467 * different ring). 468 */ 469 mapped_ring = dma_to_stream_ring(stream_info, addr); 470 if (mapped_ring != cur_ring) { 471 /* One TRB before should also fail */ 472 addr = cur_ring->first_seg->dma - trb_size; 473 mapped_ring = dma_to_stream_ring(stream_info, addr); 474 } 475 if (mapped_ring == cur_ring) { 476 xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx " 477 "mapped to valid stream ID %u; " 478 "mapped ring = %p\n", 479 (unsigned long long) addr, 480 cur_stream, 481 mapped_ring); 482 return -EINVAL; 483 } 484 } 485 return 0; 486 } 487 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ 488 489 /* 490 * Change an endpoint's internal structure so it supports stream IDs. The 491 * number of requested streams includes stream 0, which cannot be used by device 492 * drivers. 493 * 494 * The number of stream contexts in the stream context array may be bigger than 495 * the number of streams the driver wants to use. This is because the number of 496 * stream context array entries must be a power of two. 497 * 498 * We need a radix tree for mapping physical addresses of TRBs to which stream 499 * ID they belong to. We need to do this because the host controller won't tell 500 * us which stream ring the TRB came from. We could store the stream ID in an 501 * event data TRB, but that doesn't help us for the cancellation case, since the 502 * endpoint may stop before it reaches that event data TRB. 503 * 504 * The radix tree maps the upper portion of the TRB DMA address to a ring 505 * segment that has the same upper portion of DMA addresses. For example, say I 506 * have segments of size 1KB, that are always 64-byte aligned. A segment may 507 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the 508 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to 509 * pass the radix tree a key to get the right stream ID: 510 * 511 * 0x10c90fff >> 10 = 0x43243 512 * 0x10c912c0 >> 10 = 0x43244 513 * 0x10c91400 >> 10 = 0x43245 514 * 515 * Obviously, only those TRBs with DMA addresses that are within the segment 516 * will make the radix tree return the stream ID for that ring. 517 * 518 * Caveats for the radix tree: 519 * 520 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an 521 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be 522 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the 523 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit 524 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit 525 * extended systems (where the DMA address can be bigger than 32-bits), 526 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. 527 */ 528 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 529 unsigned int num_stream_ctxs, 530 unsigned int num_streams, gfp_t mem_flags) 531 { 532 struct xhci_stream_info *stream_info; 533 u32 cur_stream; 534 struct xhci_ring *cur_ring; 535 unsigned long key; 536 u64 addr; 537 int ret; 538 539 xhci_dbg(xhci, "Allocating %u streams and %u " 540 "stream context array entries.\n", 541 num_streams, num_stream_ctxs); 542 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { 543 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); 544 return NULL; 545 } 546 xhci->cmd_ring_reserved_trbs++; 547 548 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); 549 if (!stream_info) 550 goto cleanup_trbs; 551 552 stream_info->num_streams = num_streams; 553 stream_info->num_stream_ctxs = num_stream_ctxs; 554 555 /* Initialize the array of virtual pointers to stream rings. */ 556 stream_info->stream_rings = kzalloc( 557 sizeof(struct xhci_ring *)*num_streams, 558 mem_flags); 559 if (!stream_info->stream_rings) 560 goto cleanup_info; 561 562 /* Initialize the array of DMA addresses for stream rings for the HW. */ 563 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, 564 num_stream_ctxs, &stream_info->ctx_array_dma, 565 mem_flags); 566 if (!stream_info->stream_ctx_array) 567 goto cleanup_ctx; 568 memset(stream_info->stream_ctx_array, 0, 569 sizeof(struct xhci_stream_ctx)*num_stream_ctxs); 570 571 /* Allocate everything needed to free the stream rings later */ 572 stream_info->free_streams_command = 573 xhci_alloc_command(xhci, true, true, mem_flags); 574 if (!stream_info->free_streams_command) 575 goto cleanup_ctx; 576 577 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); 578 579 /* Allocate rings for all the streams that the driver will use, 580 * and add their segment DMA addresses to the radix tree. 581 * Stream 0 is reserved. 582 */ 583 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 584 stream_info->stream_rings[cur_stream] = 585 xhci_ring_alloc(xhci, 1, true, mem_flags); 586 cur_ring = stream_info->stream_rings[cur_stream]; 587 if (!cur_ring) 588 goto cleanup_rings; 589 cur_ring->stream_id = cur_stream; 590 /* Set deq ptr, cycle bit, and stream context type */ 591 addr = cur_ring->first_seg->dma | 592 SCT_FOR_CTX(SCT_PRI_TR) | 593 cur_ring->cycle_state; 594 stream_info->stream_ctx_array[cur_stream].stream_ring = addr; 595 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", 596 cur_stream, (unsigned long long) addr); 597 598 key = (unsigned long) 599 (cur_ring->first_seg->dma >> SEGMENT_SHIFT); 600 ret = radix_tree_insert(&stream_info->trb_address_map, 601 key, cur_ring); 602 if (ret) { 603 xhci_ring_free(xhci, cur_ring); 604 stream_info->stream_rings[cur_stream] = NULL; 605 goto cleanup_rings; 606 } 607 } 608 /* Leave the other unused stream ring pointers in the stream context 609 * array initialized to zero. This will cause the xHC to give us an 610 * error if the device asks for a stream ID we don't have setup (if it 611 * was any other way, the host controller would assume the ring is 612 * "empty" and wait forever for data to be queued to that stream ID). 613 */ 614 #if XHCI_DEBUG 615 /* Do a little test on the radix tree to make sure it returns the 616 * correct values. 617 */ 618 if (xhci_test_radix_tree(xhci, num_streams, stream_info)) 619 goto cleanup_rings; 620 #endif 621 622 return stream_info; 623 624 cleanup_rings: 625 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 626 cur_ring = stream_info->stream_rings[cur_stream]; 627 if (cur_ring) { 628 addr = cur_ring->first_seg->dma; 629 radix_tree_delete(&stream_info->trb_address_map, 630 addr >> SEGMENT_SHIFT); 631 xhci_ring_free(xhci, cur_ring); 632 stream_info->stream_rings[cur_stream] = NULL; 633 } 634 } 635 xhci_free_command(xhci, stream_info->free_streams_command); 636 cleanup_ctx: 637 kfree(stream_info->stream_rings); 638 cleanup_info: 639 kfree(stream_info); 640 cleanup_trbs: 641 xhci->cmd_ring_reserved_trbs--; 642 return NULL; 643 } 644 /* 645 * Sets the MaxPStreams field and the Linear Stream Array field. 646 * Sets the dequeue pointer to the stream context array. 647 */ 648 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 649 struct xhci_ep_ctx *ep_ctx, 650 struct xhci_stream_info *stream_info) 651 { 652 u32 max_primary_streams; 653 /* MaxPStreams is the number of stream context array entries, not the 654 * number we're actually using. Must be in 2^(MaxPstreams + 1) format. 655 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. 656 */ 657 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; 658 xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n", 659 1 << (max_primary_streams + 1)); 660 ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK; 661 ep_ctx->ep_info |= EP_MAXPSTREAMS(max_primary_streams); 662 ep_ctx->ep_info |= EP_HAS_LSA; 663 ep_ctx->deq = stream_info->ctx_array_dma; 664 } 665 666 /* 667 * Sets the MaxPStreams field and the Linear Stream Array field to 0. 668 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, 669 * not at the beginning of the ring). 670 */ 671 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 672 struct xhci_ep_ctx *ep_ctx, 673 struct xhci_virt_ep *ep) 674 { 675 dma_addr_t addr; 676 ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK; 677 ep_ctx->ep_info &= ~EP_HAS_LSA; 678 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); 679 ep_ctx->deq = addr | ep->ring->cycle_state; 680 } 681 682 /* Frees all stream contexts associated with the endpoint, 683 * 684 * Caller should fix the endpoint context streams fields. 685 */ 686 void xhci_free_stream_info(struct xhci_hcd *xhci, 687 struct xhci_stream_info *stream_info) 688 { 689 int cur_stream; 690 struct xhci_ring *cur_ring; 691 dma_addr_t addr; 692 693 if (!stream_info) 694 return; 695 696 for (cur_stream = 1; cur_stream < stream_info->num_streams; 697 cur_stream++) { 698 cur_ring = stream_info->stream_rings[cur_stream]; 699 if (cur_ring) { 700 addr = cur_ring->first_seg->dma; 701 radix_tree_delete(&stream_info->trb_address_map, 702 addr >> SEGMENT_SHIFT); 703 xhci_ring_free(xhci, cur_ring); 704 stream_info->stream_rings[cur_stream] = NULL; 705 } 706 } 707 xhci_free_command(xhci, stream_info->free_streams_command); 708 xhci->cmd_ring_reserved_trbs--; 709 if (stream_info->stream_ctx_array) 710 xhci_free_stream_ctx(xhci, 711 stream_info->num_stream_ctxs, 712 stream_info->stream_ctx_array, 713 stream_info->ctx_array_dma); 714 715 if (stream_info) 716 kfree(stream_info->stream_rings); 717 kfree(stream_info); 718 } 719 720 721 /***************** Device context manipulation *************************/ 722 723 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, 724 struct xhci_virt_ep *ep) 725 { 726 init_timer(&ep->stop_cmd_timer); 727 ep->stop_cmd_timer.data = (unsigned long) ep; 728 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; 729 ep->xhci = xhci; 730 } 731 732 /* All the xhci_tds in the ring's TD list should be freed at this point */ 733 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) 734 { 735 struct xhci_virt_device *dev; 736 int i; 737 738 /* Slot ID 0 is reserved */ 739 if (slot_id == 0 || !xhci->devs[slot_id]) 740 return; 741 742 dev = xhci->devs[slot_id]; 743 xhci->dcbaa->dev_context_ptrs[slot_id] = 0; 744 if (!dev) 745 return; 746 747 for (i = 0; i < 31; ++i) { 748 if (dev->eps[i].ring) 749 xhci_ring_free(xhci, dev->eps[i].ring); 750 if (dev->eps[i].stream_info) 751 xhci_free_stream_info(xhci, 752 dev->eps[i].stream_info); 753 } 754 755 if (dev->ring_cache) { 756 for (i = 0; i < dev->num_rings_cached; i++) 757 xhci_ring_free(xhci, dev->ring_cache[i]); 758 kfree(dev->ring_cache); 759 } 760 761 if (dev->in_ctx) 762 xhci_free_container_ctx(xhci, dev->in_ctx); 763 if (dev->out_ctx) 764 xhci_free_container_ctx(xhci, dev->out_ctx); 765 766 kfree(xhci->devs[slot_id]); 767 xhci->devs[slot_id] = NULL; 768 } 769 770 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, 771 struct usb_device *udev, gfp_t flags) 772 { 773 struct xhci_virt_device *dev; 774 int i; 775 776 /* Slot ID 0 is reserved */ 777 if (slot_id == 0 || xhci->devs[slot_id]) { 778 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); 779 return 0; 780 } 781 782 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); 783 if (!xhci->devs[slot_id]) 784 return 0; 785 dev = xhci->devs[slot_id]; 786 787 /* Allocate the (output) device context that will be used in the HC. */ 788 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); 789 if (!dev->out_ctx) 790 goto fail; 791 792 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, 793 (unsigned long long)dev->out_ctx->dma); 794 795 /* Allocate the (input) device context for address device command */ 796 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); 797 if (!dev->in_ctx) 798 goto fail; 799 800 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, 801 (unsigned long long)dev->in_ctx->dma); 802 803 /* Initialize the cancellation list and watchdog timers for each ep */ 804 for (i = 0; i < 31; i++) { 805 xhci_init_endpoint_timer(xhci, &dev->eps[i]); 806 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); 807 } 808 809 /* Allocate endpoint 0 ring */ 810 dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags); 811 if (!dev->eps[0].ring) 812 goto fail; 813 814 /* Allocate pointers to the ring cache */ 815 dev->ring_cache = kzalloc( 816 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, 817 flags); 818 if (!dev->ring_cache) 819 goto fail; 820 dev->num_rings_cached = 0; 821 822 init_completion(&dev->cmd_completion); 823 INIT_LIST_HEAD(&dev->cmd_list); 824 825 /* Point to output device context in dcbaa. */ 826 xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma; 827 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", 828 slot_id, 829 &xhci->dcbaa->dev_context_ptrs[slot_id], 830 (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]); 831 832 return 1; 833 fail: 834 xhci_free_virt_device(xhci, slot_id); 835 return 0; 836 } 837 838 /* Setup an xHCI virtual device for a Set Address command */ 839 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) 840 { 841 struct xhci_virt_device *dev; 842 struct xhci_ep_ctx *ep0_ctx; 843 struct usb_device *top_dev; 844 struct xhci_slot_ctx *slot_ctx; 845 struct xhci_input_control_ctx *ctrl_ctx; 846 847 dev = xhci->devs[udev->slot_id]; 848 /* Slot ID 0 is reserved */ 849 if (udev->slot_id == 0 || !dev) { 850 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", 851 udev->slot_id); 852 return -EINVAL; 853 } 854 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); 855 ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx); 856 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); 857 858 /* 2) New slot context and endpoint 0 context are valid*/ 859 ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG; 860 861 /* 3) Only the control endpoint is valid - one endpoint context */ 862 slot_ctx->dev_info |= LAST_CTX(1); 863 864 slot_ctx->dev_info |= (u32) udev->route; 865 switch (udev->speed) { 866 case USB_SPEED_SUPER: 867 slot_ctx->dev_info |= (u32) SLOT_SPEED_SS; 868 break; 869 case USB_SPEED_HIGH: 870 slot_ctx->dev_info |= (u32) SLOT_SPEED_HS; 871 break; 872 case USB_SPEED_FULL: 873 slot_ctx->dev_info |= (u32) SLOT_SPEED_FS; 874 break; 875 case USB_SPEED_LOW: 876 slot_ctx->dev_info |= (u32) SLOT_SPEED_LS; 877 break; 878 case USB_SPEED_WIRELESS: 879 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); 880 return -EINVAL; 881 break; 882 default: 883 /* Speed was set earlier, this shouldn't happen. */ 884 BUG(); 885 } 886 /* Find the root hub port this device is under */ 887 for (top_dev = udev; top_dev->parent && top_dev->parent->parent; 888 top_dev = top_dev->parent) 889 /* Found device below root hub */; 890 slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum); 891 xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum); 892 893 /* Is this a LS/FS device under a HS hub? */ 894 if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) && 895 udev->tt) { 896 slot_ctx->tt_info = udev->tt->hub->slot_id; 897 slot_ctx->tt_info |= udev->ttport << 8; 898 if (udev->tt->multi) 899 slot_ctx->dev_info |= DEV_MTT; 900 } 901 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); 902 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); 903 904 /* Step 4 - ring already allocated */ 905 /* Step 5 */ 906 ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP); 907 /* 908 * XXX: Not sure about wireless USB devices. 909 */ 910 switch (udev->speed) { 911 case USB_SPEED_SUPER: 912 ep0_ctx->ep_info2 |= MAX_PACKET(512); 913 break; 914 case USB_SPEED_HIGH: 915 /* USB core guesses at a 64-byte max packet first for FS devices */ 916 case USB_SPEED_FULL: 917 ep0_ctx->ep_info2 |= MAX_PACKET(64); 918 break; 919 case USB_SPEED_LOW: 920 ep0_ctx->ep_info2 |= MAX_PACKET(8); 921 break; 922 case USB_SPEED_WIRELESS: 923 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); 924 return -EINVAL; 925 break; 926 default: 927 /* New speed? */ 928 BUG(); 929 } 930 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ 931 ep0_ctx->ep_info2 |= MAX_BURST(0); 932 ep0_ctx->ep_info2 |= ERROR_COUNT(3); 933 934 ep0_ctx->deq = 935 dev->eps[0].ring->first_seg->dma; 936 ep0_ctx->deq |= dev->eps[0].ring->cycle_state; 937 938 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ 939 940 return 0; 941 } 942 943 /* Return the polling or NAK interval. 944 * 945 * The polling interval is expressed in "microframes". If xHCI's Interval field 946 * is set to N, it will service the endpoint every 2^(Interval)*125us. 947 * 948 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval 949 * is set to 0. 950 */ 951 static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev, 952 struct usb_host_endpoint *ep) 953 { 954 unsigned int interval = 0; 955 956 switch (udev->speed) { 957 case USB_SPEED_HIGH: 958 /* Max NAK rate */ 959 if (usb_endpoint_xfer_control(&ep->desc) || 960 usb_endpoint_xfer_bulk(&ep->desc)) 961 interval = ep->desc.bInterval; 962 /* Fall through - SS and HS isoc/int have same decoding */ 963 case USB_SPEED_SUPER: 964 if (usb_endpoint_xfer_int(&ep->desc) || 965 usb_endpoint_xfer_isoc(&ep->desc)) { 966 if (ep->desc.bInterval == 0) 967 interval = 0; 968 else 969 interval = ep->desc.bInterval - 1; 970 if (interval > 15) 971 interval = 15; 972 if (interval != ep->desc.bInterval + 1) 973 dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n", 974 ep->desc.bEndpointAddress, 1 << interval); 975 } 976 break; 977 /* Convert bInterval (in 1-255 frames) to microframes and round down to 978 * nearest power of 2. 979 */ 980 case USB_SPEED_FULL: 981 case USB_SPEED_LOW: 982 if (usb_endpoint_xfer_int(&ep->desc) || 983 usb_endpoint_xfer_isoc(&ep->desc)) { 984 interval = fls(8*ep->desc.bInterval) - 1; 985 if (interval > 10) 986 interval = 10; 987 if (interval < 3) 988 interval = 3; 989 if ((1 << interval) != 8*ep->desc.bInterval) 990 dev_warn(&udev->dev, 991 "ep %#x - rounding interval" 992 " to %d microframes, " 993 "ep desc says %d microframes\n", 994 ep->desc.bEndpointAddress, 995 1 << interval, 996 8*ep->desc.bInterval); 997 } 998 break; 999 default: 1000 BUG(); 1001 } 1002 return EP_INTERVAL(interval); 1003 } 1004 1005 /* The "Mult" field in the endpoint context is only set for SuperSpeed devices. 1006 * High speed endpoint descriptors can define "the number of additional 1007 * transaction opportunities per microframe", but that goes in the Max Burst 1008 * endpoint context field. 1009 */ 1010 static inline u32 xhci_get_endpoint_mult(struct usb_device *udev, 1011 struct usb_host_endpoint *ep) 1012 { 1013 if (udev->speed != USB_SPEED_SUPER) 1014 return 0; 1015 return ep->ss_ep_comp.bmAttributes; 1016 } 1017 1018 static inline u32 xhci_get_endpoint_type(struct usb_device *udev, 1019 struct usb_host_endpoint *ep) 1020 { 1021 int in; 1022 u32 type; 1023 1024 in = usb_endpoint_dir_in(&ep->desc); 1025 if (usb_endpoint_xfer_control(&ep->desc)) { 1026 type = EP_TYPE(CTRL_EP); 1027 } else if (usb_endpoint_xfer_bulk(&ep->desc)) { 1028 if (in) 1029 type = EP_TYPE(BULK_IN_EP); 1030 else 1031 type = EP_TYPE(BULK_OUT_EP); 1032 } else if (usb_endpoint_xfer_isoc(&ep->desc)) { 1033 if (in) 1034 type = EP_TYPE(ISOC_IN_EP); 1035 else 1036 type = EP_TYPE(ISOC_OUT_EP); 1037 } else if (usb_endpoint_xfer_int(&ep->desc)) { 1038 if (in) 1039 type = EP_TYPE(INT_IN_EP); 1040 else 1041 type = EP_TYPE(INT_OUT_EP); 1042 } else { 1043 BUG(); 1044 } 1045 return type; 1046 } 1047 1048 /* Return the maximum endpoint service interval time (ESIT) payload. 1049 * Basically, this is the maxpacket size, multiplied by the burst size 1050 * and mult size. 1051 */ 1052 static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, 1053 struct usb_device *udev, 1054 struct usb_host_endpoint *ep) 1055 { 1056 int max_burst; 1057 int max_packet; 1058 1059 /* Only applies for interrupt or isochronous endpoints */ 1060 if (usb_endpoint_xfer_control(&ep->desc) || 1061 usb_endpoint_xfer_bulk(&ep->desc)) 1062 return 0; 1063 1064 if (udev->speed == USB_SPEED_SUPER) 1065 return ep->ss_ep_comp.wBytesPerInterval; 1066 1067 max_packet = ep->desc.wMaxPacketSize & 0x3ff; 1068 max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11; 1069 /* A 0 in max burst means 1 transfer per ESIT */ 1070 return max_packet * (max_burst + 1); 1071 } 1072 1073 /* Set up an endpoint with one ring segment. Do not allocate stream rings. 1074 * Drivers will have to call usb_alloc_streams() to do that. 1075 */ 1076 int xhci_endpoint_init(struct xhci_hcd *xhci, 1077 struct xhci_virt_device *virt_dev, 1078 struct usb_device *udev, 1079 struct usb_host_endpoint *ep, 1080 gfp_t mem_flags) 1081 { 1082 unsigned int ep_index; 1083 struct xhci_ep_ctx *ep_ctx; 1084 struct xhci_ring *ep_ring; 1085 unsigned int max_packet; 1086 unsigned int max_burst; 1087 u32 max_esit_payload; 1088 1089 ep_index = xhci_get_endpoint_index(&ep->desc); 1090 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); 1091 1092 /* Set up the endpoint ring */ 1093 virt_dev->eps[ep_index].new_ring = 1094 xhci_ring_alloc(xhci, 1, true, mem_flags); 1095 if (!virt_dev->eps[ep_index].new_ring) { 1096 /* Attempt to use the ring cache */ 1097 if (virt_dev->num_rings_cached == 0) 1098 return -ENOMEM; 1099 virt_dev->eps[ep_index].new_ring = 1100 virt_dev->ring_cache[virt_dev->num_rings_cached]; 1101 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; 1102 virt_dev->num_rings_cached--; 1103 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring); 1104 } 1105 ep_ring = virt_dev->eps[ep_index].new_ring; 1106 ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state; 1107 1108 ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep); 1109 ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep)); 1110 1111 /* FIXME dig Mult and streams info out of ep companion desc */ 1112 1113 /* Allow 3 retries for everything but isoc; 1114 * error count = 0 means infinite retries. 1115 */ 1116 if (!usb_endpoint_xfer_isoc(&ep->desc)) 1117 ep_ctx->ep_info2 = ERROR_COUNT(3); 1118 else 1119 ep_ctx->ep_info2 = ERROR_COUNT(1); 1120 1121 ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep); 1122 1123 /* Set the max packet size and max burst */ 1124 switch (udev->speed) { 1125 case USB_SPEED_SUPER: 1126 max_packet = ep->desc.wMaxPacketSize; 1127 ep_ctx->ep_info2 |= MAX_PACKET(max_packet); 1128 /* dig out max burst from ep companion desc */ 1129 max_packet = ep->ss_ep_comp.bMaxBurst; 1130 if (!max_packet) 1131 xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n"); 1132 ep_ctx->ep_info2 |= MAX_BURST(max_packet); 1133 break; 1134 case USB_SPEED_HIGH: 1135 /* bits 11:12 specify the number of additional transaction 1136 * opportunities per microframe (USB 2.0, section 9.6.6) 1137 */ 1138 if (usb_endpoint_xfer_isoc(&ep->desc) || 1139 usb_endpoint_xfer_int(&ep->desc)) { 1140 max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11; 1141 ep_ctx->ep_info2 |= MAX_BURST(max_burst); 1142 } 1143 /* Fall through */ 1144 case USB_SPEED_FULL: 1145 case USB_SPEED_LOW: 1146 max_packet = ep->desc.wMaxPacketSize & 0x3ff; 1147 ep_ctx->ep_info2 |= MAX_PACKET(max_packet); 1148 break; 1149 default: 1150 BUG(); 1151 } 1152 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); 1153 ep_ctx->tx_info = MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload); 1154 1155 /* 1156 * XXX no idea how to calculate the average TRB buffer length for bulk 1157 * endpoints, as the driver gives us no clue how big each scatter gather 1158 * list entry (or buffer) is going to be. 1159 * 1160 * For isochronous and interrupt endpoints, we set it to the max 1161 * available, until we have new API in the USB core to allow drivers to 1162 * declare how much bandwidth they actually need. 1163 * 1164 * Normally, it would be calculated by taking the total of the buffer 1165 * lengths in the TD and then dividing by the number of TRBs in a TD, 1166 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't 1167 * use Event Data TRBs, and we don't chain in a link TRB on short 1168 * transfers, we're basically dividing by 1. 1169 */ 1170 ep_ctx->tx_info |= AVG_TRB_LENGTH_FOR_EP(max_esit_payload); 1171 1172 /* FIXME Debug endpoint context */ 1173 return 0; 1174 } 1175 1176 void xhci_endpoint_zero(struct xhci_hcd *xhci, 1177 struct xhci_virt_device *virt_dev, 1178 struct usb_host_endpoint *ep) 1179 { 1180 unsigned int ep_index; 1181 struct xhci_ep_ctx *ep_ctx; 1182 1183 ep_index = xhci_get_endpoint_index(&ep->desc); 1184 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); 1185 1186 ep_ctx->ep_info = 0; 1187 ep_ctx->ep_info2 = 0; 1188 ep_ctx->deq = 0; 1189 ep_ctx->tx_info = 0; 1190 /* Don't free the endpoint ring until the set interface or configuration 1191 * request succeeds. 1192 */ 1193 } 1194 1195 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. 1196 * Useful when you want to change one particular aspect of the endpoint and then 1197 * issue a configure endpoint command. 1198 */ 1199 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1200 struct xhci_container_ctx *in_ctx, 1201 struct xhci_container_ctx *out_ctx, 1202 unsigned int ep_index) 1203 { 1204 struct xhci_ep_ctx *out_ep_ctx; 1205 struct xhci_ep_ctx *in_ep_ctx; 1206 1207 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); 1208 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); 1209 1210 in_ep_ctx->ep_info = out_ep_ctx->ep_info; 1211 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; 1212 in_ep_ctx->deq = out_ep_ctx->deq; 1213 in_ep_ctx->tx_info = out_ep_ctx->tx_info; 1214 } 1215 1216 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. 1217 * Useful when you want to change one particular aspect of the endpoint and then 1218 * issue a configure endpoint command. Only the context entries field matters, 1219 * but we'll copy the whole thing anyway. 1220 */ 1221 void xhci_slot_copy(struct xhci_hcd *xhci, 1222 struct xhci_container_ctx *in_ctx, 1223 struct xhci_container_ctx *out_ctx) 1224 { 1225 struct xhci_slot_ctx *in_slot_ctx; 1226 struct xhci_slot_ctx *out_slot_ctx; 1227 1228 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); 1229 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); 1230 1231 in_slot_ctx->dev_info = out_slot_ctx->dev_info; 1232 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; 1233 in_slot_ctx->tt_info = out_slot_ctx->tt_info; 1234 in_slot_ctx->dev_state = out_slot_ctx->dev_state; 1235 } 1236 1237 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ 1238 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) 1239 { 1240 int i; 1241 struct device *dev = xhci_to_hcd(xhci)->self.controller; 1242 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); 1243 1244 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp); 1245 1246 if (!num_sp) 1247 return 0; 1248 1249 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); 1250 if (!xhci->scratchpad) 1251 goto fail_sp; 1252 1253 xhci->scratchpad->sp_array = 1254 pci_alloc_consistent(to_pci_dev(dev), 1255 num_sp * sizeof(u64), 1256 &xhci->scratchpad->sp_dma); 1257 if (!xhci->scratchpad->sp_array) 1258 goto fail_sp2; 1259 1260 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); 1261 if (!xhci->scratchpad->sp_buffers) 1262 goto fail_sp3; 1263 1264 xhci->scratchpad->sp_dma_buffers = 1265 kzalloc(sizeof(dma_addr_t) * num_sp, flags); 1266 1267 if (!xhci->scratchpad->sp_dma_buffers) 1268 goto fail_sp4; 1269 1270 xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma; 1271 for (i = 0; i < num_sp; i++) { 1272 dma_addr_t dma; 1273 void *buf = pci_alloc_consistent(to_pci_dev(dev), 1274 xhci->page_size, &dma); 1275 if (!buf) 1276 goto fail_sp5; 1277 1278 xhci->scratchpad->sp_array[i] = dma; 1279 xhci->scratchpad->sp_buffers[i] = buf; 1280 xhci->scratchpad->sp_dma_buffers[i] = dma; 1281 } 1282 1283 return 0; 1284 1285 fail_sp5: 1286 for (i = i - 1; i >= 0; i--) { 1287 pci_free_consistent(to_pci_dev(dev), xhci->page_size, 1288 xhci->scratchpad->sp_buffers[i], 1289 xhci->scratchpad->sp_dma_buffers[i]); 1290 } 1291 kfree(xhci->scratchpad->sp_dma_buffers); 1292 1293 fail_sp4: 1294 kfree(xhci->scratchpad->sp_buffers); 1295 1296 fail_sp3: 1297 pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64), 1298 xhci->scratchpad->sp_array, 1299 xhci->scratchpad->sp_dma); 1300 1301 fail_sp2: 1302 kfree(xhci->scratchpad); 1303 xhci->scratchpad = NULL; 1304 1305 fail_sp: 1306 return -ENOMEM; 1307 } 1308 1309 static void scratchpad_free(struct xhci_hcd *xhci) 1310 { 1311 int num_sp; 1312 int i; 1313 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 1314 1315 if (!xhci->scratchpad) 1316 return; 1317 1318 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); 1319 1320 for (i = 0; i < num_sp; i++) { 1321 pci_free_consistent(pdev, xhci->page_size, 1322 xhci->scratchpad->sp_buffers[i], 1323 xhci->scratchpad->sp_dma_buffers[i]); 1324 } 1325 kfree(xhci->scratchpad->sp_dma_buffers); 1326 kfree(xhci->scratchpad->sp_buffers); 1327 pci_free_consistent(pdev, num_sp * sizeof(u64), 1328 xhci->scratchpad->sp_array, 1329 xhci->scratchpad->sp_dma); 1330 kfree(xhci->scratchpad); 1331 xhci->scratchpad = NULL; 1332 } 1333 1334 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1335 bool allocate_in_ctx, bool allocate_completion, 1336 gfp_t mem_flags) 1337 { 1338 struct xhci_command *command; 1339 1340 command = kzalloc(sizeof(*command), mem_flags); 1341 if (!command) 1342 return NULL; 1343 1344 if (allocate_in_ctx) { 1345 command->in_ctx = 1346 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, 1347 mem_flags); 1348 if (!command->in_ctx) { 1349 kfree(command); 1350 return NULL; 1351 } 1352 } 1353 1354 if (allocate_completion) { 1355 command->completion = 1356 kzalloc(sizeof(struct completion), mem_flags); 1357 if (!command->completion) { 1358 xhci_free_container_ctx(xhci, command->in_ctx); 1359 kfree(command); 1360 return NULL; 1361 } 1362 init_completion(command->completion); 1363 } 1364 1365 command->status = 0; 1366 INIT_LIST_HEAD(&command->cmd_list); 1367 return command; 1368 } 1369 1370 void xhci_free_command(struct xhci_hcd *xhci, 1371 struct xhci_command *command) 1372 { 1373 xhci_free_container_ctx(xhci, 1374 command->in_ctx); 1375 kfree(command->completion); 1376 kfree(command); 1377 } 1378 1379 void xhci_mem_cleanup(struct xhci_hcd *xhci) 1380 { 1381 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); 1382 int size; 1383 int i; 1384 1385 /* Free the Event Ring Segment Table and the actual Event Ring */ 1386 if (xhci->ir_set) { 1387 xhci_writel(xhci, 0, &xhci->ir_set->erst_size); 1388 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base); 1389 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue); 1390 } 1391 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); 1392 if (xhci->erst.entries) 1393 pci_free_consistent(pdev, size, 1394 xhci->erst.entries, xhci->erst.erst_dma_addr); 1395 xhci->erst.entries = NULL; 1396 xhci_dbg(xhci, "Freed ERST\n"); 1397 if (xhci->event_ring) 1398 xhci_ring_free(xhci, xhci->event_ring); 1399 xhci->event_ring = NULL; 1400 xhci_dbg(xhci, "Freed event ring\n"); 1401 1402 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring); 1403 if (xhci->cmd_ring) 1404 xhci_ring_free(xhci, xhci->cmd_ring); 1405 xhci->cmd_ring = NULL; 1406 xhci_dbg(xhci, "Freed command ring\n"); 1407 1408 for (i = 1; i < MAX_HC_SLOTS; ++i) 1409 xhci_free_virt_device(xhci, i); 1410 1411 if (xhci->segment_pool) 1412 dma_pool_destroy(xhci->segment_pool); 1413 xhci->segment_pool = NULL; 1414 xhci_dbg(xhci, "Freed segment pool\n"); 1415 1416 if (xhci->device_pool) 1417 dma_pool_destroy(xhci->device_pool); 1418 xhci->device_pool = NULL; 1419 xhci_dbg(xhci, "Freed device context pool\n"); 1420 1421 if (xhci->small_streams_pool) 1422 dma_pool_destroy(xhci->small_streams_pool); 1423 xhci->small_streams_pool = NULL; 1424 xhci_dbg(xhci, "Freed small stream array pool\n"); 1425 1426 if (xhci->medium_streams_pool) 1427 dma_pool_destroy(xhci->medium_streams_pool); 1428 xhci->medium_streams_pool = NULL; 1429 xhci_dbg(xhci, "Freed medium stream array pool\n"); 1430 1431 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr); 1432 if (xhci->dcbaa) 1433 pci_free_consistent(pdev, sizeof(*xhci->dcbaa), 1434 xhci->dcbaa, xhci->dcbaa->dma); 1435 xhci->dcbaa = NULL; 1436 1437 scratchpad_free(xhci); 1438 xhci->page_size = 0; 1439 xhci->page_shift = 0; 1440 } 1441 1442 static int xhci_test_trb_in_td(struct xhci_hcd *xhci, 1443 struct xhci_segment *input_seg, 1444 union xhci_trb *start_trb, 1445 union xhci_trb *end_trb, 1446 dma_addr_t input_dma, 1447 struct xhci_segment *result_seg, 1448 char *test_name, int test_number) 1449 { 1450 unsigned long long start_dma; 1451 unsigned long long end_dma; 1452 struct xhci_segment *seg; 1453 1454 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); 1455 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); 1456 1457 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); 1458 if (seg != result_seg) { 1459 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", 1460 test_name, test_number); 1461 xhci_warn(xhci, "Tested TRB math w/ seg %p and " 1462 "input DMA 0x%llx\n", 1463 input_seg, 1464 (unsigned long long) input_dma); 1465 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " 1466 "ending TRB %p (0x%llx DMA)\n", 1467 start_trb, start_dma, 1468 end_trb, end_dma); 1469 xhci_warn(xhci, "Expected seg %p, got seg %p\n", 1470 result_seg, seg); 1471 return -1; 1472 } 1473 return 0; 1474 } 1475 1476 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ 1477 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) 1478 { 1479 struct { 1480 dma_addr_t input_dma; 1481 struct xhci_segment *result_seg; 1482 } simple_test_vector [] = { 1483 /* A zeroed DMA field should fail */ 1484 { 0, NULL }, 1485 /* One TRB before the ring start should fail */ 1486 { xhci->event_ring->first_seg->dma - 16, NULL }, 1487 /* One byte before the ring start should fail */ 1488 { xhci->event_ring->first_seg->dma - 1, NULL }, 1489 /* Starting TRB should succeed */ 1490 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, 1491 /* Ending TRB should succeed */ 1492 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, 1493 xhci->event_ring->first_seg }, 1494 /* One byte after the ring end should fail */ 1495 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, 1496 /* One TRB after the ring end should fail */ 1497 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, 1498 /* An address of all ones should fail */ 1499 { (dma_addr_t) (~0), NULL }, 1500 }; 1501 struct { 1502 struct xhci_segment *input_seg; 1503 union xhci_trb *start_trb; 1504 union xhci_trb *end_trb; 1505 dma_addr_t input_dma; 1506 struct xhci_segment *result_seg; 1507 } complex_test_vector [] = { 1508 /* Test feeding a valid DMA address from a different ring */ 1509 { .input_seg = xhci->event_ring->first_seg, 1510 .start_trb = xhci->event_ring->first_seg->trbs, 1511 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1512 .input_dma = xhci->cmd_ring->first_seg->dma, 1513 .result_seg = NULL, 1514 }, 1515 /* Test feeding a valid end TRB from a different ring */ 1516 { .input_seg = xhci->event_ring->first_seg, 1517 .start_trb = xhci->event_ring->first_seg->trbs, 1518 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1519 .input_dma = xhci->cmd_ring->first_seg->dma, 1520 .result_seg = NULL, 1521 }, 1522 /* Test feeding a valid start and end TRB from a different ring */ 1523 { .input_seg = xhci->event_ring->first_seg, 1524 .start_trb = xhci->cmd_ring->first_seg->trbs, 1525 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1526 .input_dma = xhci->cmd_ring->first_seg->dma, 1527 .result_seg = NULL, 1528 }, 1529 /* TRB in this ring, but after this TD */ 1530 { .input_seg = xhci->event_ring->first_seg, 1531 .start_trb = &xhci->event_ring->first_seg->trbs[0], 1532 .end_trb = &xhci->event_ring->first_seg->trbs[3], 1533 .input_dma = xhci->event_ring->first_seg->dma + 4*16, 1534 .result_seg = NULL, 1535 }, 1536 /* TRB in this ring, but before this TD */ 1537 { .input_seg = xhci->event_ring->first_seg, 1538 .start_trb = &xhci->event_ring->first_seg->trbs[3], 1539 .end_trb = &xhci->event_ring->first_seg->trbs[6], 1540 .input_dma = xhci->event_ring->first_seg->dma + 2*16, 1541 .result_seg = NULL, 1542 }, 1543 /* TRB in this ring, but after this wrapped TD */ 1544 { .input_seg = xhci->event_ring->first_seg, 1545 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 1546 .end_trb = &xhci->event_ring->first_seg->trbs[1], 1547 .input_dma = xhci->event_ring->first_seg->dma + 2*16, 1548 .result_seg = NULL, 1549 }, 1550 /* TRB in this ring, but before this wrapped TD */ 1551 { .input_seg = xhci->event_ring->first_seg, 1552 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 1553 .end_trb = &xhci->event_ring->first_seg->trbs[1], 1554 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, 1555 .result_seg = NULL, 1556 }, 1557 /* TRB not in this ring, and we have a wrapped TD */ 1558 { .input_seg = xhci->event_ring->first_seg, 1559 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], 1560 .end_trb = &xhci->event_ring->first_seg->trbs[1], 1561 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, 1562 .result_seg = NULL, 1563 }, 1564 }; 1565 1566 unsigned int num_tests; 1567 int i, ret; 1568 1569 num_tests = sizeof(simple_test_vector) / sizeof(simple_test_vector[0]); 1570 for (i = 0; i < num_tests; i++) { 1571 ret = xhci_test_trb_in_td(xhci, 1572 xhci->event_ring->first_seg, 1573 xhci->event_ring->first_seg->trbs, 1574 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], 1575 simple_test_vector[i].input_dma, 1576 simple_test_vector[i].result_seg, 1577 "Simple", i); 1578 if (ret < 0) 1579 return ret; 1580 } 1581 1582 num_tests = sizeof(complex_test_vector) / sizeof(complex_test_vector[0]); 1583 for (i = 0; i < num_tests; i++) { 1584 ret = xhci_test_trb_in_td(xhci, 1585 complex_test_vector[i].input_seg, 1586 complex_test_vector[i].start_trb, 1587 complex_test_vector[i].end_trb, 1588 complex_test_vector[i].input_dma, 1589 complex_test_vector[i].result_seg, 1590 "Complex", i); 1591 if (ret < 0) 1592 return ret; 1593 } 1594 xhci_dbg(xhci, "TRB math tests passed.\n"); 1595 return 0; 1596 } 1597 1598 1599 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 1600 { 1601 dma_addr_t dma; 1602 struct device *dev = xhci_to_hcd(xhci)->self.controller; 1603 unsigned int val, val2; 1604 u64 val_64; 1605 struct xhci_segment *seg; 1606 u32 page_size; 1607 int i; 1608 1609 page_size = xhci_readl(xhci, &xhci->op_regs->page_size); 1610 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size); 1611 for (i = 0; i < 16; i++) { 1612 if ((0x1 & page_size) != 0) 1613 break; 1614 page_size = page_size >> 1; 1615 } 1616 if (i < 16) 1617 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024); 1618 else 1619 xhci_warn(xhci, "WARN: no supported page size\n"); 1620 /* Use 4K pages, since that's common and the minimum the HC supports */ 1621 xhci->page_shift = 12; 1622 xhci->page_size = 1 << xhci->page_shift; 1623 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024); 1624 1625 /* 1626 * Program the Number of Device Slots Enabled field in the CONFIG 1627 * register with the max value of slots the HC can handle. 1628 */ 1629 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1)); 1630 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n", 1631 (unsigned int) val); 1632 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg); 1633 val |= (val2 & ~HCS_SLOTS_MASK); 1634 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n", 1635 (unsigned int) val); 1636 xhci_writel(xhci, val, &xhci->op_regs->config_reg); 1637 1638 /* 1639 * Section 5.4.8 - doorbell array must be 1640 * "physically contiguous and 64-byte (cache line) aligned". 1641 */ 1642 xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev), 1643 sizeof(*xhci->dcbaa), &dma); 1644 if (!xhci->dcbaa) 1645 goto fail; 1646 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); 1647 xhci->dcbaa->dma = dma; 1648 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n", 1649 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); 1650 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); 1651 1652 /* 1653 * Initialize the ring segment pool. The ring must be a contiguous 1654 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 1655 * however, the command ring segment needs 64-byte aligned segments, 1656 * so we pick the greater alignment need. 1657 */ 1658 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, 1659 SEGMENT_SIZE, 64, xhci->page_size); 1660 1661 /* See Table 46 and Note on Figure 55 */ 1662 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, 1663 2112, 64, xhci->page_size); 1664 if (!xhci->segment_pool || !xhci->device_pool) 1665 goto fail; 1666 1667 /* Linear stream context arrays don't have any boundary restrictions, 1668 * and only need to be 16-byte aligned. 1669 */ 1670 xhci->small_streams_pool = 1671 dma_pool_create("xHCI 256 byte stream ctx arrays", 1672 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); 1673 xhci->medium_streams_pool = 1674 dma_pool_create("xHCI 1KB stream ctx arrays", 1675 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); 1676 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE 1677 * will be allocated with pci_alloc_consistent() 1678 */ 1679 1680 if (!xhci->small_streams_pool || !xhci->medium_streams_pool) 1681 goto fail; 1682 1683 /* Set up the command ring to have one segments for now. */ 1684 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags); 1685 if (!xhci->cmd_ring) 1686 goto fail; 1687 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring); 1688 xhci_dbg(xhci, "First segment DMA is 0x%llx\n", 1689 (unsigned long long)xhci->cmd_ring->first_seg->dma); 1690 1691 /* Set the address in the Command Ring Control register */ 1692 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1693 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | 1694 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | 1695 xhci->cmd_ring->cycle_state; 1696 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val); 1697 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); 1698 xhci_dbg_cmd_ptrs(xhci); 1699 1700 val = xhci_readl(xhci, &xhci->cap_regs->db_off); 1701 val &= DBOFF_MASK; 1702 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" 1703 " from cap regs base addr\n", val); 1704 xhci->dba = (void *) xhci->cap_regs + val; 1705 xhci_dbg_regs(xhci); 1706 xhci_print_run_regs(xhci); 1707 /* Set ir_set to interrupt register set 0 */ 1708 xhci->ir_set = (void *) xhci->run_regs->ir_set; 1709 1710 /* 1711 * Event ring setup: Allocate a normal ring, but also setup 1712 * the event ring segment table (ERST). Section 4.9.3. 1713 */ 1714 xhci_dbg(xhci, "// Allocating event ring\n"); 1715 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags); 1716 if (!xhci->event_ring) 1717 goto fail; 1718 if (xhci_check_trb_in_td_math(xhci, flags) < 0) 1719 goto fail; 1720 1721 xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev), 1722 sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma); 1723 if (!xhci->erst.entries) 1724 goto fail; 1725 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n", 1726 (unsigned long long)dma); 1727 1728 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); 1729 xhci->erst.num_entries = ERST_NUM_SEGS; 1730 xhci->erst.erst_dma_addr = dma; 1731 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n", 1732 xhci->erst.num_entries, 1733 xhci->erst.entries, 1734 (unsigned long long)xhci->erst.erst_dma_addr); 1735 1736 /* set ring base address and size for each segment table entry */ 1737 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { 1738 struct xhci_erst_entry *entry = &xhci->erst.entries[val]; 1739 entry->seg_addr = seg->dma; 1740 entry->seg_size = TRBS_PER_SEGMENT; 1741 entry->rsvd = 0; 1742 seg = seg->next; 1743 } 1744 1745 /* set ERST count with the number of entries in the segment table */ 1746 val = xhci_readl(xhci, &xhci->ir_set->erst_size); 1747 val &= ERST_SIZE_MASK; 1748 val |= ERST_NUM_SEGS; 1749 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n", 1750 val); 1751 xhci_writel(xhci, val, &xhci->ir_set->erst_size); 1752 1753 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n"); 1754 /* set the segment table base address */ 1755 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n", 1756 (unsigned long long)xhci->erst.erst_dma_addr); 1757 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); 1758 val_64 &= ERST_PTR_MASK; 1759 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); 1760 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); 1761 1762 /* Set the event ring dequeue address */ 1763 xhci_set_hc_event_deq(xhci); 1764 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); 1765 xhci_print_ir_set(xhci, xhci->ir_set, 0); 1766 1767 /* 1768 * XXX: Might need to set the Interrupter Moderation Register to 1769 * something other than the default (~1ms minimum between interrupts). 1770 * See section 5.5.1.2. 1771 */ 1772 init_completion(&xhci->addr_dev); 1773 for (i = 0; i < MAX_HC_SLOTS; ++i) 1774 xhci->devs[i] = NULL; 1775 1776 if (scratchpad_alloc(xhci, flags)) 1777 goto fail; 1778 1779 return 0; 1780 1781 fail: 1782 xhci_warn(xhci, "Couldn't initialize memory\n"); 1783 xhci_mem_cleanup(xhci); 1784 return -ENOMEM; 1785 } 1786