1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 24 #include <linux/slab.h> 25 #include <asm/unaligned.h> 26 27 #include "xhci.h" 28 #include "xhci-trace.h" 29 30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 32 PORT_RC | PORT_PLC | PORT_PE) 33 34 /* USB 3.0 BOS descriptor and a capability descriptor, combined */ 35 static u8 usb_bos_descriptor [] = { 36 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 37 USB_DT_BOS, /* __u8 bDescriptorType */ 38 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 39 0x1, /* __u8 bNumDeviceCaps */ 40 /* First device capability */ 41 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 43 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 44 0x00, /* bmAttributes, LTM off by default */ 45 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 46 0x03, /* bFunctionalitySupport, 47 USB 3.0 speed only */ 48 0x00, /* bU1DevExitLat, set later. */ 49 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 50 }; 51 52 53 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 54 struct usb_hub_descriptor *desc, int ports) 55 { 56 u16 temp; 57 58 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 59 desc->bHubContrCurrent = 0; 60 61 desc->bNbrPorts = ports; 62 temp = 0; 63 /* Bits 1:0 - support per-port power switching, or power always on */ 64 if (HCC_PPC(xhci->hcc_params)) 65 temp |= HUB_CHAR_INDV_PORT_LPSM; 66 else 67 temp |= HUB_CHAR_NO_LPSM; 68 /* Bit 2 - root hubs are not part of a compound device */ 69 /* Bits 4:3 - individual port over current protection */ 70 temp |= HUB_CHAR_INDV_PORT_OCPM; 71 /* Bits 6:5 - no TTs in root ports */ 72 /* Bit 7 - no port indicators */ 73 desc->wHubCharacteristics = cpu_to_le16(temp); 74 } 75 76 /* Fill in the USB 2.0 roothub descriptor */ 77 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 78 struct usb_hub_descriptor *desc) 79 { 80 int ports; 81 u16 temp; 82 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 83 u32 portsc; 84 unsigned int i; 85 86 ports = xhci->num_usb2_ports; 87 88 xhci_common_hub_descriptor(xhci, desc, ports); 89 desc->bDescriptorType = USB_DT_HUB; 90 temp = 1 + (ports / 8); 91 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 92 93 /* The Device Removable bits are reported on a byte granularity. 94 * If the port doesn't exist within that byte, the bit is set to 0. 95 */ 96 memset(port_removable, 0, sizeof(port_removable)); 97 for (i = 0; i < ports; i++) { 98 portsc = readl(xhci->usb2_ports[i]); 99 /* If a device is removable, PORTSC reports a 0, same as in the 100 * hub descriptor DeviceRemovable bits. 101 */ 102 if (portsc & PORT_DEV_REMOVE) 103 /* This math is hairy because bit 0 of DeviceRemovable 104 * is reserved, and bit 1 is for port 1, etc. 105 */ 106 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 107 } 108 109 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 110 * ports on it. The USB 2.0 specification says that there are two 111 * variable length fields at the end of the hub descriptor: 112 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 113 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 114 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 115 * 0xFF, so we initialize the both arrays (DeviceRemovable and 116 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 117 * set of ports that actually exist. 118 */ 119 memset(desc->u.hs.DeviceRemovable, 0xff, 120 sizeof(desc->u.hs.DeviceRemovable)); 121 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 122 sizeof(desc->u.hs.PortPwrCtrlMask)); 123 124 for (i = 0; i < (ports + 1 + 7) / 8; i++) 125 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 126 sizeof(__u8)); 127 } 128 129 /* Fill in the USB 3.0 roothub descriptor */ 130 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 131 struct usb_hub_descriptor *desc) 132 { 133 int ports; 134 u16 port_removable; 135 u32 portsc; 136 unsigned int i; 137 138 ports = xhci->num_usb3_ports; 139 xhci_common_hub_descriptor(xhci, desc, ports); 140 desc->bDescriptorType = USB_DT_SS_HUB; 141 desc->bDescLength = USB_DT_SS_HUB_SIZE; 142 143 /* header decode latency should be zero for roothubs, 144 * see section 4.23.5.2. 145 */ 146 desc->u.ss.bHubHdrDecLat = 0; 147 desc->u.ss.wHubDelay = 0; 148 149 port_removable = 0; 150 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 151 for (i = 0; i < ports; i++) { 152 portsc = readl(xhci->usb3_ports[i]); 153 if (portsc & PORT_DEV_REMOVE) 154 port_removable |= 1 << (i + 1); 155 } 156 157 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 158 } 159 160 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 161 struct usb_hub_descriptor *desc) 162 { 163 164 if (hcd->speed == HCD_USB3) 165 xhci_usb3_hub_descriptor(hcd, xhci, desc); 166 else 167 xhci_usb2_hub_descriptor(hcd, xhci, desc); 168 169 } 170 171 static unsigned int xhci_port_speed(unsigned int port_status) 172 { 173 if (DEV_LOWSPEED(port_status)) 174 return USB_PORT_STAT_LOW_SPEED; 175 if (DEV_HIGHSPEED(port_status)) 176 return USB_PORT_STAT_HIGH_SPEED; 177 /* 178 * FIXME: Yes, we should check for full speed, but the core uses that as 179 * a default in portspeed() in usb/core/hub.c (which is the only place 180 * USB_PORT_STAT_*_SPEED is used). 181 */ 182 return 0; 183 } 184 185 /* 186 * These bits are Read Only (RO) and should be saved and written to the 187 * registers: 0, 3, 10:13, 30 188 * connect status, over-current status, port speed, and device removable. 189 * connect status and port speed are also sticky - meaning they're in 190 * the AUX well and they aren't changed by a hot, warm, or cold reset. 191 */ 192 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 193 /* 194 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 195 * bits 5:8, 9, 14:15, 25:27 196 * link state, port power, port indicator state, "wake on" enable state 197 */ 198 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 199 /* 200 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 201 * bit 4 (port reset) 202 */ 203 #define XHCI_PORT_RW1S ((1<<4)) 204 /* 205 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 206 * bits 1, 17, 18, 19, 20, 21, 22, 23 207 * port enable/disable, and 208 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 209 * over-current, reset, link state, and L1 change 210 */ 211 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 212 /* 213 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 214 * latched in 215 */ 216 #define XHCI_PORT_RW ((1<<16)) 217 /* 218 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 219 * bits 2, 24, 28:31 220 */ 221 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 222 223 /* 224 * Given a port state, this function returns a value that would result in the 225 * port being in the same state, if the value was written to the port status 226 * control register. 227 * Save Read Only (RO) bits and save read/write bits where 228 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 229 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 230 */ 231 u32 xhci_port_state_to_neutral(u32 state) 232 { 233 /* Save read-only status and port state */ 234 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 235 } 236 237 /* 238 * find slot id based on port number. 239 * @port: The one-based port number from one of the two split roothubs. 240 */ 241 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 242 u16 port) 243 { 244 int slot_id; 245 int i; 246 enum usb_device_speed speed; 247 248 slot_id = 0; 249 for (i = 0; i < MAX_HC_SLOTS; i++) { 250 if (!xhci->devs[i]) 251 continue; 252 speed = xhci->devs[i]->udev->speed; 253 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 254 && xhci->devs[i]->fake_port == port) { 255 slot_id = i; 256 break; 257 } 258 } 259 260 return slot_id; 261 } 262 263 /* 264 * Stop device 265 * It issues stop endpoint command for EP 0 to 30. And wait the last command 266 * to complete. 267 * suspend will set to 1, if suspend bit need to set in command. 268 */ 269 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 270 { 271 struct xhci_virt_device *virt_dev; 272 struct xhci_command *cmd; 273 unsigned long flags; 274 int ret; 275 int i; 276 277 ret = 0; 278 virt_dev = xhci->devs[slot_id]; 279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 280 if (!cmd) { 281 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 282 return -ENOMEM; 283 } 284 285 spin_lock_irqsave(&xhci->lock, flags); 286 for (i = LAST_EP_INDEX; i > 0; i--) { 287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 288 struct xhci_command *command; 289 command = xhci_alloc_command(xhci, false, false, 290 GFP_NOWAIT); 291 if (!command) { 292 spin_unlock_irqrestore(&xhci->lock, flags); 293 xhci_free_command(xhci, cmd); 294 return -ENOMEM; 295 296 } 297 xhci_queue_stop_endpoint(xhci, command, slot_id, i, 298 suspend); 299 } 300 } 301 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 302 xhci_ring_cmd_db(xhci); 303 spin_unlock_irqrestore(&xhci->lock, flags); 304 305 /* Wait for last stop endpoint command to finish */ 306 wait_for_completion(cmd->completion); 307 308 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { 309 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 310 ret = -ETIME; 311 } 312 xhci_free_command(xhci, cmd); 313 return ret; 314 } 315 316 /* 317 * Ring device, it rings the all doorbells unconditionally. 318 */ 319 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 320 { 321 int i, s; 322 struct xhci_virt_ep *ep; 323 324 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 325 ep = &xhci->devs[slot_id]->eps[i]; 326 327 if (ep->ep_state & EP_HAS_STREAMS) { 328 for (s = 1; s < ep->stream_info->num_streams; s++) 329 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 330 } else if (ep->ring && ep->ring->dequeue) { 331 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 332 } 333 } 334 335 return; 336 } 337 338 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 339 u16 wIndex, __le32 __iomem *addr, u32 port_status) 340 { 341 /* Don't allow the USB core to disable SuperSpeed ports. */ 342 if (hcd->speed == HCD_USB3) { 343 xhci_dbg(xhci, "Ignoring request to disable " 344 "SuperSpeed port.\n"); 345 return; 346 } 347 348 /* Write 1 to disable the port */ 349 writel(port_status | PORT_PE, addr); 350 port_status = readl(addr); 351 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 352 wIndex, port_status); 353 } 354 355 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 356 u16 wIndex, __le32 __iomem *addr, u32 port_status) 357 { 358 char *port_change_bit; 359 u32 status; 360 361 switch (wValue) { 362 case USB_PORT_FEAT_C_RESET: 363 status = PORT_RC; 364 port_change_bit = "reset"; 365 break; 366 case USB_PORT_FEAT_C_BH_PORT_RESET: 367 status = PORT_WRC; 368 port_change_bit = "warm(BH) reset"; 369 break; 370 case USB_PORT_FEAT_C_CONNECTION: 371 status = PORT_CSC; 372 port_change_bit = "connect"; 373 break; 374 case USB_PORT_FEAT_C_OVER_CURRENT: 375 status = PORT_OCC; 376 port_change_bit = "over-current"; 377 break; 378 case USB_PORT_FEAT_C_ENABLE: 379 status = PORT_PEC; 380 port_change_bit = "enable/disable"; 381 break; 382 case USB_PORT_FEAT_C_SUSPEND: 383 status = PORT_PLC; 384 port_change_bit = "suspend/resume"; 385 break; 386 case USB_PORT_FEAT_C_PORT_LINK_STATE: 387 status = PORT_PLC; 388 port_change_bit = "link state"; 389 break; 390 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 391 status = PORT_CEC; 392 port_change_bit = "config error"; 393 break; 394 default: 395 /* Should never happen */ 396 return; 397 } 398 /* Change bits are all write 1 to clear */ 399 writel(port_status | status, addr); 400 port_status = readl(addr); 401 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 402 port_change_bit, wIndex, port_status); 403 } 404 405 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 406 { 407 int max_ports; 408 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 409 410 if (hcd->speed == HCD_USB3) { 411 max_ports = xhci->num_usb3_ports; 412 *port_array = xhci->usb3_ports; 413 } else { 414 max_ports = xhci->num_usb2_ports; 415 *port_array = xhci->usb2_ports; 416 } 417 418 return max_ports; 419 } 420 421 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 422 int port_id, u32 link_state) 423 { 424 u32 temp; 425 426 temp = readl(port_array[port_id]); 427 temp = xhci_port_state_to_neutral(temp); 428 temp &= ~PORT_PLS_MASK; 429 temp |= PORT_LINK_STROBE | link_state; 430 writel(temp, port_array[port_id]); 431 } 432 433 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 434 __le32 __iomem **port_array, int port_id, u16 wake_mask) 435 { 436 u32 temp; 437 438 temp = readl(port_array[port_id]); 439 temp = xhci_port_state_to_neutral(temp); 440 441 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 442 temp |= PORT_WKCONN_E; 443 else 444 temp &= ~PORT_WKCONN_E; 445 446 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 447 temp |= PORT_WKDISC_E; 448 else 449 temp &= ~PORT_WKDISC_E; 450 451 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 452 temp |= PORT_WKOC_E; 453 else 454 temp &= ~PORT_WKOC_E; 455 456 writel(temp, port_array[port_id]); 457 } 458 459 /* Test and clear port RWC bit */ 460 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 461 int port_id, u32 port_bit) 462 { 463 u32 temp; 464 465 temp = readl(port_array[port_id]); 466 if (temp & port_bit) { 467 temp = xhci_port_state_to_neutral(temp); 468 temp |= port_bit; 469 writel(temp, port_array[port_id]); 470 } 471 } 472 473 /* Updates Link Status for USB 2.1 port */ 474 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) 475 { 476 if ((status_reg & PORT_PLS_MASK) == XDEV_U2) 477 *status |= USB_PORT_STAT_L1; 478 } 479 480 /* Updates Link Status for super Speed port */ 481 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 482 u32 *status, u32 status_reg) 483 { 484 u32 pls = status_reg & PORT_PLS_MASK; 485 486 /* resume state is a xHCI internal state. 487 * Do not report it to usb core. 488 */ 489 if (pls == XDEV_RESUME) 490 return; 491 492 /* When the CAS bit is set then warm reset 493 * should be performed on port 494 */ 495 if (status_reg & PORT_CAS) { 496 /* The CAS bit can be set while the port is 497 * in any link state. 498 * Only roothubs have CAS bit, so we 499 * pretend to be in compliance mode 500 * unless we're already in compliance 501 * or the inactive state. 502 */ 503 if (pls != USB_SS_PORT_LS_COMP_MOD && 504 pls != USB_SS_PORT_LS_SS_INACTIVE) { 505 pls = USB_SS_PORT_LS_COMP_MOD; 506 } 507 /* Return also connection bit - 508 * hub state machine resets port 509 * when this bit is set. 510 */ 511 pls |= USB_PORT_STAT_CONNECTION; 512 } else { 513 /* 514 * If CAS bit isn't set but the Port is already at 515 * Compliance Mode, fake a connection so the USB core 516 * notices the Compliance state and resets the port. 517 * This resolves an issue generated by the SN65LVPE502CP 518 * in which sometimes the port enters compliance mode 519 * caused by a delay on the host-device negotiation. 520 */ 521 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 522 (pls == USB_SS_PORT_LS_COMP_MOD)) 523 pls |= USB_PORT_STAT_CONNECTION; 524 } 525 526 /* update status field */ 527 *status |= pls; 528 } 529 530 /* 531 * Function for Compliance Mode Quirk. 532 * 533 * This Function verifies if all xhc USB3 ports have entered U0, if so, 534 * the compliance mode timer is deleted. A port won't enter 535 * compliance mode if it has previously entered U0. 536 */ 537 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 538 u16 wIndex) 539 { 540 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); 541 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 542 543 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 544 return; 545 546 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 547 xhci->port_status_u0 |= 1 << wIndex; 548 if (xhci->port_status_u0 == all_ports_seen_u0) { 549 del_timer_sync(&xhci->comp_mode_recovery_timer); 550 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 551 "All USB3 ports have entered U0 already!"); 552 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 553 "Compliance Mode Recovery Timer Deleted."); 554 } 555 } 556 } 557 558 /* 559 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 560 * 3.0 hubs use. 561 * 562 * Possible side effects: 563 * - Mark a port as being done with device resume, 564 * and ring the endpoint doorbells. 565 * - Stop the Synopsys redriver Compliance Mode polling. 566 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 567 */ 568 static u32 xhci_get_port_status(struct usb_hcd *hcd, 569 struct xhci_bus_state *bus_state, 570 __le32 __iomem **port_array, 571 u16 wIndex, u32 raw_port_status, 572 unsigned long flags) 573 __releases(&xhci->lock) 574 __acquires(&xhci->lock) 575 { 576 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 577 u32 status = 0; 578 int slot_id; 579 580 /* wPortChange bits */ 581 if (raw_port_status & PORT_CSC) 582 status |= USB_PORT_STAT_C_CONNECTION << 16; 583 if (raw_port_status & PORT_PEC) 584 status |= USB_PORT_STAT_C_ENABLE << 16; 585 if ((raw_port_status & PORT_OCC)) 586 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 587 if ((raw_port_status & PORT_RC)) 588 status |= USB_PORT_STAT_C_RESET << 16; 589 /* USB3.0 only */ 590 if (hcd->speed == HCD_USB3) { 591 if ((raw_port_status & PORT_PLC)) 592 status |= USB_PORT_STAT_C_LINK_STATE << 16; 593 if ((raw_port_status & PORT_WRC)) 594 status |= USB_PORT_STAT_C_BH_RESET << 16; 595 if ((raw_port_status & PORT_CEC)) 596 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 597 } 598 599 if (hcd->speed != HCD_USB3) { 600 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 601 && (raw_port_status & PORT_POWER)) 602 status |= USB_PORT_STAT_SUSPEND; 603 } 604 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && 605 !DEV_SUPERSPEED(raw_port_status)) { 606 if ((raw_port_status & PORT_RESET) || 607 !(raw_port_status & PORT_PE)) 608 return 0xffffffff; 609 if (time_after_eq(jiffies, 610 bus_state->resume_done[wIndex])) { 611 int time_left; 612 613 xhci_dbg(xhci, "Resume USB2 port %d\n", 614 wIndex + 1); 615 bus_state->resume_done[wIndex] = 0; 616 clear_bit(wIndex, &bus_state->resuming_ports); 617 618 set_bit(wIndex, &bus_state->rexit_ports); 619 xhci_set_link_state(xhci, port_array, wIndex, 620 XDEV_U0); 621 622 spin_unlock_irqrestore(&xhci->lock, flags); 623 time_left = wait_for_completion_timeout( 624 &bus_state->rexit_done[wIndex], 625 msecs_to_jiffies( 626 XHCI_MAX_REXIT_TIMEOUT)); 627 spin_lock_irqsave(&xhci->lock, flags); 628 629 if (time_left) { 630 slot_id = xhci_find_slot_id_by_port(hcd, 631 xhci, wIndex + 1); 632 if (!slot_id) { 633 xhci_dbg(xhci, "slot_id is zero\n"); 634 return 0xffffffff; 635 } 636 xhci_ring_device(xhci, slot_id); 637 } else { 638 int port_status = readl(port_array[wIndex]); 639 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", 640 XHCI_MAX_REXIT_TIMEOUT, 641 port_status); 642 status |= USB_PORT_STAT_SUSPEND; 643 clear_bit(wIndex, &bus_state->rexit_ports); 644 } 645 646 bus_state->port_c_suspend |= 1 << wIndex; 647 bus_state->suspended_ports &= ~(1 << wIndex); 648 } else { 649 /* 650 * The resume has been signaling for less than 651 * 20ms. Report the port status as SUSPEND, 652 * let the usbcore check port status again 653 * and clear resume signaling later. 654 */ 655 status |= USB_PORT_STAT_SUSPEND; 656 } 657 } 658 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 659 && (raw_port_status & PORT_POWER) 660 && (bus_state->suspended_ports & (1 << wIndex))) { 661 bus_state->suspended_ports &= ~(1 << wIndex); 662 if (hcd->speed != HCD_USB3) 663 bus_state->port_c_suspend |= 1 << wIndex; 664 } 665 if (raw_port_status & PORT_CONNECT) { 666 status |= USB_PORT_STAT_CONNECTION; 667 status |= xhci_port_speed(raw_port_status); 668 } 669 if (raw_port_status & PORT_PE) 670 status |= USB_PORT_STAT_ENABLE; 671 if (raw_port_status & PORT_OC) 672 status |= USB_PORT_STAT_OVERCURRENT; 673 if (raw_port_status & PORT_RESET) 674 status |= USB_PORT_STAT_RESET; 675 if (raw_port_status & PORT_POWER) { 676 if (hcd->speed == HCD_USB3) 677 status |= USB_SS_PORT_STAT_POWER; 678 else 679 status |= USB_PORT_STAT_POWER; 680 } 681 /* Update Port Link State */ 682 if (hcd->speed == HCD_USB3) { 683 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); 684 /* 685 * Verify if all USB3 Ports Have entered U0 already. 686 * Delete Compliance Mode Timer if so. 687 */ 688 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); 689 } else { 690 xhci_hub_report_usb2_link_state(&status, raw_port_status); 691 } 692 if (bus_state->port_c_suspend & (1 << wIndex)) 693 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 694 695 return status; 696 } 697 698 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 699 u16 wIndex, char *buf, u16 wLength) 700 { 701 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 702 int max_ports; 703 unsigned long flags; 704 u32 temp, status; 705 int retval = 0; 706 __le32 __iomem **port_array; 707 int slot_id; 708 struct xhci_bus_state *bus_state; 709 u16 link_state = 0; 710 u16 wake_mask = 0; 711 u16 timeout = 0; 712 713 max_ports = xhci_get_ports(hcd, &port_array); 714 bus_state = &xhci->bus_state[hcd_index(hcd)]; 715 716 spin_lock_irqsave(&xhci->lock, flags); 717 switch (typeReq) { 718 case GetHubStatus: 719 /* No power source, over-current reported per port */ 720 memset(buf, 0, 4); 721 break; 722 case GetHubDescriptor: 723 /* Check to make sure userspace is asking for the USB 3.0 hub 724 * descriptor for the USB 3.0 roothub. If not, we stall the 725 * endpoint, like external hubs do. 726 */ 727 if (hcd->speed == HCD_USB3 && 728 (wLength < USB_DT_SS_HUB_SIZE || 729 wValue != (USB_DT_SS_HUB << 8))) { 730 xhci_dbg(xhci, "Wrong hub descriptor type for " 731 "USB 3.0 roothub.\n"); 732 goto error; 733 } 734 xhci_hub_descriptor(hcd, xhci, 735 (struct usb_hub_descriptor *) buf); 736 break; 737 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 738 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 739 goto error; 740 741 if (hcd->speed != HCD_USB3) 742 goto error; 743 744 /* Set the U1 and U2 exit latencies. */ 745 memcpy(buf, &usb_bos_descriptor, 746 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 747 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 748 temp = readl(&xhci->cap_regs->hcs_params3); 749 buf[12] = HCS_U1_LATENCY(temp); 750 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 751 } 752 753 /* Indicate whether the host has LTM support. */ 754 temp = readl(&xhci->cap_regs->hcc_params); 755 if (HCC_LTC(temp)) 756 buf[8] |= USB_LTM_SUPPORT; 757 758 spin_unlock_irqrestore(&xhci->lock, flags); 759 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 760 case GetPortStatus: 761 if (!wIndex || wIndex > max_ports) 762 goto error; 763 wIndex--; 764 temp = readl(port_array[wIndex]); 765 if (temp == 0xffffffff) { 766 retval = -ENODEV; 767 break; 768 } 769 status = xhci_get_port_status(hcd, bus_state, port_array, 770 wIndex, temp, flags); 771 if (status == 0xffffffff) 772 goto error; 773 774 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", 775 wIndex, temp); 776 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 777 778 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 779 break; 780 case SetPortFeature: 781 if (wValue == USB_PORT_FEAT_LINK_STATE) 782 link_state = (wIndex & 0xff00) >> 3; 783 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 784 wake_mask = wIndex & 0xff00; 785 /* The MSB of wIndex is the U1/U2 timeout */ 786 timeout = (wIndex & 0xff00) >> 8; 787 wIndex &= 0xff; 788 if (!wIndex || wIndex > max_ports) 789 goto error; 790 wIndex--; 791 temp = readl(port_array[wIndex]); 792 if (temp == 0xffffffff) { 793 retval = -ENODEV; 794 break; 795 } 796 temp = xhci_port_state_to_neutral(temp); 797 /* FIXME: What new port features do we need to support? */ 798 switch (wValue) { 799 case USB_PORT_FEAT_SUSPEND: 800 temp = readl(port_array[wIndex]); 801 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 802 /* Resume the port to U0 first */ 803 xhci_set_link_state(xhci, port_array, wIndex, 804 XDEV_U0); 805 spin_unlock_irqrestore(&xhci->lock, flags); 806 msleep(10); 807 spin_lock_irqsave(&xhci->lock, flags); 808 } 809 /* In spec software should not attempt to suspend 810 * a port unless the port reports that it is in the 811 * enabled (PED = ‘1’,PLS < ‘3’) state. 812 */ 813 temp = readl(port_array[wIndex]); 814 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 815 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 816 xhci_warn(xhci, "USB core suspending device " 817 "not in U0/U1/U2.\n"); 818 goto error; 819 } 820 821 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 822 wIndex + 1); 823 if (!slot_id) { 824 xhci_warn(xhci, "slot_id is zero\n"); 825 goto error; 826 } 827 /* unlock to execute stop endpoint commands */ 828 spin_unlock_irqrestore(&xhci->lock, flags); 829 xhci_stop_device(xhci, slot_id, 1); 830 spin_lock_irqsave(&xhci->lock, flags); 831 832 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 833 834 spin_unlock_irqrestore(&xhci->lock, flags); 835 msleep(10); /* wait device to enter */ 836 spin_lock_irqsave(&xhci->lock, flags); 837 838 temp = readl(port_array[wIndex]); 839 bus_state->suspended_ports |= 1 << wIndex; 840 break; 841 case USB_PORT_FEAT_LINK_STATE: 842 temp = readl(port_array[wIndex]); 843 844 /* Disable port */ 845 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 846 xhci_dbg(xhci, "Disable port %d\n", wIndex); 847 temp = xhci_port_state_to_neutral(temp); 848 /* 849 * Clear all change bits, so that we get a new 850 * connection event. 851 */ 852 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 853 PORT_OCC | PORT_RC | PORT_PLC | 854 PORT_CEC; 855 writel(temp | PORT_PE, port_array[wIndex]); 856 temp = readl(port_array[wIndex]); 857 break; 858 } 859 860 /* Put link in RxDetect (enable port) */ 861 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 862 xhci_dbg(xhci, "Enable port %d\n", wIndex); 863 xhci_set_link_state(xhci, port_array, wIndex, 864 link_state); 865 temp = readl(port_array[wIndex]); 866 break; 867 } 868 869 /* Software should not attempt to set 870 * port link state above '3' (U3) and the port 871 * must be enabled. 872 */ 873 if ((temp & PORT_PE) == 0 || 874 (link_state > USB_SS_PORT_LS_U3)) { 875 xhci_warn(xhci, "Cannot set link state.\n"); 876 goto error; 877 } 878 879 if (link_state == USB_SS_PORT_LS_U3) { 880 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 881 wIndex + 1); 882 if (slot_id) { 883 /* unlock to execute stop endpoint 884 * commands */ 885 spin_unlock_irqrestore(&xhci->lock, 886 flags); 887 xhci_stop_device(xhci, slot_id, 1); 888 spin_lock_irqsave(&xhci->lock, flags); 889 } 890 } 891 892 xhci_set_link_state(xhci, port_array, wIndex, 893 link_state); 894 895 spin_unlock_irqrestore(&xhci->lock, flags); 896 msleep(20); /* wait device to enter */ 897 spin_lock_irqsave(&xhci->lock, flags); 898 899 temp = readl(port_array[wIndex]); 900 if (link_state == USB_SS_PORT_LS_U3) 901 bus_state->suspended_ports |= 1 << wIndex; 902 break; 903 case USB_PORT_FEAT_POWER: 904 /* 905 * Turn on ports, even if there isn't per-port switching. 906 * HC will report connect events even before this is set. 907 * However, hub_wq will ignore the roothub events until 908 * the roothub is registered. 909 */ 910 writel(temp | PORT_POWER, port_array[wIndex]); 911 912 temp = readl(port_array[wIndex]); 913 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 914 915 spin_unlock_irqrestore(&xhci->lock, flags); 916 temp = usb_acpi_power_manageable(hcd->self.root_hub, 917 wIndex); 918 if (temp) 919 usb_acpi_set_power_state(hcd->self.root_hub, 920 wIndex, true); 921 spin_lock_irqsave(&xhci->lock, flags); 922 break; 923 case USB_PORT_FEAT_RESET: 924 temp = (temp | PORT_RESET); 925 writel(temp, port_array[wIndex]); 926 927 temp = readl(port_array[wIndex]); 928 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 929 break; 930 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 931 xhci_set_remote_wake_mask(xhci, port_array, 932 wIndex, wake_mask); 933 temp = readl(port_array[wIndex]); 934 xhci_dbg(xhci, "set port remote wake mask, " 935 "actual port %d status = 0x%x\n", 936 wIndex, temp); 937 break; 938 case USB_PORT_FEAT_BH_PORT_RESET: 939 temp |= PORT_WR; 940 writel(temp, port_array[wIndex]); 941 942 temp = readl(port_array[wIndex]); 943 break; 944 case USB_PORT_FEAT_U1_TIMEOUT: 945 if (hcd->speed != HCD_USB3) 946 goto error; 947 temp = readl(port_array[wIndex] + PORTPMSC); 948 temp &= ~PORT_U1_TIMEOUT_MASK; 949 temp |= PORT_U1_TIMEOUT(timeout); 950 writel(temp, port_array[wIndex] + PORTPMSC); 951 break; 952 case USB_PORT_FEAT_U2_TIMEOUT: 953 if (hcd->speed != HCD_USB3) 954 goto error; 955 temp = readl(port_array[wIndex] + PORTPMSC); 956 temp &= ~PORT_U2_TIMEOUT_MASK; 957 temp |= PORT_U2_TIMEOUT(timeout); 958 writel(temp, port_array[wIndex] + PORTPMSC); 959 break; 960 default: 961 goto error; 962 } 963 /* unblock any posted writes */ 964 temp = readl(port_array[wIndex]); 965 break; 966 case ClearPortFeature: 967 if (!wIndex || wIndex > max_ports) 968 goto error; 969 wIndex--; 970 temp = readl(port_array[wIndex]); 971 if (temp == 0xffffffff) { 972 retval = -ENODEV; 973 break; 974 } 975 /* FIXME: What new port features do we need to support? */ 976 temp = xhci_port_state_to_neutral(temp); 977 switch (wValue) { 978 case USB_PORT_FEAT_SUSPEND: 979 temp = readl(port_array[wIndex]); 980 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 981 xhci_dbg(xhci, "PORTSC %04x\n", temp); 982 if (temp & PORT_RESET) 983 goto error; 984 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 985 if ((temp & PORT_PE) == 0) 986 goto error; 987 988 xhci_set_link_state(xhci, port_array, wIndex, 989 XDEV_RESUME); 990 spin_unlock_irqrestore(&xhci->lock, flags); 991 msleep(20); 992 spin_lock_irqsave(&xhci->lock, flags); 993 xhci_set_link_state(xhci, port_array, wIndex, 994 XDEV_U0); 995 } 996 bus_state->port_c_suspend |= 1 << wIndex; 997 998 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 999 wIndex + 1); 1000 if (!slot_id) { 1001 xhci_dbg(xhci, "slot_id is zero\n"); 1002 goto error; 1003 } 1004 xhci_ring_device(xhci, slot_id); 1005 break; 1006 case USB_PORT_FEAT_C_SUSPEND: 1007 bus_state->port_c_suspend &= ~(1 << wIndex); 1008 case USB_PORT_FEAT_C_RESET: 1009 case USB_PORT_FEAT_C_BH_PORT_RESET: 1010 case USB_PORT_FEAT_C_CONNECTION: 1011 case USB_PORT_FEAT_C_OVER_CURRENT: 1012 case USB_PORT_FEAT_C_ENABLE: 1013 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1014 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1015 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1016 port_array[wIndex], temp); 1017 break; 1018 case USB_PORT_FEAT_ENABLE: 1019 xhci_disable_port(hcd, xhci, wIndex, 1020 port_array[wIndex], temp); 1021 break; 1022 case USB_PORT_FEAT_POWER: 1023 writel(temp & ~PORT_POWER, port_array[wIndex]); 1024 1025 spin_unlock_irqrestore(&xhci->lock, flags); 1026 temp = usb_acpi_power_manageable(hcd->self.root_hub, 1027 wIndex); 1028 if (temp) 1029 usb_acpi_set_power_state(hcd->self.root_hub, 1030 wIndex, false); 1031 spin_lock_irqsave(&xhci->lock, flags); 1032 break; 1033 default: 1034 goto error; 1035 } 1036 break; 1037 default: 1038 error: 1039 /* "stall" on error */ 1040 retval = -EPIPE; 1041 } 1042 spin_unlock_irqrestore(&xhci->lock, flags); 1043 return retval; 1044 } 1045 1046 /* 1047 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1048 * Ports are 0-indexed from the HCD point of view, 1049 * and 1-indexed from the USB core pointer of view. 1050 * 1051 * Note that the status change bits will be cleared as soon as a port status 1052 * change event is generated, so we use the saved status from that event. 1053 */ 1054 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1055 { 1056 unsigned long flags; 1057 u32 temp, status; 1058 u32 mask; 1059 int i, retval; 1060 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1061 int max_ports; 1062 __le32 __iomem **port_array; 1063 struct xhci_bus_state *bus_state; 1064 bool reset_change = false; 1065 1066 max_ports = xhci_get_ports(hcd, &port_array); 1067 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1068 1069 /* Initial status is no changes */ 1070 retval = (max_ports + 8) / 8; 1071 memset(buf, 0, retval); 1072 1073 /* 1074 * Inform the usbcore about resume-in-progress by returning 1075 * a non-zero value even if there are no status changes. 1076 */ 1077 status = bus_state->resuming_ports; 1078 1079 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1080 1081 spin_lock_irqsave(&xhci->lock, flags); 1082 /* For each port, did anything change? If so, set that bit in buf. */ 1083 for (i = 0; i < max_ports; i++) { 1084 temp = readl(port_array[i]); 1085 if (temp == 0xffffffff) { 1086 retval = -ENODEV; 1087 break; 1088 } 1089 if ((temp & mask) != 0 || 1090 (bus_state->port_c_suspend & 1 << i) || 1091 (bus_state->resume_done[i] && time_after_eq( 1092 jiffies, bus_state->resume_done[i]))) { 1093 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1094 status = 1; 1095 } 1096 if ((temp & PORT_RC)) 1097 reset_change = true; 1098 } 1099 if (!status && !reset_change) { 1100 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); 1101 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1102 } 1103 spin_unlock_irqrestore(&xhci->lock, flags); 1104 return status ? retval : 0; 1105 } 1106 1107 #ifdef CONFIG_PM 1108 1109 int xhci_bus_suspend(struct usb_hcd *hcd) 1110 { 1111 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1112 int max_ports, port_index; 1113 __le32 __iomem **port_array; 1114 struct xhci_bus_state *bus_state; 1115 unsigned long flags; 1116 1117 max_ports = xhci_get_ports(hcd, &port_array); 1118 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1119 1120 spin_lock_irqsave(&xhci->lock, flags); 1121 1122 if (hcd->self.root_hub->do_remote_wakeup) { 1123 if (bus_state->resuming_ports) { 1124 spin_unlock_irqrestore(&xhci->lock, flags); 1125 xhci_dbg(xhci, "suspend failed because " 1126 "a port is resuming\n"); 1127 return -EBUSY; 1128 } 1129 } 1130 1131 port_index = max_ports; 1132 bus_state->bus_suspended = 0; 1133 while (port_index--) { 1134 /* suspend the port if the port is not suspended */ 1135 u32 t1, t2; 1136 int slot_id; 1137 1138 t1 = readl(port_array[port_index]); 1139 t2 = xhci_port_state_to_neutral(t1); 1140 1141 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 1142 xhci_dbg(xhci, "port %d not suspended\n", port_index); 1143 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1144 port_index + 1); 1145 if (slot_id) { 1146 spin_unlock_irqrestore(&xhci->lock, flags); 1147 xhci_stop_device(xhci, slot_id, 1); 1148 spin_lock_irqsave(&xhci->lock, flags); 1149 } 1150 t2 &= ~PORT_PLS_MASK; 1151 t2 |= PORT_LINK_STROBE | XDEV_U3; 1152 set_bit(port_index, &bus_state->bus_suspended); 1153 } 1154 /* USB core sets remote wake mask for USB 3.0 hubs, 1155 * including the USB 3.0 roothub, but only if CONFIG_PM 1156 * is enabled, so also enable remote wake here. 1157 */ 1158 if (hcd->self.root_hub->do_remote_wakeup) { 1159 if (t1 & PORT_CONNECT) { 1160 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1161 t2 &= ~PORT_WKCONN_E; 1162 } else { 1163 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1164 t2 &= ~PORT_WKDISC_E; 1165 } 1166 } else 1167 t2 &= ~PORT_WAKE_BITS; 1168 1169 t1 = xhci_port_state_to_neutral(t1); 1170 if (t1 != t2) 1171 writel(t2, port_array[port_index]); 1172 } 1173 hcd->state = HC_STATE_SUSPENDED; 1174 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1175 spin_unlock_irqrestore(&xhci->lock, flags); 1176 return 0; 1177 } 1178 1179 int xhci_bus_resume(struct usb_hcd *hcd) 1180 { 1181 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1182 int max_ports, port_index; 1183 __le32 __iomem **port_array; 1184 struct xhci_bus_state *bus_state; 1185 u32 temp; 1186 unsigned long flags; 1187 1188 max_ports = xhci_get_ports(hcd, &port_array); 1189 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1190 1191 if (time_before(jiffies, bus_state->next_statechange)) 1192 msleep(5); 1193 1194 spin_lock_irqsave(&xhci->lock, flags); 1195 if (!HCD_HW_ACCESSIBLE(hcd)) { 1196 spin_unlock_irqrestore(&xhci->lock, flags); 1197 return -ESHUTDOWN; 1198 } 1199 1200 /* delay the irqs */ 1201 temp = readl(&xhci->op_regs->command); 1202 temp &= ~CMD_EIE; 1203 writel(temp, &xhci->op_regs->command); 1204 1205 port_index = max_ports; 1206 while (port_index--) { 1207 /* Check whether need resume ports. If needed 1208 resume port and disable remote wakeup */ 1209 u32 temp; 1210 int slot_id; 1211 1212 temp = readl(port_array[port_index]); 1213 if (DEV_SUPERSPEED(temp)) 1214 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1215 else 1216 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 1217 if (test_bit(port_index, &bus_state->bus_suspended) && 1218 (temp & PORT_PLS_MASK)) { 1219 if (DEV_SUPERSPEED(temp)) { 1220 xhci_set_link_state(xhci, port_array, 1221 port_index, XDEV_U0); 1222 } else { 1223 xhci_set_link_state(xhci, port_array, 1224 port_index, XDEV_RESUME); 1225 1226 spin_unlock_irqrestore(&xhci->lock, flags); 1227 msleep(20); 1228 spin_lock_irqsave(&xhci->lock, flags); 1229 1230 xhci_set_link_state(xhci, port_array, 1231 port_index, XDEV_U0); 1232 } 1233 /* wait for the port to enter U0 and report port link 1234 * state change. 1235 */ 1236 spin_unlock_irqrestore(&xhci->lock, flags); 1237 msleep(20); 1238 spin_lock_irqsave(&xhci->lock, flags); 1239 1240 /* Clear PLC */ 1241 xhci_test_and_clear_bit(xhci, port_array, port_index, 1242 PORT_PLC); 1243 1244 slot_id = xhci_find_slot_id_by_port(hcd, 1245 xhci, port_index + 1); 1246 if (slot_id) 1247 xhci_ring_device(xhci, slot_id); 1248 } else 1249 writel(temp, port_array[port_index]); 1250 } 1251 1252 (void) readl(&xhci->op_regs->command); 1253 1254 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1255 /* re-enable irqs */ 1256 temp = readl(&xhci->op_regs->command); 1257 temp |= CMD_EIE; 1258 writel(temp, &xhci->op_regs->command); 1259 temp = readl(&xhci->op_regs->command); 1260 1261 spin_unlock_irqrestore(&xhci->lock, flags); 1262 return 0; 1263 } 1264 1265 #endif /* CONFIG_PM */ 1266