1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 12 #include <linux/slab.h> 13 #include <linux/unaligned.h> 14 #include <linux/bitfield.h> 15 #include <linux/pci.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 20 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 21 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 22 PORT_RC | PORT_PLC | PORT_PE) 23 24 /* Default sublink speed attribute of each lane */ 25 static u32 ssp_cap_default_ssa[] = { 26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 34 }; 35 36 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, 37 u16 wLength) 38 { 39 struct usb_bos_descriptor *bos; 40 struct usb_ss_cap_descriptor *ss_cap; 41 struct usb_ssp_cap_descriptor *ssp_cap; 42 struct xhci_port_cap *port_cap = NULL; 43 u16 bcdUSB; 44 u32 reg; 45 u32 min_rate = 0; 46 u8 min_ssid; 47 u8 ssac; 48 u8 ssic; 49 int offset; 50 int i; 51 52 /* BOS descriptor */ 53 bos = (struct usb_bos_descriptor *)buf; 54 bos->bLength = USB_DT_BOS_SIZE; 55 bos->bDescriptorType = USB_DT_BOS; 56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 57 USB_DT_USB_SS_CAP_SIZE); 58 bos->bNumDeviceCaps = 1; 59 60 /* Create the descriptor for port with the highest revision */ 61 for (i = 0; i < xhci->num_port_caps; i++) { 62 u8 major = xhci->port_caps[i].maj_rev; 63 u8 minor = xhci->port_caps[i].min_rev; 64 u16 rev = (major << 8) | minor; 65 66 if (i == 0 || bcdUSB < rev) { 67 bcdUSB = rev; 68 port_cap = &xhci->port_caps[i]; 69 } 70 } 71 72 if (bcdUSB >= 0x0310) { 73 if (port_cap->psi_count) { 74 u8 num_sym_ssa = 0; 75 76 for (i = 0; i < port_cap->psi_count; i++) { 77 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM) 78 num_sym_ssa++; 79 } 80 81 ssac = port_cap->psi_count + num_sym_ssa - 1; 82 ssic = port_cap->psi_uid_count - 1; 83 } else { 84 if (bcdUSB >= 0x0320) 85 ssac = 7; 86 else 87 ssac = 3; 88 89 ssic = (ssac + 1) / 2 - 1; 90 } 91 92 bos->bNumDeviceCaps++; 93 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 94 USB_DT_USB_SS_CAP_SIZE + 95 USB_DT_USB_SSP_CAP_SIZE(ssac)); 96 } 97 98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 99 return wLength; 100 101 /* SuperSpeed USB Device Capability */ 102 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE]; 103 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; 104 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 105 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; 106 ss_cap->bmAttributes = 0; /* set later */ 107 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION); 108 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 109 ss_cap->bU1devExitLat = 0; /* set later */ 110 ss_cap->bU2DevExitLat = 0; /* set later */ 111 112 reg = readl(&xhci->cap_regs->hcc_params); 113 if (HCC_LTC(reg)) 114 ss_cap->bmAttributes |= USB_LTM_SUPPORT; 115 116 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 117 reg = readl(&xhci->cap_regs->hcs_params3); 118 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg); 119 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg)); 120 } 121 122 if (wLength < le16_to_cpu(bos->wTotalLength)) 123 return wLength; 124 125 if (bcdUSB < 0x0310) 126 return le16_to_cpu(bos->wTotalLength); 127 128 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE + 129 USB_DT_USB_SS_CAP_SIZE]; 130 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac); 131 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 132 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE; 133 ssp_cap->bReserved = 0; 134 ssp_cap->wReserved = 0; 135 ssp_cap->bmAttributes = 136 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) | 137 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic)); 138 139 if (!port_cap->psi_count) { 140 for (i = 0; i < ssac + 1; i++) 141 ssp_cap->bmSublinkSpeedAttr[i] = 142 cpu_to_le32(ssp_cap_default_ssa[i]); 143 144 min_ssid = 4; 145 goto out; 146 } 147 148 offset = 0; 149 for (i = 0; i < port_cap->psi_count; i++) { 150 u32 psi; 151 u32 attr; 152 u8 ssid; 153 u8 lp; 154 u8 lse; 155 u8 psie; 156 u16 lane_mantissa; 157 u16 psim; 158 u16 plt; 159 160 psi = port_cap->psi[i]; 161 ssid = XHCI_EXT_PORT_PSIV(psi); 162 lp = XHCI_EXT_PORT_LP(psi); 163 psie = XHCI_EXT_PORT_PSIE(psi); 164 psim = XHCI_EXT_PORT_PSIM(psi); 165 plt = psi & PLT_MASK; 166 167 lse = psie; 168 lane_mantissa = psim; 169 170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ 171 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++) 172 psim /= 1000; 173 174 if (!min_rate || psim < min_rate) { 175 min_ssid = ssid; 176 min_rate = psim; 177 } 178 179 /* Some host controllers don't set the link protocol for SSP */ 180 if (psim >= 10) 181 lp = USB_SSP_SUBLINK_SPEED_LP_SSP; 182 183 /* 184 * PSIM and PSIE represent the total speed of PSI. The BOS 185 * descriptor SSP sublink speed attribute lane mantissa 186 * describes the lane speed. E.g. PSIM and PSIE for gen2x2 187 * is 20Gbps, but the BOS descriptor lane speed mantissa is 188 * 10Gbps. Check and modify the mantissa value to match the 189 * lane speed. 190 */ 191 if (bcdUSB == 0x0320 && plt == PLT_SYM) { 192 /* 193 * The PSI dword for gen1x2 and gen2x1 share the same 194 * values. But the lane speed for gen1x2 is 5Gbps while 195 * gen2x1 is 10Gbps. If the previous PSI dword SSID is 196 * 5 and the PSIE and PSIM match with SSID 6, let's 197 * assume that the controller follows the default speed 198 * id with SSID 6 for gen1x2. 199 */ 200 if (ssid == 6 && psie == 3 && psim == 10 && i) { 201 u32 prev = port_cap->psi[i - 1]; 202 203 if ((prev & PLT_MASK) == PLT_SYM && 204 XHCI_EXT_PORT_PSIV(prev) == 5 && 205 XHCI_EXT_PORT_PSIE(prev) == 3 && 206 XHCI_EXT_PORT_PSIM(prev) == 10) { 207 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 208 lane_mantissa = 5; 209 } 210 } 211 212 if (psie == 3 && psim > 10) { 213 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 214 lane_mantissa = 10; 215 } 216 } 217 218 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) | 219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) | 220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) | 221 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa)); 222 223 switch (plt) { 224 case PLT_SYM: 225 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 226 USB_SSP_SUBLINK_SPEED_ST_SYM_RX); 227 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 228 229 attr &= ~USB_SSP_SUBLINK_SPEED_ST; 230 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 231 USB_SSP_SUBLINK_SPEED_ST_SYM_TX); 232 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 233 break; 234 case PLT_ASYM_RX: 235 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 236 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX); 237 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 238 break; 239 case PLT_ASYM_TX: 240 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 241 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX); 242 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 243 break; 244 } 245 } 246 out: 247 ssp_cap->wFunctionalitySupport = 248 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 249 min_ssid) | 250 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) | 251 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1)); 252 253 return le16_to_cpu(bos->wTotalLength); 254 } 255 256 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 257 struct usb_hub_descriptor *desc, int ports) 258 { 259 u16 temp; 260 261 desc->bHubContrCurrent = 0; 262 263 desc->bNbrPorts = ports; 264 temp = 0; 265 /* Bits 1:0 - support per-port power switching, or power always on */ 266 if (HCC_PPC(xhci->hcc_params)) 267 temp |= HUB_CHAR_INDV_PORT_LPSM; 268 else 269 temp |= HUB_CHAR_NO_LPSM; 270 /* Bit 2 - root hubs are not part of a compound device */ 271 /* Bits 4:3 - individual port over current protection */ 272 temp |= HUB_CHAR_INDV_PORT_OCPM; 273 /* Bits 6:5 - no TTs in root ports */ 274 /* Bit 7 - no port indicators */ 275 desc->wHubCharacteristics = cpu_to_le16(temp); 276 } 277 278 /* Fill in the USB 2.0 roothub descriptor */ 279 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 280 struct usb_hub_descriptor *desc) 281 { 282 int ports; 283 u16 temp; 284 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 285 u32 portsc; 286 unsigned int i; 287 struct xhci_hub *rhub; 288 289 rhub = &xhci->usb2_rhub; 290 ports = rhub->num_ports; 291 xhci_common_hub_descriptor(xhci, desc, ports); 292 desc->bDescriptorType = USB_DT_HUB; 293 temp = 1 + (ports / 8); 294 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 295 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */ 296 297 /* The Device Removable bits are reported on a byte granularity. 298 * If the port doesn't exist within that byte, the bit is set to 0. 299 */ 300 memset(port_removable, 0, sizeof(port_removable)); 301 for (i = 0; i < ports; i++) { 302 portsc = readl(rhub->ports[i]->addr); 303 /* If a device is removable, PORTSC reports a 0, same as in the 304 * hub descriptor DeviceRemovable bits. 305 */ 306 if (portsc & PORT_DEV_REMOVE) 307 /* This math is hairy because bit 0 of DeviceRemovable 308 * is reserved, and bit 1 is for port 1, etc. 309 */ 310 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 311 } 312 313 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 314 * ports on it. The USB 2.0 specification says that there are two 315 * variable length fields at the end of the hub descriptor: 316 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 317 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 318 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 319 * 0xFF, so we initialize the both arrays (DeviceRemovable and 320 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 321 * set of ports that actually exist. 322 */ 323 memset(desc->u.hs.DeviceRemovable, 0xff, 324 sizeof(desc->u.hs.DeviceRemovable)); 325 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 326 sizeof(desc->u.hs.PortPwrCtrlMask)); 327 328 for (i = 0; i < (ports + 1 + 7) / 8; i++) 329 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 330 sizeof(__u8)); 331 } 332 333 /* Fill in the USB 3.0 roothub descriptor */ 334 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 struct usb_hub_descriptor *desc) 336 { 337 int ports; 338 u16 port_removable; 339 u32 portsc; 340 unsigned int i; 341 struct xhci_hub *rhub; 342 343 rhub = &xhci->usb3_rhub; 344 ports = rhub->num_ports; 345 xhci_common_hub_descriptor(xhci, desc, ports); 346 desc->bDescriptorType = USB_DT_SS_HUB; 347 desc->bDescLength = USB_DT_SS_HUB_SIZE; 348 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */ 349 350 /* header decode latency should be zero for roothubs, 351 * see section 4.23.5.2. 352 */ 353 desc->u.ss.bHubHdrDecLat = 0; 354 desc->u.ss.wHubDelay = 0; 355 356 port_removable = 0; 357 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 358 for (i = 0; i < ports; i++) { 359 portsc = readl(rhub->ports[i]->addr); 360 if (portsc & PORT_DEV_REMOVE) 361 port_removable |= 1 << (i + 1); 362 } 363 364 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 365 } 366 367 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 368 struct usb_hub_descriptor *desc) 369 { 370 371 if (hcd->speed >= HCD_USB3) 372 xhci_usb3_hub_descriptor(hcd, xhci, desc); 373 else 374 xhci_usb2_hub_descriptor(hcd, xhci, desc); 375 376 } 377 378 static unsigned int xhci_port_speed(unsigned int port_status) 379 { 380 if (DEV_LOWSPEED(port_status)) 381 return USB_PORT_STAT_LOW_SPEED; 382 if (DEV_HIGHSPEED(port_status)) 383 return USB_PORT_STAT_HIGH_SPEED; 384 /* 385 * FIXME: Yes, we should check for full speed, but the core uses that as 386 * a default in portspeed() in usb/core/hub.c (which is the only place 387 * USB_PORT_STAT_*_SPEED is used). 388 */ 389 return 0; 390 } 391 392 /* 393 * These bits are Read Only (RO) and should be saved and written to the 394 * registers: 0, 3, 10:13, 30 395 * connect status, over-current status, port speed, and device removable. 396 * connect status and port speed are also sticky - meaning they're in 397 * the AUX well and they aren't changed by a hot, warm, or cold reset. 398 */ 399 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 400 /* 401 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 402 * bits 5:8, 9, 14:15, 25:27 403 * link state, port power, port indicator state, "wake on" enable state 404 */ 405 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 406 /* 407 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 408 * bit 4 (port reset) 409 */ 410 #define XHCI_PORT_RW1S ((1<<4)) 411 /* 412 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 413 * bits 1, 17, 18, 19, 20, 21, 22, 23 414 * port enable/disable, and 415 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 416 * over-current, reset, link state, and L1 change 417 */ 418 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 419 /* 420 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 421 * latched in 422 */ 423 #define XHCI_PORT_RW ((1<<16)) 424 /* 425 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 426 * bits 2, 24, 28:31 427 */ 428 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 429 430 /** 431 * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable 432 * @state: u32 port value read from portsc register to be cleanup up 433 * 434 * Given a port state, this function returns a value that would result in the 435 * port being in the same state, if the value was written to the port status 436 * control register. 437 * Save Read Only (RO) bits and save read/write bits where 438 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 439 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 440 * 441 * Return: u32 value that can be written back to portsc register without 442 * changing port state. 443 */ 444 445 u32 xhci_port_state_to_neutral(u32 state) 446 { 447 /* Save read-only status and port state */ 448 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 449 } 450 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral); 451 452 /* 453 * Stop device 454 * It issues stop endpoint command for EP 0 to 30. And wait the last command 455 * to complete. 456 * suspend will set to 1, if suspend bit need to set in command. 457 */ 458 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 459 { 460 struct xhci_virt_device *virt_dev; 461 struct xhci_command *cmd; 462 unsigned long flags; 463 int ret; 464 int i; 465 466 ret = 0; 467 virt_dev = xhci->devs[slot_id]; 468 if (!virt_dev) 469 return -ENODEV; 470 471 trace_xhci_stop_device(virt_dev); 472 473 cmd = xhci_alloc_command(xhci, true, GFP_NOIO); 474 if (!cmd) 475 return -ENOMEM; 476 477 spin_lock_irqsave(&xhci->lock, flags); 478 for (i = LAST_EP_INDEX; i > 0; i--) { 479 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 480 struct xhci_ep_ctx *ep_ctx; 481 struct xhci_command *command; 482 483 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 484 485 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 486 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 487 continue; 488 489 command = xhci_alloc_command(xhci, false, GFP_NOWAIT); 490 if (!command) { 491 spin_unlock_irqrestore(&xhci->lock, flags); 492 ret = -ENOMEM; 493 goto cmd_cleanup; 494 } 495 496 ret = xhci_queue_stop_endpoint(xhci, command, slot_id, 497 i, suspend); 498 if (ret) { 499 spin_unlock_irqrestore(&xhci->lock, flags); 500 xhci_free_command(xhci, command); 501 goto cmd_cleanup; 502 } 503 } 504 } 505 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 506 if (ret) { 507 spin_unlock_irqrestore(&xhci->lock, flags); 508 goto cmd_cleanup; 509 } 510 511 xhci_ring_cmd_db(xhci); 512 spin_unlock_irqrestore(&xhci->lock, flags); 513 514 /* Wait for last stop endpoint command to finish */ 515 wait_for_completion(cmd->completion); 516 517 if (cmd->status == COMP_COMMAND_ABORTED || 518 cmd->status == COMP_COMMAND_RING_STOPPED) { 519 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 520 ret = -ETIME; 521 } 522 523 cmd_cleanup: 524 xhci_free_command(xhci, cmd); 525 return ret; 526 } 527 528 /* 529 * Ring device, it rings the all doorbells unconditionally. 530 */ 531 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 532 { 533 int i, s; 534 struct xhci_virt_ep *ep; 535 536 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 537 ep = &xhci->devs[slot_id]->eps[i]; 538 539 if (ep->ep_state & EP_HAS_STREAMS) { 540 for (s = 1; s < ep->stream_info->num_streams; s++) 541 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 542 } else if (ep->ring && ep->ring->dequeue) { 543 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 544 } 545 } 546 547 return; 548 } 549 550 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port) 551 { 552 struct usb_hcd *hcd; 553 u32 portsc; 554 555 hcd = port->rhub->hcd; 556 557 /* Don't allow the USB core to disable SuperSpeed ports. */ 558 if (hcd->speed >= HCD_USB3) { 559 xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n"); 560 return; 561 } 562 563 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 564 xhci_dbg(xhci, 565 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 566 return; 567 } 568 569 portsc = readl(port->addr); 570 portsc = xhci_port_state_to_neutral(portsc); 571 572 /* Write 1 to disable the port */ 573 writel(portsc | PORT_PE, port->addr); 574 575 portsc = readl(port->addr); 576 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", 577 hcd->self.busnum, port->hcd_portnum + 1, portsc); 578 } 579 580 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 581 u16 wIndex, __le32 __iomem *addr, u32 port_status) 582 { 583 char *port_change_bit; 584 u32 status; 585 586 switch (wValue) { 587 case USB_PORT_FEAT_C_RESET: 588 status = PORT_RC; 589 port_change_bit = "reset"; 590 break; 591 case USB_PORT_FEAT_C_BH_PORT_RESET: 592 status = PORT_WRC; 593 port_change_bit = "warm(BH) reset"; 594 break; 595 case USB_PORT_FEAT_C_CONNECTION: 596 status = PORT_CSC; 597 port_change_bit = "connect"; 598 break; 599 case USB_PORT_FEAT_C_OVER_CURRENT: 600 status = PORT_OCC; 601 port_change_bit = "over-current"; 602 break; 603 case USB_PORT_FEAT_C_ENABLE: 604 status = PORT_PEC; 605 port_change_bit = "enable/disable"; 606 break; 607 case USB_PORT_FEAT_C_SUSPEND: 608 status = PORT_PLC; 609 port_change_bit = "suspend/resume"; 610 break; 611 case USB_PORT_FEAT_C_PORT_LINK_STATE: 612 status = PORT_PLC; 613 port_change_bit = "link state"; 614 break; 615 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 616 status = PORT_CEC; 617 port_change_bit = "config error"; 618 break; 619 default: 620 /* Should never happen */ 621 return; 622 } 623 /* Change bits are all write 1 to clear */ 624 writel(port_status | status, addr); 625 port_status = readl(addr); 626 627 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", 628 wIndex + 1, port_change_bit, port_status); 629 } 630 631 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) 632 { 633 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 634 635 if (hcd->speed >= HCD_USB3) 636 return &xhci->usb3_rhub; 637 return &xhci->usb2_rhub; 638 } 639 640 /* 641 * xhci_set_port_power() must be called with xhci->lock held. 642 * It will release and re-aquire the lock while calling ACPI 643 * method. 644 */ 645 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port, 646 bool on, unsigned long *flags) 647 __must_hold(&xhci->lock) 648 { 649 struct usb_hcd *hcd; 650 u32 temp; 651 652 hcd = port->rhub->hcd; 653 temp = readl(port->addr); 654 655 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", 656 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); 657 658 temp = xhci_port_state_to_neutral(temp); 659 660 if (on) { 661 /* Power on */ 662 writel(temp | PORT_POWER, port->addr); 663 readl(port->addr); 664 } else { 665 /* Power off */ 666 writel(temp & ~PORT_POWER, port->addr); 667 } 668 669 spin_unlock_irqrestore(&xhci->lock, *flags); 670 temp = usb_acpi_power_manageable(hcd->self.root_hub, 671 port->hcd_portnum); 672 if (temp) 673 usb_acpi_set_power_state(hcd->self.root_hub, 674 port->hcd_portnum, on); 675 spin_lock_irqsave(&xhci->lock, *flags); 676 } 677 678 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, 679 u16 test_mode, u16 wIndex) 680 { 681 u32 temp; 682 struct xhci_port *port; 683 684 /* xhci only supports test mode for usb2 ports */ 685 port = xhci->usb2_rhub.ports[wIndex]; 686 temp = readl(port->addr + PORTPMSC); 687 temp |= test_mode << PORT_TEST_MODE_SHIFT; 688 writel(temp, port->addr + PORTPMSC); 689 xhci->test_mode = test_mode; 690 if (test_mode == USB_TEST_FORCE_ENABLE) 691 xhci_start(xhci); 692 } 693 694 static int xhci_enter_test_mode(struct xhci_hcd *xhci, 695 u16 test_mode, u16 wIndex, unsigned long *flags) 696 __must_hold(&xhci->lock) 697 { 698 int i, retval; 699 700 /* Disable all Device Slots */ 701 xhci_dbg(xhci, "Disable all slots\n"); 702 spin_unlock_irqrestore(&xhci->lock, *flags); 703 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 704 if (!xhci->devs[i]) 705 continue; 706 707 retval = xhci_disable_and_free_slot(xhci, i); 708 if (retval) 709 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 710 i, retval); 711 } 712 spin_lock_irqsave(&xhci->lock, *flags); 713 /* Put all ports to the Disable state by clear PP */ 714 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 715 /* Power off USB3 ports*/ 716 for (i = 0; i < xhci->usb3_rhub.num_ports; i++) 717 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags); 718 /* Power off USB2 ports*/ 719 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) 720 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags); 721 /* Stop the controller */ 722 xhci_dbg(xhci, "Stop controller\n"); 723 retval = xhci_halt(xhci); 724 if (retval) 725 return retval; 726 /* Disable runtime PM for test mode */ 727 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 728 /* Set PORTPMSC.PTC field to enter selected test mode */ 729 /* Port is selected by wIndex. port_id = wIndex + 1 */ 730 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", 731 test_mode, wIndex + 1); 732 xhci_port_set_test_mode(xhci, test_mode, wIndex); 733 return retval; 734 } 735 736 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 737 { 738 int retval; 739 740 if (!xhci->test_mode) { 741 xhci_err(xhci, "Not in test mode, do nothing.\n"); 742 return 0; 743 } 744 if (xhci->test_mode == USB_TEST_FORCE_ENABLE && 745 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 746 retval = xhci_halt(xhci); 747 if (retval) 748 return retval; 749 } 750 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 751 xhci->test_mode = 0; 752 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC); 753 } 754 755 /** 756 * xhci_port_is_tunneled() - Check if USB3 connection is tunneled over USB4 757 * @xhci: xhci host controller 758 * @port: USB3 port to be checked. 759 * 760 * Some hosts can detect if a USB3 connection is native USB3 or tunneled over 761 * USB4. Intel hosts expose this via vendor specific extended capability 206 762 * eSS PORT registers TUNEN (tunnel enabled) bit. 763 * 764 * A USB3 device must be connected to the port to detect the tunnel. 765 * 766 * Return: link tunnel mode enum, USB_LINK_UNKNOWN if host is incapable of 767 * detecting USB3 over USB4 tunnels. USB_LINK_NATIVE or USB_LINK_TUNNELED 768 * otherwise. 769 */ 770 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 771 struct xhci_port *port) 772 { 773 struct usb_hcd *hcd; 774 void __iomem *base; 775 u32 offset; 776 777 /* Don't try and probe this capability for non-Intel hosts */ 778 hcd = xhci_to_hcd(xhci); 779 if (!dev_is_pci(hcd->self.controller) || 780 to_pci_dev(hcd->self.controller)->vendor != PCI_VENDOR_ID_INTEL) 781 return USB_LINK_UNKNOWN; 782 783 base = &xhci->cap_regs->hc_capbase; 784 offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW); 785 786 if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) { 787 offset = XHCI_INTEL_SPR_ESS_PORT_OFFSET + port->hcd_portnum * 0x20; 788 789 if (readl(base + offset) & XHCI_INTEL_SPR_TUNEN) 790 return USB_LINK_TUNNELED; 791 else 792 return USB_LINK_NATIVE; 793 } 794 795 return USB_LINK_UNKNOWN; 796 } 797 798 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 799 u32 link_state) 800 { 801 u32 temp; 802 u32 portsc; 803 804 portsc = readl(port->addr); 805 temp = xhci_port_state_to_neutral(portsc); 806 temp &= ~PORT_PLS_MASK; 807 temp |= PORT_LINK_STROBE | link_state; 808 writel(temp, port->addr); 809 810 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", 811 port->rhub->hcd->self.busnum, port->hcd_portnum + 1, 812 portsc, temp); 813 } 814 815 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 816 struct xhci_port *port, u16 wake_mask) 817 { 818 u32 temp; 819 820 temp = readl(port->addr); 821 temp = xhci_port_state_to_neutral(temp); 822 823 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 824 temp |= PORT_WKCONN_E; 825 else 826 temp &= ~PORT_WKCONN_E; 827 828 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 829 temp |= PORT_WKDISC_E; 830 else 831 temp &= ~PORT_WKDISC_E; 832 833 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 834 temp |= PORT_WKOC_E; 835 else 836 temp &= ~PORT_WKOC_E; 837 838 writel(temp, port->addr); 839 } 840 841 /* Test and clear port RWC bit */ 842 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 843 u32 port_bit) 844 { 845 u32 temp; 846 847 temp = readl(port->addr); 848 if (temp & port_bit) { 849 temp = xhci_port_state_to_neutral(temp); 850 temp |= port_bit; 851 writel(temp, port->addr); 852 } 853 } 854 855 /* Updates Link Status for super Speed port */ 856 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 857 u32 *status, u32 status_reg) 858 { 859 u32 pls = status_reg & PORT_PLS_MASK; 860 861 /* When the CAS bit is set then warm reset 862 * should be performed on port 863 */ 864 if (status_reg & PORT_CAS) { 865 /* The CAS bit can be set while the port is 866 * in any link state. 867 * Only roothubs have CAS bit, so we 868 * pretend to be in compliance mode 869 * unless we're already in compliance 870 * or the inactive state. 871 */ 872 if (pls != USB_SS_PORT_LS_COMP_MOD && 873 pls != USB_SS_PORT_LS_SS_INACTIVE) { 874 pls = USB_SS_PORT_LS_COMP_MOD; 875 } 876 /* Return also connection bit - 877 * hub state machine resets port 878 * when this bit is set. 879 */ 880 pls |= USB_PORT_STAT_CONNECTION; 881 } else { 882 /* 883 * Resume state is an xHCI internal state. Do not report it to 884 * usb core, instead, pretend to be U3, thus usb core knows 885 * it's not ready for transfer. 886 */ 887 if (pls == XDEV_RESUME) { 888 *status |= USB_SS_PORT_LS_U3; 889 return; 890 } 891 892 /* 893 * If CAS bit isn't set but the Port is already at 894 * Compliance Mode, fake a connection so the USB core 895 * notices the Compliance state and resets the port. 896 * This resolves an issue generated by the SN65LVPE502CP 897 * in which sometimes the port enters compliance mode 898 * caused by a delay on the host-device negotiation. 899 */ 900 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 901 (pls == USB_SS_PORT_LS_COMP_MOD)) 902 pls |= USB_PORT_STAT_CONNECTION; 903 } 904 905 /* update status field */ 906 *status |= pls; 907 } 908 909 /* 910 * Function for Compliance Mode Quirk. 911 * 912 * This Function verifies if all xhc USB3 ports have entered U0, if so, 913 * the compliance mode timer is deleted. A port won't enter 914 * compliance mode if it has previously entered U0. 915 */ 916 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 917 u16 wIndex) 918 { 919 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); 920 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 921 922 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 923 return; 924 925 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 926 xhci->port_status_u0 |= 1 << wIndex; 927 if (xhci->port_status_u0 == all_ports_seen_u0) { 928 timer_delete_sync(&xhci->comp_mode_recovery_timer); 929 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 930 "All USB3 ports have entered U0 already!"); 931 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 932 "Compliance Mode Recovery Timer Deleted."); 933 } 934 } 935 } 936 937 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, 938 u32 portsc, 939 unsigned long *flags) 940 { 941 struct xhci_bus_state *bus_state; 942 struct xhci_hcd *xhci; 943 struct usb_hcd *hcd; 944 u32 wIndex; 945 946 hcd = port->rhub->hcd; 947 bus_state = &port->rhub->bus_state; 948 xhci = hcd_to_xhci(hcd); 949 wIndex = port->hcd_portnum; 950 951 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { 952 return -EINVAL; 953 } 954 /* did port event handler already start resume timing? */ 955 if (!port->resume_timestamp) { 956 /* If not, maybe we are in a host initiated resume? */ 957 if (test_bit(wIndex, &bus_state->resuming_ports)) { 958 /* Host initiated resume doesn't time the resume 959 * signalling using resume_done[]. 960 * It manually sets RESUME state, sleeps 20ms 961 * and sets U0 state. This should probably be 962 * changed, but not right now. 963 */ 964 } else { 965 /* port resume was discovered now and here, 966 * start resume timing 967 */ 968 unsigned long timeout = jiffies + 969 msecs_to_jiffies(USB_RESUME_TIMEOUT); 970 971 set_bit(wIndex, &bus_state->resuming_ports); 972 port->resume_timestamp = timeout; 973 mod_timer(&hcd->rh_timer, timeout); 974 usb_hcd_start_port_resume(&hcd->self, wIndex); 975 } 976 /* Has resume been signalled for USB_RESUME_TIME yet? */ 977 } else if (time_after_eq(jiffies, port->resume_timestamp)) { 978 int time_left; 979 980 xhci_dbg(xhci, "resume USB2 port %d-%d\n", 981 hcd->self.busnum, wIndex + 1); 982 983 port->resume_timestamp = 0; 984 clear_bit(wIndex, &bus_state->resuming_ports); 985 986 reinit_completion(&port->rexit_done); 987 port->rexit_active = true; 988 989 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 990 xhci_set_link_state(xhci, port, XDEV_U0); 991 992 spin_unlock_irqrestore(&xhci->lock, *flags); 993 time_left = wait_for_completion_timeout( 994 &port->rexit_done, 995 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); 996 spin_lock_irqsave(&xhci->lock, *flags); 997 998 if (time_left) { 999 if (!port->slot_id) { 1000 xhci_dbg(xhci, "slot_id is zero\n"); 1001 return -ENODEV; 1002 } 1003 xhci_ring_device(xhci, port->slot_id); 1004 } else { 1005 int port_status = readl(port->addr); 1006 1007 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", 1008 hcd->self.busnum, wIndex + 1, port_status); 1009 /* 1010 * keep rexit_active set if U0 transition failed so we 1011 * know to report PORT_STAT_SUSPEND status back to 1012 * usbcore. It will be cleared later once the port is 1013 * out of RESUME/U3 state 1014 */ 1015 } 1016 1017 usb_hcd_end_port_resume(&hcd->self, wIndex); 1018 bus_state->port_c_suspend |= 1 << wIndex; 1019 bus_state->suspended_ports &= ~(1 << wIndex); 1020 } 1021 1022 return 0; 1023 } 1024 1025 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) 1026 { 1027 u32 ext_stat = 0; 1028 int speed_id; 1029 1030 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 1031 speed_id = DEV_PORT_SPEED(raw_port_status); 1032 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 1033 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 1034 1035 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 1036 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 1037 1038 return ext_stat; 1039 } 1040 1041 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, 1042 u32 portsc) 1043 { 1044 struct xhci_bus_state *bus_state; 1045 struct xhci_hcd *xhci; 1046 struct usb_hcd *hcd; 1047 u32 link_state; 1048 u32 portnum; 1049 1050 bus_state = &port->rhub->bus_state; 1051 xhci = hcd_to_xhci(port->rhub->hcd); 1052 hcd = port->rhub->hcd; 1053 link_state = portsc & PORT_PLS_MASK; 1054 portnum = port->hcd_portnum; 1055 1056 /* USB3 specific wPortChange bits 1057 * 1058 * Port link change with port in resume state should not be 1059 * reported to usbcore, as this is an internal state to be 1060 * handled by xhci driver. Reporting PLC to usbcore may 1061 * cause usbcore clearing PLC first and port change event 1062 * irq won't be generated. 1063 */ 1064 1065 if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) 1066 *status |= USB_PORT_STAT_C_LINK_STATE << 16; 1067 if (portsc & PORT_WRC) 1068 *status |= USB_PORT_STAT_C_BH_RESET << 16; 1069 if (portsc & PORT_CEC) 1070 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 1071 1072 /* USB3 specific wPortStatus bits */ 1073 if (portsc & PORT_POWER) 1074 *status |= USB_SS_PORT_STAT_POWER; 1075 1076 /* no longer suspended or resuming */ 1077 if (link_state != XDEV_U3 && 1078 link_state != XDEV_RESUME && 1079 link_state != XDEV_RECOVERY) { 1080 /* remote wake resume signaling complete */ 1081 if (bus_state->port_remote_wakeup & (1 << portnum)) { 1082 bus_state->port_remote_wakeup &= ~(1 << portnum); 1083 usb_hcd_end_port_resume(&hcd->self, portnum); 1084 } 1085 bus_state->suspended_ports &= ~(1 << portnum); 1086 } 1087 1088 xhci_hub_report_usb3_link_state(xhci, status, portsc); 1089 xhci_del_comp_mod_timer(xhci, portsc, portnum); 1090 } 1091 1092 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, 1093 u32 portsc, unsigned long *flags) 1094 { 1095 struct xhci_bus_state *bus_state; 1096 u32 link_state; 1097 u32 portnum; 1098 int err; 1099 1100 bus_state = &port->rhub->bus_state; 1101 link_state = portsc & PORT_PLS_MASK; 1102 portnum = port->hcd_portnum; 1103 1104 /* USB2 wPortStatus bits */ 1105 if (portsc & PORT_POWER) { 1106 *status |= USB_PORT_STAT_POWER; 1107 1108 /* link state is only valid if port is powered */ 1109 if (link_state == XDEV_U3) 1110 *status |= USB_PORT_STAT_SUSPEND; 1111 if (link_state == XDEV_U2) 1112 *status |= USB_PORT_STAT_L1; 1113 if (link_state == XDEV_U0) { 1114 if (bus_state->suspended_ports & (1 << portnum)) { 1115 bus_state->suspended_ports &= ~(1 << portnum); 1116 bus_state->port_c_suspend |= 1 << portnum; 1117 } 1118 } 1119 if (link_state == XDEV_RESUME) { 1120 err = xhci_handle_usb2_port_link_resume(port, portsc, 1121 flags); 1122 if (err < 0) 1123 *status = 0xffffffff; 1124 else if (port->resume_timestamp || port->rexit_active) 1125 *status |= USB_PORT_STAT_SUSPEND; 1126 } 1127 } 1128 1129 /* 1130 * Clear usb2 resume signalling variables if port is no longer suspended 1131 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a 1132 * error state. Resume related variables should be cleared in all those cases. 1133 */ 1134 if (link_state != XDEV_U3 && link_state != XDEV_RESUME) { 1135 if (port->resume_timestamp || 1136 test_bit(portnum, &bus_state->resuming_ports)) { 1137 port->resume_timestamp = 0; 1138 clear_bit(portnum, &bus_state->resuming_ports); 1139 usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum); 1140 } 1141 port->rexit_active = 0; 1142 bus_state->suspended_ports &= ~(1 << portnum); 1143 } 1144 } 1145 1146 /* 1147 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 1148 * 3.0 hubs use. 1149 * 1150 * Possible side effects: 1151 * - Mark a port as being done with device resume, 1152 * and ring the endpoint doorbells. 1153 * - Stop the Synopsys redriver Compliance Mode polling. 1154 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 1155 */ 1156 static u32 xhci_get_port_status(struct usb_hcd *hcd, 1157 struct xhci_bus_state *bus_state, 1158 u16 wIndex, u32 raw_port_status, 1159 unsigned long *flags) 1160 __releases(&xhci->lock) 1161 __acquires(&xhci->lock) 1162 { 1163 u32 status = 0; 1164 struct xhci_hub *rhub; 1165 struct xhci_port *port; 1166 1167 rhub = xhci_get_rhub(hcd); 1168 port = rhub->ports[wIndex]; 1169 1170 /* common wPortChange bits */ 1171 if (raw_port_status & PORT_CSC) 1172 status |= USB_PORT_STAT_C_CONNECTION << 16; 1173 if (raw_port_status & PORT_PEC) 1174 status |= USB_PORT_STAT_C_ENABLE << 16; 1175 if ((raw_port_status & PORT_OCC)) 1176 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1177 if ((raw_port_status & PORT_RC)) 1178 status |= USB_PORT_STAT_C_RESET << 16; 1179 1180 /* common wPortStatus bits */ 1181 if (raw_port_status & PORT_CONNECT) { 1182 status |= USB_PORT_STAT_CONNECTION; 1183 status |= xhci_port_speed(raw_port_status); 1184 } 1185 if (raw_port_status & PORT_PE) 1186 status |= USB_PORT_STAT_ENABLE; 1187 if (raw_port_status & PORT_OC) 1188 status |= USB_PORT_STAT_OVERCURRENT; 1189 if (raw_port_status & PORT_RESET) 1190 status |= USB_PORT_STAT_RESET; 1191 1192 /* USB2 and USB3 specific bits, including Port Link State */ 1193 if (hcd->speed >= HCD_USB3) 1194 xhci_get_usb3_port_status(port, &status, raw_port_status); 1195 else 1196 xhci_get_usb2_port_status(port, &status, raw_port_status, 1197 flags); 1198 1199 if (bus_state->port_c_suspend & (1 << wIndex)) 1200 status |= USB_PORT_STAT_C_SUSPEND << 16; 1201 1202 return status; 1203 } 1204 1205 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1206 u16 wIndex, char *buf, u16 wLength) 1207 { 1208 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1209 int max_ports; 1210 unsigned long flags; 1211 u32 temp, status; 1212 int retval = 0; 1213 struct xhci_bus_state *bus_state; 1214 u16 link_state = 0; 1215 u16 wake_mask = 0; 1216 u16 timeout = 0; 1217 u16 test_mode = 0; 1218 struct xhci_hub *rhub; 1219 struct xhci_port **ports; 1220 struct xhci_port *port; 1221 int portnum1; 1222 1223 rhub = xhci_get_rhub(hcd); 1224 ports = rhub->ports; 1225 max_ports = rhub->num_ports; 1226 bus_state = &rhub->bus_state; 1227 portnum1 = wIndex & 0xff; 1228 1229 spin_lock_irqsave(&xhci->lock, flags); 1230 switch (typeReq) { 1231 case GetHubStatus: 1232 /* No power source, over-current reported per port */ 1233 memset(buf, 0, 4); 1234 break; 1235 case GetHubDescriptor: 1236 /* Check to make sure userspace is asking for the USB 3.0 hub 1237 * descriptor for the USB 3.0 roothub. If not, we stall the 1238 * endpoint, like external hubs do. 1239 */ 1240 if (hcd->speed >= HCD_USB3 && 1241 (wLength < USB_DT_SS_HUB_SIZE || 1242 wValue != (USB_DT_SS_HUB << 8))) { 1243 xhci_dbg(xhci, "Wrong hub descriptor type for " 1244 "USB 3.0 roothub.\n"); 1245 goto error; 1246 } 1247 xhci_hub_descriptor(hcd, xhci, 1248 (struct usb_hub_descriptor *) buf); 1249 break; 1250 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1251 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 1252 goto error; 1253 1254 if (hcd->speed < HCD_USB3) 1255 goto error; 1256 1257 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength); 1258 spin_unlock_irqrestore(&xhci->lock, flags); 1259 return retval; 1260 case GetPortStatus: 1261 if (!portnum1 || portnum1 > max_ports) 1262 goto error; 1263 1264 wIndex--; 1265 port = ports[portnum1 - 1]; 1266 temp = readl(port->addr); 1267 if (temp == ~(u32)0) { 1268 xhci_hc_died(xhci); 1269 retval = -ENODEV; 1270 break; 1271 } 1272 trace_xhci_get_port_status(port, temp); 1273 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, 1274 &flags); 1275 if (status == 0xffffffff) 1276 goto error; 1277 1278 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", 1279 hcd->self.busnum, portnum1, temp, status); 1280 1281 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1282 /* if USB 3.1 extended port status return additional 4 bytes */ 1283 if (wValue == 0x02) { 1284 u32 port_li; 1285 1286 if (hcd->speed < HCD_USB31 || wLength != 8) { 1287 xhci_err(xhci, "get ext port status invalid parameter\n"); 1288 retval = -EINVAL; 1289 break; 1290 } 1291 port_li = readl(port->addr + PORTLI); 1292 status = xhci_get_ext_port_status(temp, port_li); 1293 put_unaligned_le32(status, &buf[4]); 1294 } 1295 break; 1296 case SetPortFeature: 1297 if (wValue == USB_PORT_FEAT_LINK_STATE) 1298 link_state = (wIndex & 0xff00) >> 3; 1299 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 1300 wake_mask = wIndex & 0xff00; 1301 if (wValue == USB_PORT_FEAT_TEST) 1302 test_mode = (wIndex & 0xff00) >> 8; 1303 /* The MSB of wIndex is the U1/U2 timeout */ 1304 timeout = (wIndex & 0xff00) >> 8; 1305 1306 wIndex &= 0xff; 1307 if (!portnum1 || portnum1 > max_ports) 1308 goto error; 1309 1310 port = ports[portnum1 - 1]; 1311 wIndex--; 1312 temp = readl(port->addr); 1313 if (temp == ~(u32)0) { 1314 xhci_hc_died(xhci); 1315 retval = -ENODEV; 1316 break; 1317 } 1318 temp = xhci_port_state_to_neutral(temp); 1319 /* FIXME: What new port features do we need to support? */ 1320 switch (wValue) { 1321 case USB_PORT_FEAT_SUSPEND: 1322 temp = readl(port->addr); 1323 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 1324 /* Resume the port to U0 first */ 1325 xhci_set_link_state(xhci, port, XDEV_U0); 1326 spin_unlock_irqrestore(&xhci->lock, flags); 1327 msleep(10); 1328 spin_lock_irqsave(&xhci->lock, flags); 1329 } 1330 /* In spec software should not attempt to suspend 1331 * a port unless the port reports that it is in the 1332 * enabled (PED = ‘1’,PLS < ‘3’) state. 1333 */ 1334 temp = readl(port->addr); 1335 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 1336 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 1337 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", 1338 hcd->self.busnum, portnum1); 1339 goto error; 1340 } 1341 1342 if (!port->slot_id) { 1343 xhci_warn(xhci, "slot_id is zero\n"); 1344 goto error; 1345 } 1346 /* unlock to execute stop endpoint commands */ 1347 spin_unlock_irqrestore(&xhci->lock, flags); 1348 xhci_stop_device(xhci, port->slot_id, 1); 1349 spin_lock_irqsave(&xhci->lock, flags); 1350 1351 xhci_set_link_state(xhci, port, XDEV_U3); 1352 1353 spin_unlock_irqrestore(&xhci->lock, flags); 1354 msleep(10); /* wait device to enter */ 1355 spin_lock_irqsave(&xhci->lock, flags); 1356 1357 temp = readl(port->addr); 1358 bus_state->suspended_ports |= 1 << wIndex; 1359 break; 1360 case USB_PORT_FEAT_LINK_STATE: 1361 temp = readl(port->addr); 1362 /* Disable port */ 1363 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1364 xhci_dbg(xhci, "Disable port %d-%d\n", 1365 hcd->self.busnum, portnum1); 1366 temp = xhci_port_state_to_neutral(temp); 1367 /* 1368 * Clear all change bits, so that we get a new 1369 * connection event. 1370 */ 1371 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 1372 PORT_OCC | PORT_RC | PORT_PLC | 1373 PORT_CEC; 1374 writel(temp | PORT_PE, port->addr); 1375 temp = readl(port->addr); 1376 break; 1377 } 1378 1379 /* Put link in RxDetect (enable port) */ 1380 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1381 xhci_dbg(xhci, "Enable port %d-%d\n", 1382 hcd->self.busnum, portnum1); 1383 xhci_set_link_state(xhci, port, link_state); 1384 temp = readl(port->addr); 1385 break; 1386 } 1387 1388 /* 1389 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1390 * root hub port's transition to compliance mode upon 1391 * detecting LFPS timeout may be controlled by an 1392 * Compliance Transition Enabled (CTE) flag (not 1393 * software visible). This flag is set by writing 0xA 1394 * to PORTSC PLS field which will allow transition to 1395 * compliance mode the next time LFPS timeout is 1396 * encountered. A warm reset will clear it. 1397 * 1398 * The CTE flag is only supported if the HCCPARAMS2 CTC 1399 * flag is set, otherwise, the compliance substate is 1400 * automatically entered as on 1.0 and prior. 1401 */ 1402 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1403 if (!HCC2_CTC(xhci->hcc_params2)) { 1404 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1405 break; 1406 } 1407 1408 if ((temp & PORT_CONNECT)) { 1409 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1410 goto error; 1411 } 1412 1413 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", 1414 hcd->self.busnum, portnum1); 1415 xhci_set_link_state(xhci, port, link_state); 1416 1417 temp = readl(port->addr); 1418 break; 1419 } 1420 /* Port must be enabled */ 1421 if (!(temp & PORT_PE)) { 1422 retval = -ENODEV; 1423 break; 1424 } 1425 /* Can't set port link state above '3' (U3) */ 1426 if (link_state > USB_SS_PORT_LS_U3) { 1427 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", 1428 hcd->self.busnum, portnum1, link_state); 1429 goto error; 1430 } 1431 1432 /* 1433 * set link to U0, steps depend on current link state. 1434 * U3: set link to U0 and wait for u3exit completion. 1435 * U1/U2: no PLC complete event, only set link to U0. 1436 * Resume/Recovery: device initiated U0, only wait for 1437 * completion 1438 */ 1439 if (link_state == USB_SS_PORT_LS_U0) { 1440 u32 pls = temp & PORT_PLS_MASK; 1441 bool wait_u0 = false; 1442 1443 /* already in U0 */ 1444 if (pls == XDEV_U0) 1445 break; 1446 if (pls == XDEV_U3 || 1447 pls == XDEV_RESUME || 1448 pls == XDEV_RECOVERY) { 1449 wait_u0 = true; 1450 reinit_completion(&port->u3exit_done); 1451 } 1452 if (pls <= XDEV_U3) /* U1, U2, U3 */ 1453 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0); 1454 if (!wait_u0) { 1455 if (pls > XDEV_U3) 1456 goto error; 1457 break; 1458 } 1459 spin_unlock_irqrestore(&xhci->lock, flags); 1460 if (!wait_for_completion_timeout(&port->u3exit_done, 1461 msecs_to_jiffies(500))) 1462 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", 1463 hcd->self.busnum, portnum1); 1464 spin_lock_irqsave(&xhci->lock, flags); 1465 temp = readl(port->addr); 1466 break; 1467 } 1468 1469 if (link_state == USB_SS_PORT_LS_U3) { 1470 int retries = 16; 1471 if (port->slot_id) { 1472 /* unlock to execute stop endpoint 1473 * commands */ 1474 spin_unlock_irqrestore(&xhci->lock, 1475 flags); 1476 xhci_stop_device(xhci, port->slot_id, 1); 1477 spin_lock_irqsave(&xhci->lock, flags); 1478 } 1479 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3); 1480 spin_unlock_irqrestore(&xhci->lock, flags); 1481 while (retries--) { 1482 usleep_range(4000, 8000); 1483 temp = readl(port->addr); 1484 if ((temp & PORT_PLS_MASK) == XDEV_U3) 1485 break; 1486 } 1487 spin_lock_irqsave(&xhci->lock, flags); 1488 temp = readl(port->addr); 1489 bus_state->suspended_ports |= 1 << wIndex; 1490 } 1491 break; 1492 case USB_PORT_FEAT_POWER: 1493 /* 1494 * Turn on ports, even if there isn't per-port switching. 1495 * HC will report connect events even before this is set. 1496 * However, hub_wq will ignore the roothub events until 1497 * the roothub is registered. 1498 */ 1499 xhci_set_port_power(xhci, port, true, &flags); 1500 break; 1501 case USB_PORT_FEAT_RESET: 1502 temp = (temp | PORT_RESET); 1503 writel(temp, port->addr); 1504 1505 temp = readl(port->addr); 1506 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", 1507 hcd->self.busnum, portnum1, temp); 1508 break; 1509 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1510 xhci_set_remote_wake_mask(xhci, port, wake_mask); 1511 temp = readl(port->addr); 1512 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", 1513 hcd->self.busnum, portnum1, temp); 1514 break; 1515 case USB_PORT_FEAT_BH_PORT_RESET: 1516 temp |= PORT_WR; 1517 writel(temp, port->addr); 1518 temp = readl(port->addr); 1519 break; 1520 case USB_PORT_FEAT_U1_TIMEOUT: 1521 if (hcd->speed < HCD_USB3) 1522 goto error; 1523 temp = readl(port->addr + PORTPMSC); 1524 temp &= ~PORT_U1_TIMEOUT_MASK; 1525 temp |= PORT_U1_TIMEOUT(timeout); 1526 writel(temp, port->addr + PORTPMSC); 1527 break; 1528 case USB_PORT_FEAT_U2_TIMEOUT: 1529 if (hcd->speed < HCD_USB3) 1530 goto error; 1531 temp = readl(port->addr + PORTPMSC); 1532 temp &= ~PORT_U2_TIMEOUT_MASK; 1533 temp |= PORT_U2_TIMEOUT(timeout); 1534 writel(temp, port->addr + PORTPMSC); 1535 break; 1536 case USB_PORT_FEAT_TEST: 1537 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1538 if (hcd->speed != HCD_USB2) 1539 goto error; 1540 if (test_mode > USB_TEST_FORCE_ENABLE || 1541 test_mode < USB_TEST_J) 1542 goto error; 1543 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, 1544 &flags); 1545 break; 1546 default: 1547 goto error; 1548 } 1549 /* unblock any posted writes */ 1550 temp = readl(port->addr); 1551 break; 1552 case ClearPortFeature: 1553 if (!portnum1 || portnum1 > max_ports) 1554 goto error; 1555 1556 port = ports[portnum1 - 1]; 1557 1558 wIndex--; 1559 temp = readl(port->addr); 1560 if (temp == ~(u32)0) { 1561 xhci_hc_died(xhci); 1562 retval = -ENODEV; 1563 break; 1564 } 1565 /* FIXME: What new port features do we need to support? */ 1566 temp = xhci_port_state_to_neutral(temp); 1567 switch (wValue) { 1568 case USB_PORT_FEAT_SUSPEND: 1569 temp = readl(port->addr); 1570 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1571 xhci_dbg(xhci, "PORTSC %04x\n", temp); 1572 if (temp & PORT_RESET) 1573 goto error; 1574 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 1575 if ((temp & PORT_PE) == 0) 1576 goto error; 1577 1578 set_bit(wIndex, &bus_state->resuming_ports); 1579 usb_hcd_start_port_resume(&hcd->self, wIndex); 1580 xhci_set_link_state(xhci, port, XDEV_RESUME); 1581 spin_unlock_irqrestore(&xhci->lock, flags); 1582 msleep(USB_RESUME_TIMEOUT); 1583 spin_lock_irqsave(&xhci->lock, flags); 1584 xhci_set_link_state(xhci, port, XDEV_U0); 1585 clear_bit(wIndex, &bus_state->resuming_ports); 1586 usb_hcd_end_port_resume(&hcd->self, wIndex); 1587 } 1588 bus_state->port_c_suspend |= 1 << wIndex; 1589 1590 if (!port->slot_id) { 1591 xhci_dbg(xhci, "slot_id is zero\n"); 1592 goto error; 1593 } 1594 xhci_ring_device(xhci, port->slot_id); 1595 break; 1596 case USB_PORT_FEAT_C_SUSPEND: 1597 bus_state->port_c_suspend &= ~(1 << wIndex); 1598 fallthrough; 1599 case USB_PORT_FEAT_C_RESET: 1600 case USB_PORT_FEAT_C_BH_PORT_RESET: 1601 case USB_PORT_FEAT_C_CONNECTION: 1602 case USB_PORT_FEAT_C_OVER_CURRENT: 1603 case USB_PORT_FEAT_C_ENABLE: 1604 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1605 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1606 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1607 port->addr, temp); 1608 break; 1609 case USB_PORT_FEAT_ENABLE: 1610 xhci_disable_port(xhci, port); 1611 break; 1612 case USB_PORT_FEAT_POWER: 1613 xhci_set_port_power(xhci, port, false, &flags); 1614 break; 1615 case USB_PORT_FEAT_TEST: 1616 retval = xhci_exit_test_mode(xhci); 1617 break; 1618 default: 1619 goto error; 1620 } 1621 break; 1622 default: 1623 error: 1624 /* "stall" on error */ 1625 retval = -EPIPE; 1626 } 1627 spin_unlock_irqrestore(&xhci->lock, flags); 1628 return retval; 1629 } 1630 EXPORT_SYMBOL_GPL(xhci_hub_control); 1631 1632 /* 1633 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1634 * Ports are 0-indexed from the HCD point of view, 1635 * and 1-indexed from the USB core pointer of view. 1636 * 1637 * Note that the status change bits will be cleared as soon as a port status 1638 * change event is generated, so we use the saved status from that event. 1639 */ 1640 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1641 { 1642 unsigned long flags; 1643 u32 temp, status; 1644 u32 mask; 1645 int i, retval; 1646 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1647 int max_ports; 1648 struct xhci_bus_state *bus_state; 1649 bool reset_change = false; 1650 struct xhci_hub *rhub; 1651 struct xhci_port **ports; 1652 1653 rhub = xhci_get_rhub(hcd); 1654 ports = rhub->ports; 1655 max_ports = rhub->num_ports; 1656 bus_state = &rhub->bus_state; 1657 1658 /* Initial status is no changes */ 1659 retval = (max_ports + 8) / 8; 1660 memset(buf, 0, retval); 1661 1662 /* 1663 * Inform the usbcore about resume-in-progress by returning 1664 * a non-zero value even if there are no status changes. 1665 */ 1666 spin_lock_irqsave(&xhci->lock, flags); 1667 1668 status = bus_state->resuming_ports; 1669 1670 /* 1671 * SS devices are only visible to roothub after link training completes. 1672 * Keep polling roothubs for a grace period after xHC start 1673 */ 1674 if (xhci->run_graceperiod) { 1675 if (time_before(jiffies, xhci->run_graceperiod)) 1676 status = 1; 1677 else 1678 xhci->run_graceperiod = 0; 1679 } 1680 1681 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1682 1683 /* For each port, did anything change? If so, set that bit in buf. */ 1684 for (i = 0; i < max_ports; i++) { 1685 temp = readl(ports[i]->addr); 1686 if (temp == ~(u32)0) { 1687 xhci_hc_died(xhci); 1688 retval = -ENODEV; 1689 break; 1690 } 1691 trace_xhci_hub_status_data(ports[i], temp); 1692 1693 if ((temp & mask) != 0 || 1694 (bus_state->port_c_suspend & 1 << i) || 1695 (ports[i]->resume_timestamp && time_after_eq( 1696 jiffies, ports[i]->resume_timestamp))) { 1697 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1698 status = 1; 1699 } 1700 if ((temp & PORT_RC)) 1701 reset_change = true; 1702 if (temp & PORT_OC) 1703 status = 1; 1704 } 1705 if (!status && !reset_change) { 1706 xhci_dbg(xhci, "%s: stopping usb%d port polling\n", 1707 __func__, hcd->self.busnum); 1708 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1709 } 1710 spin_unlock_irqrestore(&xhci->lock, flags); 1711 return status ? retval : 0; 1712 } 1713 1714 #ifdef CONFIG_PM 1715 1716 int xhci_bus_suspend(struct usb_hcd *hcd) 1717 { 1718 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1719 int max_ports, port_index; 1720 struct xhci_bus_state *bus_state; 1721 unsigned long flags; 1722 struct xhci_hub *rhub; 1723 struct xhci_port **ports; 1724 u32 portsc_buf[USB_MAXCHILDREN]; 1725 bool wake_enabled; 1726 1727 rhub = xhci_get_rhub(hcd); 1728 ports = rhub->ports; 1729 max_ports = rhub->num_ports; 1730 bus_state = &rhub->bus_state; 1731 wake_enabled = hcd->self.root_hub->do_remote_wakeup; 1732 1733 spin_lock_irqsave(&xhci->lock, flags); 1734 1735 if (wake_enabled) { 1736 if (bus_state->resuming_ports || /* USB2 */ 1737 bus_state->port_remote_wakeup) { /* USB3 */ 1738 spin_unlock_irqrestore(&xhci->lock, flags); 1739 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n", 1740 hcd->self.busnum); 1741 return -EBUSY; 1742 } 1743 } 1744 /* 1745 * Prepare ports for suspend, but don't write anything before all ports 1746 * are checked and we know bus suspend can proceed 1747 */ 1748 bus_state->bus_suspended = 0; 1749 port_index = max_ports; 1750 while (port_index--) { 1751 u32 t1, t2; 1752 int retries = 10; 1753 retry: 1754 t1 = readl(ports[port_index]->addr); 1755 t2 = xhci_port_state_to_neutral(t1); 1756 portsc_buf[port_index] = 0; 1757 1758 /* 1759 * Give a USB3 port in link training time to finish, but don't 1760 * prevent suspend as port might be stuck 1761 */ 1762 if ((hcd->speed >= HCD_USB3) && retries-- && 1763 (t1 & PORT_PLS_MASK) == XDEV_POLLING) { 1764 spin_unlock_irqrestore(&xhci->lock, flags); 1765 msleep(XHCI_PORT_POLLING_LFPS_TIME); 1766 spin_lock_irqsave(&xhci->lock, flags); 1767 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", 1768 hcd->self.busnum, port_index + 1); 1769 goto retry; 1770 } 1771 /* bail out if port detected a over-current condition */ 1772 if (t1 & PORT_OC) { 1773 bus_state->bus_suspended = 0; 1774 spin_unlock_irqrestore(&xhci->lock, flags); 1775 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); 1776 return -EBUSY; 1777 } 1778 /* suspend ports in U0, or bail out for new connect changes */ 1779 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { 1780 if ((t1 & PORT_CSC) && wake_enabled) { 1781 bus_state->bus_suspended = 0; 1782 spin_unlock_irqrestore(&xhci->lock, flags); 1783 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); 1784 return -EBUSY; 1785 } 1786 xhci_dbg(xhci, "port %d-%d not suspended\n", 1787 hcd->self.busnum, port_index + 1); 1788 t2 &= ~PORT_PLS_MASK; 1789 t2 |= PORT_LINK_STROBE | XDEV_U3; 1790 set_bit(port_index, &bus_state->bus_suspended); 1791 } 1792 /* USB core sets remote wake mask for USB 3.0 hubs, 1793 * including the USB 3.0 roothub, but only if CONFIG_PM 1794 * is enabled, so also enable remote wake here. 1795 */ 1796 if (wake_enabled) { 1797 if (t1 & PORT_CONNECT) { 1798 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1799 t2 &= ~PORT_WKCONN_E; 1800 } else { 1801 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1802 t2 &= ~PORT_WKDISC_E; 1803 } 1804 1805 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1806 (hcd->speed < HCD_USB3)) { 1807 if (usb_amd_pt_check_port(hcd->self.controller, 1808 port_index)) 1809 t2 &= ~PORT_WAKE_BITS; 1810 } 1811 } else 1812 t2 &= ~PORT_WAKE_BITS; 1813 1814 t1 = xhci_port_state_to_neutral(t1); 1815 if (t1 != t2) 1816 portsc_buf[port_index] = t2; 1817 } 1818 1819 /* write port settings, stopping and suspending ports if needed */ 1820 port_index = max_ports; 1821 while (port_index--) { 1822 if (!portsc_buf[port_index]) 1823 continue; 1824 if (test_bit(port_index, &bus_state->bus_suspended)) { 1825 int slot_id = ports[port_index]->slot_id; 1826 if (slot_id) { 1827 spin_unlock_irqrestore(&xhci->lock, flags); 1828 xhci_stop_device(xhci, slot_id, 1); 1829 spin_lock_irqsave(&xhci->lock, flags); 1830 } 1831 } 1832 writel(portsc_buf[port_index], ports[port_index]->addr); 1833 } 1834 hcd->state = HC_STATE_SUSPENDED; 1835 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1836 spin_unlock_irqrestore(&xhci->lock, flags); 1837 1838 if (bus_state->bus_suspended) 1839 usleep_range(5000, 10000); 1840 1841 return 0; 1842 } 1843 1844 /* 1845 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1846 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1847 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1848 */ 1849 static bool xhci_port_missing_cas_quirk(struct xhci_port *port) 1850 { 1851 u32 portsc; 1852 1853 portsc = readl(port->addr); 1854 1855 /* if any of these are set we are not stuck */ 1856 if (portsc & (PORT_CONNECT | PORT_CAS)) 1857 return false; 1858 1859 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1860 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1861 return false; 1862 1863 /* clear wakeup/change bits, and do a warm port reset */ 1864 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1865 portsc |= PORT_WR; 1866 writel(portsc, port->addr); 1867 /* flush write */ 1868 readl(port->addr); 1869 return true; 1870 } 1871 1872 int xhci_bus_resume(struct usb_hcd *hcd) 1873 { 1874 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1875 struct xhci_bus_state *bus_state; 1876 unsigned long flags; 1877 int max_ports, port_index; 1878 int sret; 1879 u32 next_state; 1880 u32 portsc; 1881 struct xhci_hub *rhub; 1882 struct xhci_port **ports; 1883 bool disabled_irq = false; 1884 1885 rhub = xhci_get_rhub(hcd); 1886 ports = rhub->ports; 1887 max_ports = rhub->num_ports; 1888 bus_state = &rhub->bus_state; 1889 1890 if (time_before(jiffies, bus_state->next_statechange)) 1891 msleep(5); 1892 1893 spin_lock_irqsave(&xhci->lock, flags); 1894 if (!HCD_HW_ACCESSIBLE(hcd)) { 1895 spin_unlock_irqrestore(&xhci->lock, flags); 1896 return -ESHUTDOWN; 1897 } 1898 1899 /* bus specific resume for ports we suspended at bus_suspend */ 1900 if (hcd->speed >= HCD_USB3) { 1901 next_state = XDEV_U0; 1902 } else { 1903 next_state = XDEV_RESUME; 1904 if (bus_state->bus_suspended) { 1905 /* 1906 * prevent port event interrupts from interfering 1907 * with usb2 port resume process 1908 */ 1909 xhci_disable_interrupter(xhci, xhci->interrupters[0]); 1910 disabled_irq = true; 1911 } 1912 } 1913 port_index = max_ports; 1914 while (port_index--) { 1915 portsc = readl(ports[port_index]->addr); 1916 1917 /* warm reset CAS limited ports stuck in polling/compliance */ 1918 if ((xhci->quirks & XHCI_MISSING_CAS) && 1919 (hcd->speed >= HCD_USB3) && 1920 xhci_port_missing_cas_quirk(ports[port_index])) { 1921 xhci_dbg(xhci, "reset stuck port %d-%d\n", 1922 hcd->self.busnum, port_index + 1); 1923 clear_bit(port_index, &bus_state->bus_suspended); 1924 continue; 1925 } 1926 /* resume if we suspended the link, and it is still suspended */ 1927 if (test_bit(port_index, &bus_state->bus_suspended)) 1928 switch (portsc & PORT_PLS_MASK) { 1929 case XDEV_U3: 1930 portsc = xhci_port_state_to_neutral(portsc); 1931 portsc &= ~PORT_PLS_MASK; 1932 portsc |= PORT_LINK_STROBE | next_state; 1933 break; 1934 case XDEV_RESUME: 1935 /* resume already initiated */ 1936 break; 1937 default: 1938 /* not in a resumable state, ignore it */ 1939 clear_bit(port_index, 1940 &bus_state->bus_suspended); 1941 break; 1942 } 1943 /* disable wake for all ports, write new link state if needed */ 1944 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1945 writel(portsc, ports[port_index]->addr); 1946 } 1947 1948 /* USB2 specific resume signaling delay and U0 link state transition */ 1949 if (hcd->speed < HCD_USB3) { 1950 if (bus_state->bus_suspended) { 1951 spin_unlock_irqrestore(&xhci->lock, flags); 1952 msleep(USB_RESUME_TIMEOUT); 1953 spin_lock_irqsave(&xhci->lock, flags); 1954 } 1955 for_each_set_bit(port_index, &bus_state->bus_suspended, 1956 BITS_PER_LONG) { 1957 /* Clear PLC to poll it later for U0 transition */ 1958 xhci_test_and_clear_bit(xhci, ports[port_index], 1959 PORT_PLC); 1960 xhci_set_link_state(xhci, ports[port_index], XDEV_U0); 1961 } 1962 } 1963 1964 /* poll for U0 link state complete, both USB2 and USB3 */ 1965 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1966 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, 1967 PORT_PLC, 10 * 1000); 1968 if (sret) { 1969 xhci_warn(xhci, "port %d-%d resume PLC timeout\n", 1970 hcd->self.busnum, port_index + 1); 1971 continue; 1972 } 1973 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); 1974 if (ports[port_index]->slot_id) 1975 xhci_ring_device(xhci, ports[port_index]->slot_id); 1976 } 1977 (void) readl(&xhci->op_regs->command); 1978 1979 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1980 /* re-enable interrupter */ 1981 if (disabled_irq) 1982 xhci_enable_interrupter(xhci->interrupters[0]); 1983 1984 spin_unlock_irqrestore(&xhci->lock, flags); 1985 return 0; 1986 } 1987 1988 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) 1989 { 1990 struct xhci_hub *rhub = xhci_get_rhub(hcd); 1991 1992 /* USB3 port wakeups are reported via usb_wakeup_notification() */ 1993 return rhub->bus_state.resuming_ports; /* USB2 ports only */ 1994 } 1995 1996 #endif /* CONFIG_PM */ 1997