1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/gfp.h> 24 #include <asm/unaligned.h> 25 26 #include "xhci.h" 27 28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 30 PORT_RC | PORT_PLC | PORT_PE) 31 32 /* USB 3.0 BOS descriptor and a capability descriptor, combined */ 33 static u8 usb_bos_descriptor [] = { 34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 35 USB_DT_BOS, /* __u8 bDescriptorType */ 36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 37 0x1, /* __u8 bNumDeviceCaps */ 38 /* First device capability */ 39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 42 0x00, /* bmAttributes, LTM off by default */ 43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 44 0x03, /* bFunctionalitySupport, 45 USB 3.0 speed only */ 46 0x00, /* bU1DevExitLat, set later. */ 47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 48 }; 49 50 51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 52 struct usb_hub_descriptor *desc, int ports) 53 { 54 u16 temp; 55 56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 57 desc->bHubContrCurrent = 0; 58 59 desc->bNbrPorts = ports; 60 temp = 0; 61 /* Bits 1:0 - support per-port power switching, or power always on */ 62 if (HCC_PPC(xhci->hcc_params)) 63 temp |= HUB_CHAR_INDV_PORT_LPSM; 64 else 65 temp |= HUB_CHAR_NO_LPSM; 66 /* Bit 2 - root hubs are not part of a compound device */ 67 /* Bits 4:3 - individual port over current protection */ 68 temp |= HUB_CHAR_INDV_PORT_OCPM; 69 /* Bits 6:5 - no TTs in root ports */ 70 /* Bit 7 - no port indicators */ 71 desc->wHubCharacteristics = cpu_to_le16(temp); 72 } 73 74 /* Fill in the USB 2.0 roothub descriptor */ 75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 76 struct usb_hub_descriptor *desc) 77 { 78 int ports; 79 u16 temp; 80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 81 u32 portsc; 82 unsigned int i; 83 84 ports = xhci->num_usb2_ports; 85 86 xhci_common_hub_descriptor(xhci, desc, ports); 87 desc->bDescriptorType = USB_DT_HUB; 88 temp = 1 + (ports / 8); 89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 90 91 /* The Device Removable bits are reported on a byte granularity. 92 * If the port doesn't exist within that byte, the bit is set to 0. 93 */ 94 memset(port_removable, 0, sizeof(port_removable)); 95 for (i = 0; i < ports; i++) { 96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]); 97 /* If a device is removable, PORTSC reports a 0, same as in the 98 * hub descriptor DeviceRemovable bits. 99 */ 100 if (portsc & PORT_DEV_REMOVE) 101 /* This math is hairy because bit 0 of DeviceRemovable 102 * is reserved, and bit 1 is for port 1, etc. 103 */ 104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 105 } 106 107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 108 * ports on it. The USB 2.0 specification says that there are two 109 * variable length fields at the end of the hub descriptor: 110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 113 * 0xFF, so we initialize the both arrays (DeviceRemovable and 114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 115 * set of ports that actually exist. 116 */ 117 memset(desc->u.hs.DeviceRemovable, 0xff, 118 sizeof(desc->u.hs.DeviceRemovable)); 119 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 120 sizeof(desc->u.hs.PortPwrCtrlMask)); 121 122 for (i = 0; i < (ports + 1 + 7) / 8; i++) 123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 124 sizeof(__u8)); 125 } 126 127 /* Fill in the USB 3.0 roothub descriptor */ 128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 129 struct usb_hub_descriptor *desc) 130 { 131 int ports; 132 u16 port_removable; 133 u32 portsc; 134 unsigned int i; 135 136 ports = xhci->num_usb3_ports; 137 xhci_common_hub_descriptor(xhci, desc, ports); 138 desc->bDescriptorType = USB_DT_SS_HUB; 139 desc->bDescLength = USB_DT_SS_HUB_SIZE; 140 141 /* header decode latency should be zero for roothubs, 142 * see section 4.23.5.2. 143 */ 144 desc->u.ss.bHubHdrDecLat = 0; 145 desc->u.ss.wHubDelay = 0; 146 147 port_removable = 0; 148 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 149 for (i = 0; i < ports; i++) { 150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]); 151 if (portsc & PORT_DEV_REMOVE) 152 port_removable |= 1 << (i + 1); 153 } 154 memset(&desc->u.ss.DeviceRemovable, 155 (__force __u16) cpu_to_le16(port_removable), 156 sizeof(__u16)); 157 } 158 159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 160 struct usb_hub_descriptor *desc) 161 { 162 163 if (hcd->speed == HCD_USB3) 164 xhci_usb3_hub_descriptor(hcd, xhci, desc); 165 else 166 xhci_usb2_hub_descriptor(hcd, xhci, desc); 167 168 } 169 170 static unsigned int xhci_port_speed(unsigned int port_status) 171 { 172 if (DEV_LOWSPEED(port_status)) 173 return USB_PORT_STAT_LOW_SPEED; 174 if (DEV_HIGHSPEED(port_status)) 175 return USB_PORT_STAT_HIGH_SPEED; 176 /* 177 * FIXME: Yes, we should check for full speed, but the core uses that as 178 * a default in portspeed() in usb/core/hub.c (which is the only place 179 * USB_PORT_STAT_*_SPEED is used). 180 */ 181 return 0; 182 } 183 184 /* 185 * These bits are Read Only (RO) and should be saved and written to the 186 * registers: 0, 3, 10:13, 30 187 * connect status, over-current status, port speed, and device removable. 188 * connect status and port speed are also sticky - meaning they're in 189 * the AUX well and they aren't changed by a hot, warm, or cold reset. 190 */ 191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 192 /* 193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 194 * bits 5:8, 9, 14:15, 25:27 195 * link state, port power, port indicator state, "wake on" enable state 196 */ 197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 198 /* 199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 200 * bit 4 (port reset) 201 */ 202 #define XHCI_PORT_RW1S ((1<<4)) 203 /* 204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 205 * bits 1, 17, 18, 19, 20, 21, 22, 23 206 * port enable/disable, and 207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 208 * over-current, reset, link state, and L1 change 209 */ 210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 211 /* 212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 213 * latched in 214 */ 215 #define XHCI_PORT_RW ((1<<16)) 216 /* 217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 218 * bits 2, 24, 28:31 219 */ 220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 221 222 /* 223 * Given a port state, this function returns a value that would result in the 224 * port being in the same state, if the value was written to the port status 225 * control register. 226 * Save Read Only (RO) bits and save read/write bits where 227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 229 */ 230 u32 xhci_port_state_to_neutral(u32 state) 231 { 232 /* Save read-only status and port state */ 233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 234 } 235 236 /* 237 * find slot id based on port number. 238 * @port: The one-based port number from one of the two split roothubs. 239 */ 240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 241 u16 port) 242 { 243 int slot_id; 244 int i; 245 enum usb_device_speed speed; 246 247 slot_id = 0; 248 for (i = 0; i < MAX_HC_SLOTS; i++) { 249 if (!xhci->devs[i]) 250 continue; 251 speed = xhci->devs[i]->udev->speed; 252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 253 && xhci->devs[i]->fake_port == port) { 254 slot_id = i; 255 break; 256 } 257 } 258 259 return slot_id; 260 } 261 262 /* 263 * Stop device 264 * It issues stop endpoint command for EP 0 to 30. And wait the last command 265 * to complete. 266 * suspend will set to 1, if suspend bit need to set in command. 267 */ 268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 269 { 270 struct xhci_virt_device *virt_dev; 271 struct xhci_command *cmd; 272 unsigned long flags; 273 int timeleft; 274 int ret; 275 int i; 276 277 ret = 0; 278 virt_dev = xhci->devs[slot_id]; 279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 280 if (!cmd) { 281 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 282 return -ENOMEM; 283 } 284 285 spin_lock_irqsave(&xhci->lock, flags); 286 for (i = LAST_EP_INDEX; i > 0; i--) { 287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) 288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); 289 } 290 cmd->command_trb = xhci->cmd_ring->enqueue; 291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); 292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); 293 xhci_ring_cmd_db(xhci); 294 spin_unlock_irqrestore(&xhci->lock, flags); 295 296 /* Wait for last stop endpoint command to finish */ 297 timeleft = wait_for_completion_interruptible_timeout( 298 cmd->completion, 299 USB_CTRL_SET_TIMEOUT); 300 if (timeleft <= 0) { 301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n", 302 timeleft == 0 ? "Timeout" : "Signal"); 303 spin_lock_irqsave(&xhci->lock, flags); 304 /* The timeout might have raced with the event ring handler, so 305 * only delete from the list if the item isn't poisoned. 306 */ 307 if (cmd->cmd_list.next != LIST_POISON1) 308 list_del(&cmd->cmd_list); 309 spin_unlock_irqrestore(&xhci->lock, flags); 310 ret = -ETIME; 311 goto command_cleanup; 312 } 313 314 command_cleanup: 315 xhci_free_command(xhci, cmd); 316 return ret; 317 } 318 319 /* 320 * Ring device, it rings the all doorbells unconditionally. 321 */ 322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 323 { 324 int i; 325 326 for (i = 0; i < LAST_EP_INDEX + 1; i++) 327 if (xhci->devs[slot_id]->eps[i].ring && 328 xhci->devs[slot_id]->eps[i].ring->dequeue) 329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 330 331 return; 332 } 333 334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 u16 wIndex, __le32 __iomem *addr, u32 port_status) 336 { 337 /* Don't allow the USB core to disable SuperSpeed ports. */ 338 if (hcd->speed == HCD_USB3) { 339 xhci_dbg(xhci, "Ignoring request to disable " 340 "SuperSpeed port.\n"); 341 return; 342 } 343 344 /* Write 1 to disable the port */ 345 xhci_writel(xhci, port_status | PORT_PE, addr); 346 port_status = xhci_readl(xhci, addr); 347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 348 wIndex, port_status); 349 } 350 351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 352 u16 wIndex, __le32 __iomem *addr, u32 port_status) 353 { 354 char *port_change_bit; 355 u32 status; 356 357 switch (wValue) { 358 case USB_PORT_FEAT_C_RESET: 359 status = PORT_RC; 360 port_change_bit = "reset"; 361 break; 362 case USB_PORT_FEAT_C_BH_PORT_RESET: 363 status = PORT_WRC; 364 port_change_bit = "warm(BH) reset"; 365 break; 366 case USB_PORT_FEAT_C_CONNECTION: 367 status = PORT_CSC; 368 port_change_bit = "connect"; 369 break; 370 case USB_PORT_FEAT_C_OVER_CURRENT: 371 status = PORT_OCC; 372 port_change_bit = "over-current"; 373 break; 374 case USB_PORT_FEAT_C_ENABLE: 375 status = PORT_PEC; 376 port_change_bit = "enable/disable"; 377 break; 378 case USB_PORT_FEAT_C_SUSPEND: 379 status = PORT_PLC; 380 port_change_bit = "suspend/resume"; 381 break; 382 case USB_PORT_FEAT_C_PORT_LINK_STATE: 383 status = PORT_PLC; 384 port_change_bit = "link state"; 385 break; 386 default: 387 /* Should never happen */ 388 return; 389 } 390 /* Change bits are all write 1 to clear */ 391 xhci_writel(xhci, port_status | status, addr); 392 port_status = xhci_readl(xhci, addr); 393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 394 port_change_bit, wIndex, port_status); 395 } 396 397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 398 { 399 int max_ports; 400 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 401 402 if (hcd->speed == HCD_USB3) { 403 max_ports = xhci->num_usb3_ports; 404 *port_array = xhci->usb3_ports; 405 } else { 406 max_ports = xhci->num_usb2_ports; 407 *port_array = xhci->usb2_ports; 408 } 409 410 return max_ports; 411 } 412 413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 414 int port_id, u32 link_state) 415 { 416 u32 temp; 417 418 temp = xhci_readl(xhci, port_array[port_id]); 419 temp = xhci_port_state_to_neutral(temp); 420 temp &= ~PORT_PLS_MASK; 421 temp |= PORT_LINK_STROBE | link_state; 422 xhci_writel(xhci, temp, port_array[port_id]); 423 } 424 425 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 426 __le32 __iomem **port_array, int port_id, u16 wake_mask) 427 { 428 u32 temp; 429 430 temp = xhci_readl(xhci, port_array[port_id]); 431 temp = xhci_port_state_to_neutral(temp); 432 433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 434 temp |= PORT_WKCONN_E; 435 else 436 temp &= ~PORT_WKCONN_E; 437 438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 439 temp |= PORT_WKDISC_E; 440 else 441 temp &= ~PORT_WKDISC_E; 442 443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 444 temp |= PORT_WKOC_E; 445 else 446 temp &= ~PORT_WKOC_E; 447 448 xhci_writel(xhci, temp, port_array[port_id]); 449 } 450 451 /* Test and clear port RWC bit */ 452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 453 int port_id, u32 port_bit) 454 { 455 u32 temp; 456 457 temp = xhci_readl(xhci, port_array[port_id]); 458 if (temp & port_bit) { 459 temp = xhci_port_state_to_neutral(temp); 460 temp |= port_bit; 461 xhci_writel(xhci, temp, port_array[port_id]); 462 } 463 } 464 465 /* Updates Link Status for super Speed port */ 466 static void xhci_hub_report_link_state(u32 *status, u32 status_reg) 467 { 468 u32 pls = status_reg & PORT_PLS_MASK; 469 470 /* resume state is a xHCI internal state. 471 * Do not report it to usb core. 472 */ 473 if (pls == XDEV_RESUME) 474 return; 475 476 /* When the CAS bit is set then warm reset 477 * should be performed on port 478 */ 479 if (status_reg & PORT_CAS) { 480 /* The CAS bit can be set while the port is 481 * in any link state. 482 * Only roothubs have CAS bit, so we 483 * pretend to be in compliance mode 484 * unless we're already in compliance 485 * or the inactive state. 486 */ 487 if (pls != USB_SS_PORT_LS_COMP_MOD && 488 pls != USB_SS_PORT_LS_SS_INACTIVE) { 489 pls = USB_SS_PORT_LS_COMP_MOD; 490 } 491 /* Return also connection bit - 492 * hub state machine resets port 493 * when this bit is set. 494 */ 495 pls |= USB_PORT_STAT_CONNECTION; 496 } else { 497 /* 498 * If CAS bit isn't set but the Port is already at 499 * Compliance Mode, fake a connection so the USB core 500 * notices the Compliance state and resets the port. 501 * This resolves an issue generated by the SN65LVPE502CP 502 * in which sometimes the port enters compliance mode 503 * caused by a delay on the host-device negotiation. 504 */ 505 if (pls == USB_SS_PORT_LS_COMP_MOD) 506 pls |= USB_PORT_STAT_CONNECTION; 507 } 508 509 /* update status field */ 510 *status |= pls; 511 } 512 513 /* 514 * Function for Compliance Mode Quirk. 515 * 516 * This Function verifies if all xhc USB3 ports have entered U0, if so, 517 * the compliance mode timer is deleted. A port won't enter 518 * compliance mode if it has previously entered U0. 519 */ 520 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex) 521 { 522 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); 523 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 524 525 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 526 return; 527 528 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 529 xhci->port_status_u0 |= 1 << wIndex; 530 if (xhci->port_status_u0 == all_ports_seen_u0) { 531 del_timer_sync(&xhci->comp_mode_recovery_timer); 532 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n"); 533 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n"); 534 } 535 } 536 } 537 538 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 539 u16 wIndex, char *buf, u16 wLength) 540 { 541 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 542 int max_ports; 543 unsigned long flags; 544 u32 temp, status; 545 int retval = 0; 546 __le32 __iomem **port_array; 547 int slot_id; 548 struct xhci_bus_state *bus_state; 549 u16 link_state = 0; 550 u16 wake_mask = 0; 551 u16 timeout = 0; 552 553 max_ports = xhci_get_ports(hcd, &port_array); 554 bus_state = &xhci->bus_state[hcd_index(hcd)]; 555 556 spin_lock_irqsave(&xhci->lock, flags); 557 switch (typeReq) { 558 case GetHubStatus: 559 /* No power source, over-current reported per port */ 560 memset(buf, 0, 4); 561 break; 562 case GetHubDescriptor: 563 /* Check to make sure userspace is asking for the USB 3.0 hub 564 * descriptor for the USB 3.0 roothub. If not, we stall the 565 * endpoint, like external hubs do. 566 */ 567 if (hcd->speed == HCD_USB3 && 568 (wLength < USB_DT_SS_HUB_SIZE || 569 wValue != (USB_DT_SS_HUB << 8))) { 570 xhci_dbg(xhci, "Wrong hub descriptor type for " 571 "USB 3.0 roothub.\n"); 572 goto error; 573 } 574 xhci_hub_descriptor(hcd, xhci, 575 (struct usb_hub_descriptor *) buf); 576 break; 577 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 578 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 579 goto error; 580 581 if (hcd->speed != HCD_USB3) 582 goto error; 583 584 /* Set the U1 and U2 exit latencies. */ 585 memcpy(buf, &usb_bos_descriptor, 586 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 587 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); 588 buf[12] = HCS_U1_LATENCY(temp); 589 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 590 591 /* Indicate whether the host has LTM support. */ 592 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); 593 if (HCC_LTC(temp)) 594 buf[8] |= USB_LTM_SUPPORT; 595 596 spin_unlock_irqrestore(&xhci->lock, flags); 597 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 598 case GetPortStatus: 599 if (!wIndex || wIndex > max_ports) 600 goto error; 601 wIndex--; 602 status = 0; 603 temp = xhci_readl(xhci, port_array[wIndex]); 604 if (temp == 0xffffffff) { 605 retval = -ENODEV; 606 break; 607 } 608 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); 609 610 /* wPortChange bits */ 611 if (temp & PORT_CSC) 612 status |= USB_PORT_STAT_C_CONNECTION << 16; 613 if (temp & PORT_PEC) 614 status |= USB_PORT_STAT_C_ENABLE << 16; 615 if ((temp & PORT_OCC)) 616 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 617 if ((temp & PORT_RC)) 618 status |= USB_PORT_STAT_C_RESET << 16; 619 /* USB3.0 only */ 620 if (hcd->speed == HCD_USB3) { 621 if ((temp & PORT_PLC)) 622 status |= USB_PORT_STAT_C_LINK_STATE << 16; 623 if ((temp & PORT_WRC)) 624 status |= USB_PORT_STAT_C_BH_RESET << 16; 625 } 626 627 if (hcd->speed != HCD_USB3) { 628 if ((temp & PORT_PLS_MASK) == XDEV_U3 629 && (temp & PORT_POWER)) 630 status |= USB_PORT_STAT_SUSPEND; 631 } 632 if ((temp & PORT_PLS_MASK) == XDEV_RESUME && 633 !DEV_SUPERSPEED(temp)) { 634 if ((temp & PORT_RESET) || !(temp & PORT_PE)) 635 goto error; 636 if (time_after_eq(jiffies, 637 bus_state->resume_done[wIndex])) { 638 xhci_dbg(xhci, "Resume USB2 port %d\n", 639 wIndex + 1); 640 bus_state->resume_done[wIndex] = 0; 641 clear_bit(wIndex, &bus_state->resuming_ports); 642 xhci_set_link_state(xhci, port_array, wIndex, 643 XDEV_U0); 644 xhci_dbg(xhci, "set port %d resume\n", 645 wIndex + 1); 646 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 647 wIndex + 1); 648 if (!slot_id) { 649 xhci_dbg(xhci, "slot_id is zero\n"); 650 goto error; 651 } 652 xhci_ring_device(xhci, slot_id); 653 bus_state->port_c_suspend |= 1 << wIndex; 654 bus_state->suspended_ports &= ~(1 << wIndex); 655 } else { 656 /* 657 * The resume has been signaling for less than 658 * 20ms. Report the port status as SUSPEND, 659 * let the usbcore check port status again 660 * and clear resume signaling later. 661 */ 662 status |= USB_PORT_STAT_SUSPEND; 663 } 664 } 665 if ((temp & PORT_PLS_MASK) == XDEV_U0 666 && (temp & PORT_POWER) 667 && (bus_state->suspended_ports & (1 << wIndex))) { 668 bus_state->suspended_ports &= ~(1 << wIndex); 669 if (hcd->speed != HCD_USB3) 670 bus_state->port_c_suspend |= 1 << wIndex; 671 } 672 if (temp & PORT_CONNECT) { 673 status |= USB_PORT_STAT_CONNECTION; 674 status |= xhci_port_speed(temp); 675 } 676 if (temp & PORT_PE) 677 status |= USB_PORT_STAT_ENABLE; 678 if (temp & PORT_OC) 679 status |= USB_PORT_STAT_OVERCURRENT; 680 if (temp & PORT_RESET) 681 status |= USB_PORT_STAT_RESET; 682 if (temp & PORT_POWER) { 683 if (hcd->speed == HCD_USB3) 684 status |= USB_SS_PORT_STAT_POWER; 685 else 686 status |= USB_PORT_STAT_POWER; 687 } 688 /* Update Port Link State for super speed ports*/ 689 if (hcd->speed == HCD_USB3) { 690 xhci_hub_report_link_state(&status, temp); 691 /* 692 * Verify if all USB3 Ports Have entered U0 already. 693 * Delete Compliance Mode Timer if so. 694 */ 695 xhci_del_comp_mod_timer(xhci, temp, wIndex); 696 } 697 if (bus_state->port_c_suspend & (1 << wIndex)) 698 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 699 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 700 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 701 break; 702 case SetPortFeature: 703 if (wValue == USB_PORT_FEAT_LINK_STATE) 704 link_state = (wIndex & 0xff00) >> 3; 705 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 706 wake_mask = wIndex & 0xff00; 707 /* The MSB of wIndex is the U1/U2 timeout */ 708 timeout = (wIndex & 0xff00) >> 8; 709 wIndex &= 0xff; 710 if (!wIndex || wIndex > max_ports) 711 goto error; 712 wIndex--; 713 temp = xhci_readl(xhci, port_array[wIndex]); 714 if (temp == 0xffffffff) { 715 retval = -ENODEV; 716 break; 717 } 718 temp = xhci_port_state_to_neutral(temp); 719 /* FIXME: What new port features do we need to support? */ 720 switch (wValue) { 721 case USB_PORT_FEAT_SUSPEND: 722 temp = xhci_readl(xhci, port_array[wIndex]); 723 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 724 /* Resume the port to U0 first */ 725 xhci_set_link_state(xhci, port_array, wIndex, 726 XDEV_U0); 727 spin_unlock_irqrestore(&xhci->lock, flags); 728 msleep(10); 729 spin_lock_irqsave(&xhci->lock, flags); 730 } 731 /* In spec software should not attempt to suspend 732 * a port unless the port reports that it is in the 733 * enabled (PED = ‘1’,PLS < ‘3’) state. 734 */ 735 temp = xhci_readl(xhci, port_array[wIndex]); 736 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 737 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 738 xhci_warn(xhci, "USB core suspending device " 739 "not in U0/U1/U2.\n"); 740 goto error; 741 } 742 743 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 744 wIndex + 1); 745 if (!slot_id) { 746 xhci_warn(xhci, "slot_id is zero\n"); 747 goto error; 748 } 749 /* unlock to execute stop endpoint commands */ 750 spin_unlock_irqrestore(&xhci->lock, flags); 751 xhci_stop_device(xhci, slot_id, 1); 752 spin_lock_irqsave(&xhci->lock, flags); 753 754 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 755 756 spin_unlock_irqrestore(&xhci->lock, flags); 757 msleep(10); /* wait device to enter */ 758 spin_lock_irqsave(&xhci->lock, flags); 759 760 temp = xhci_readl(xhci, port_array[wIndex]); 761 bus_state->suspended_ports |= 1 << wIndex; 762 break; 763 case USB_PORT_FEAT_LINK_STATE: 764 temp = xhci_readl(xhci, port_array[wIndex]); 765 /* Software should not attempt to set 766 * port link state above '5' (Rx.Detect) and the port 767 * must be enabled. 768 */ 769 if ((temp & PORT_PE) == 0 || 770 (link_state > USB_SS_PORT_LS_RX_DETECT)) { 771 xhci_warn(xhci, "Cannot set link state.\n"); 772 goto error; 773 } 774 775 if (link_state == USB_SS_PORT_LS_U3) { 776 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 777 wIndex + 1); 778 if (slot_id) { 779 /* unlock to execute stop endpoint 780 * commands */ 781 spin_unlock_irqrestore(&xhci->lock, 782 flags); 783 xhci_stop_device(xhci, slot_id, 1); 784 spin_lock_irqsave(&xhci->lock, flags); 785 } 786 } 787 788 xhci_set_link_state(xhci, port_array, wIndex, 789 link_state); 790 791 spin_unlock_irqrestore(&xhci->lock, flags); 792 msleep(20); /* wait device to enter */ 793 spin_lock_irqsave(&xhci->lock, flags); 794 795 temp = xhci_readl(xhci, port_array[wIndex]); 796 if (link_state == USB_SS_PORT_LS_U3) 797 bus_state->suspended_ports |= 1 << wIndex; 798 break; 799 case USB_PORT_FEAT_POWER: 800 /* 801 * Turn on ports, even if there isn't per-port switching. 802 * HC will report connect events even before this is set. 803 * However, khubd will ignore the roothub events until 804 * the roothub is registered. 805 */ 806 xhci_writel(xhci, temp | PORT_POWER, 807 port_array[wIndex]); 808 809 temp = xhci_readl(xhci, port_array[wIndex]); 810 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 811 812 temp = usb_acpi_power_manageable(hcd->self.root_hub, 813 wIndex); 814 if (temp) 815 usb_acpi_set_power_state(hcd->self.root_hub, 816 wIndex, true); 817 break; 818 case USB_PORT_FEAT_RESET: 819 temp = (temp | PORT_RESET); 820 xhci_writel(xhci, temp, port_array[wIndex]); 821 822 temp = xhci_readl(xhci, port_array[wIndex]); 823 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 824 break; 825 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 826 xhci_set_remote_wake_mask(xhci, port_array, 827 wIndex, wake_mask); 828 temp = xhci_readl(xhci, port_array[wIndex]); 829 xhci_dbg(xhci, "set port remote wake mask, " 830 "actual port %d status = 0x%x\n", 831 wIndex, temp); 832 break; 833 case USB_PORT_FEAT_BH_PORT_RESET: 834 temp |= PORT_WR; 835 xhci_writel(xhci, temp, port_array[wIndex]); 836 837 temp = xhci_readl(xhci, port_array[wIndex]); 838 break; 839 case USB_PORT_FEAT_U1_TIMEOUT: 840 if (hcd->speed != HCD_USB3) 841 goto error; 842 temp = xhci_readl(xhci, port_array[wIndex] + 1); 843 temp &= ~PORT_U1_TIMEOUT_MASK; 844 temp |= PORT_U1_TIMEOUT(timeout); 845 xhci_writel(xhci, temp, port_array[wIndex] + 1); 846 break; 847 case USB_PORT_FEAT_U2_TIMEOUT: 848 if (hcd->speed != HCD_USB3) 849 goto error; 850 temp = xhci_readl(xhci, port_array[wIndex] + 1); 851 temp &= ~PORT_U2_TIMEOUT_MASK; 852 temp |= PORT_U2_TIMEOUT(timeout); 853 xhci_writel(xhci, temp, port_array[wIndex] + 1); 854 break; 855 default: 856 goto error; 857 } 858 /* unblock any posted writes */ 859 temp = xhci_readl(xhci, port_array[wIndex]); 860 break; 861 case ClearPortFeature: 862 if (!wIndex || wIndex > max_ports) 863 goto error; 864 wIndex--; 865 temp = xhci_readl(xhci, port_array[wIndex]); 866 if (temp == 0xffffffff) { 867 retval = -ENODEV; 868 break; 869 } 870 /* FIXME: What new port features do we need to support? */ 871 temp = xhci_port_state_to_neutral(temp); 872 switch (wValue) { 873 case USB_PORT_FEAT_SUSPEND: 874 temp = xhci_readl(xhci, port_array[wIndex]); 875 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 876 xhci_dbg(xhci, "PORTSC %04x\n", temp); 877 if (temp & PORT_RESET) 878 goto error; 879 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 880 if ((temp & PORT_PE) == 0) 881 goto error; 882 883 xhci_set_link_state(xhci, port_array, wIndex, 884 XDEV_RESUME); 885 spin_unlock_irqrestore(&xhci->lock, flags); 886 msleep(20); 887 spin_lock_irqsave(&xhci->lock, flags); 888 xhci_set_link_state(xhci, port_array, wIndex, 889 XDEV_U0); 890 } 891 bus_state->port_c_suspend |= 1 << wIndex; 892 893 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 894 wIndex + 1); 895 if (!slot_id) { 896 xhci_dbg(xhci, "slot_id is zero\n"); 897 goto error; 898 } 899 xhci_ring_device(xhci, slot_id); 900 break; 901 case USB_PORT_FEAT_C_SUSPEND: 902 bus_state->port_c_suspend &= ~(1 << wIndex); 903 case USB_PORT_FEAT_C_RESET: 904 case USB_PORT_FEAT_C_BH_PORT_RESET: 905 case USB_PORT_FEAT_C_CONNECTION: 906 case USB_PORT_FEAT_C_OVER_CURRENT: 907 case USB_PORT_FEAT_C_ENABLE: 908 case USB_PORT_FEAT_C_PORT_LINK_STATE: 909 xhci_clear_port_change_bit(xhci, wValue, wIndex, 910 port_array[wIndex], temp); 911 break; 912 case USB_PORT_FEAT_ENABLE: 913 xhci_disable_port(hcd, xhci, wIndex, 914 port_array[wIndex], temp); 915 break; 916 case USB_PORT_FEAT_POWER: 917 xhci_writel(xhci, temp & ~PORT_POWER, 918 port_array[wIndex]); 919 920 temp = usb_acpi_power_manageable(hcd->self.root_hub, 921 wIndex); 922 if (temp) 923 usb_acpi_set_power_state(hcd->self.root_hub, 924 wIndex, false); 925 break; 926 default: 927 goto error; 928 } 929 break; 930 default: 931 error: 932 /* "stall" on error */ 933 retval = -EPIPE; 934 } 935 spin_unlock_irqrestore(&xhci->lock, flags); 936 return retval; 937 } 938 939 /* 940 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 941 * Ports are 0-indexed from the HCD point of view, 942 * and 1-indexed from the USB core pointer of view. 943 * 944 * Note that the status change bits will be cleared as soon as a port status 945 * change event is generated, so we use the saved status from that event. 946 */ 947 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 948 { 949 unsigned long flags; 950 u32 temp, status; 951 u32 mask; 952 int i, retval; 953 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 954 int max_ports; 955 __le32 __iomem **port_array; 956 struct xhci_bus_state *bus_state; 957 958 max_ports = xhci_get_ports(hcd, &port_array); 959 bus_state = &xhci->bus_state[hcd_index(hcd)]; 960 961 /* Initial status is no changes */ 962 retval = (max_ports + 8) / 8; 963 memset(buf, 0, retval); 964 965 /* 966 * Inform the usbcore about resume-in-progress by returning 967 * a non-zero value even if there are no status changes. 968 */ 969 status = bus_state->resuming_ports; 970 971 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC; 972 973 spin_lock_irqsave(&xhci->lock, flags); 974 /* For each port, did anything change? If so, set that bit in buf. */ 975 for (i = 0; i < max_ports; i++) { 976 temp = xhci_readl(xhci, port_array[i]); 977 if (temp == 0xffffffff) { 978 retval = -ENODEV; 979 break; 980 } 981 if ((temp & mask) != 0 || 982 (bus_state->port_c_suspend & 1 << i) || 983 (bus_state->resume_done[i] && time_after_eq( 984 jiffies, bus_state->resume_done[i]))) { 985 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 986 status = 1; 987 } 988 } 989 spin_unlock_irqrestore(&xhci->lock, flags); 990 return status ? retval : 0; 991 } 992 993 #ifdef CONFIG_PM 994 995 int xhci_bus_suspend(struct usb_hcd *hcd) 996 { 997 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 998 int max_ports, port_index; 999 __le32 __iomem **port_array; 1000 struct xhci_bus_state *bus_state; 1001 unsigned long flags; 1002 1003 max_ports = xhci_get_ports(hcd, &port_array); 1004 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1005 1006 spin_lock_irqsave(&xhci->lock, flags); 1007 1008 if (hcd->self.root_hub->do_remote_wakeup) { 1009 if (bus_state->resuming_ports) { 1010 spin_unlock_irqrestore(&xhci->lock, flags); 1011 xhci_dbg(xhci, "suspend failed because " 1012 "a port is resuming\n"); 1013 return -EBUSY; 1014 } 1015 } 1016 1017 port_index = max_ports; 1018 bus_state->bus_suspended = 0; 1019 while (port_index--) { 1020 /* suspend the port if the port is not suspended */ 1021 u32 t1, t2; 1022 int slot_id; 1023 1024 t1 = xhci_readl(xhci, port_array[port_index]); 1025 t2 = xhci_port_state_to_neutral(t1); 1026 1027 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 1028 xhci_dbg(xhci, "port %d not suspended\n", port_index); 1029 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1030 port_index + 1); 1031 if (slot_id) { 1032 spin_unlock_irqrestore(&xhci->lock, flags); 1033 xhci_stop_device(xhci, slot_id, 1); 1034 spin_lock_irqsave(&xhci->lock, flags); 1035 } 1036 t2 &= ~PORT_PLS_MASK; 1037 t2 |= PORT_LINK_STROBE | XDEV_U3; 1038 set_bit(port_index, &bus_state->bus_suspended); 1039 } 1040 /* USB core sets remote wake mask for USB 3.0 hubs, 1041 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND 1042 * is enabled, so also enable remote wake here. 1043 */ 1044 if (hcd->self.root_hub->do_remote_wakeup) { 1045 if (t1 & PORT_CONNECT) { 1046 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1047 t2 &= ~PORT_WKCONN_E; 1048 } else { 1049 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1050 t2 &= ~PORT_WKDISC_E; 1051 } 1052 } else 1053 t2 &= ~PORT_WAKE_BITS; 1054 1055 t1 = xhci_port_state_to_neutral(t1); 1056 if (t1 != t2) 1057 xhci_writel(xhci, t2, port_array[port_index]); 1058 1059 if (hcd->speed != HCD_USB3) { 1060 /* enable remote wake up for USB 2.0 */ 1061 __le32 __iomem *addr; 1062 u32 tmp; 1063 1064 /* Add one to the port status register address to get 1065 * the port power control register address. 1066 */ 1067 addr = port_array[port_index] + 1; 1068 tmp = xhci_readl(xhci, addr); 1069 tmp |= PORT_RWE; 1070 xhci_writel(xhci, tmp, addr); 1071 } 1072 } 1073 hcd->state = HC_STATE_SUSPENDED; 1074 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1075 spin_unlock_irqrestore(&xhci->lock, flags); 1076 return 0; 1077 } 1078 1079 int xhci_bus_resume(struct usb_hcd *hcd) 1080 { 1081 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1082 int max_ports, port_index; 1083 __le32 __iomem **port_array; 1084 struct xhci_bus_state *bus_state; 1085 u32 temp; 1086 unsigned long flags; 1087 1088 max_ports = xhci_get_ports(hcd, &port_array); 1089 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1090 1091 if (time_before(jiffies, bus_state->next_statechange)) 1092 msleep(5); 1093 1094 spin_lock_irqsave(&xhci->lock, flags); 1095 if (!HCD_HW_ACCESSIBLE(hcd)) { 1096 spin_unlock_irqrestore(&xhci->lock, flags); 1097 return -ESHUTDOWN; 1098 } 1099 1100 /* delay the irqs */ 1101 temp = xhci_readl(xhci, &xhci->op_regs->command); 1102 temp &= ~CMD_EIE; 1103 xhci_writel(xhci, temp, &xhci->op_regs->command); 1104 1105 port_index = max_ports; 1106 while (port_index--) { 1107 /* Check whether need resume ports. If needed 1108 resume port and disable remote wakeup */ 1109 u32 temp; 1110 int slot_id; 1111 1112 temp = xhci_readl(xhci, port_array[port_index]); 1113 if (DEV_SUPERSPEED(temp)) 1114 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1115 else 1116 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 1117 if (test_bit(port_index, &bus_state->bus_suspended) && 1118 (temp & PORT_PLS_MASK)) { 1119 if (DEV_SUPERSPEED(temp)) { 1120 xhci_set_link_state(xhci, port_array, 1121 port_index, XDEV_U0); 1122 } else { 1123 xhci_set_link_state(xhci, port_array, 1124 port_index, XDEV_RESUME); 1125 1126 spin_unlock_irqrestore(&xhci->lock, flags); 1127 msleep(20); 1128 spin_lock_irqsave(&xhci->lock, flags); 1129 1130 xhci_set_link_state(xhci, port_array, 1131 port_index, XDEV_U0); 1132 } 1133 /* wait for the port to enter U0 and report port link 1134 * state change. 1135 */ 1136 spin_unlock_irqrestore(&xhci->lock, flags); 1137 msleep(20); 1138 spin_lock_irqsave(&xhci->lock, flags); 1139 1140 /* Clear PLC */ 1141 xhci_test_and_clear_bit(xhci, port_array, port_index, 1142 PORT_PLC); 1143 1144 slot_id = xhci_find_slot_id_by_port(hcd, 1145 xhci, port_index + 1); 1146 if (slot_id) 1147 xhci_ring_device(xhci, slot_id); 1148 } else 1149 xhci_writel(xhci, temp, port_array[port_index]); 1150 1151 if (hcd->speed != HCD_USB3) { 1152 /* disable remote wake up for USB 2.0 */ 1153 __le32 __iomem *addr; 1154 u32 tmp; 1155 1156 /* Add one to the port status register address to get 1157 * the port power control register address. 1158 */ 1159 addr = port_array[port_index] + 1; 1160 tmp = xhci_readl(xhci, addr); 1161 tmp &= ~PORT_RWE; 1162 xhci_writel(xhci, tmp, addr); 1163 } 1164 } 1165 1166 (void) xhci_readl(xhci, &xhci->op_regs->command); 1167 1168 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1169 /* re-enable irqs */ 1170 temp = xhci_readl(xhci, &xhci->op_regs->command); 1171 temp |= CMD_EIE; 1172 xhci_writel(xhci, temp, &xhci->op_regs->command); 1173 temp = xhci_readl(xhci, &xhci->op_regs->command); 1174 1175 spin_unlock_irqrestore(&xhci->lock, flags); 1176 return 0; 1177 } 1178 1179 #endif /* CONFIG_PM */ 1180