1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/gfp.h> 24 #include <asm/unaligned.h> 25 26 #include "xhci.h" 27 28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 30 PORT_RC | PORT_PLC | PORT_PE) 31 32 /* usb 1.1 root hub device descriptor */ 33 static u8 usb_bos_descriptor [] = { 34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 35 USB_DT_BOS, /* __u8 bDescriptorType */ 36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 37 0x1, /* __u8 bNumDeviceCaps */ 38 /* First device capability */ 39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 42 0x00, /* bmAttributes, LTM off by default */ 43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 44 0x03, /* bFunctionalitySupport, 45 USB 3.0 speed only */ 46 0x00, /* bU1DevExitLat, set later. */ 47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 48 }; 49 50 51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 52 struct usb_hub_descriptor *desc, int ports) 53 { 54 u16 temp; 55 56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 57 desc->bHubContrCurrent = 0; 58 59 desc->bNbrPorts = ports; 60 temp = 0; 61 /* Bits 1:0 - support per-port power switching, or power always on */ 62 if (HCC_PPC(xhci->hcc_params)) 63 temp |= HUB_CHAR_INDV_PORT_LPSM; 64 else 65 temp |= HUB_CHAR_NO_LPSM; 66 /* Bit 2 - root hubs are not part of a compound device */ 67 /* Bits 4:3 - individual port over current protection */ 68 temp |= HUB_CHAR_INDV_PORT_OCPM; 69 /* Bits 6:5 - no TTs in root ports */ 70 /* Bit 7 - no port indicators */ 71 desc->wHubCharacteristics = cpu_to_le16(temp); 72 } 73 74 /* Fill in the USB 2.0 roothub descriptor */ 75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 76 struct usb_hub_descriptor *desc) 77 { 78 int ports; 79 u16 temp; 80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 81 u32 portsc; 82 unsigned int i; 83 84 ports = xhci->num_usb2_ports; 85 86 xhci_common_hub_descriptor(xhci, desc, ports); 87 desc->bDescriptorType = USB_DT_HUB; 88 temp = 1 + (ports / 8); 89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 90 91 /* The Device Removable bits are reported on a byte granularity. 92 * If the port doesn't exist within that byte, the bit is set to 0. 93 */ 94 memset(port_removable, 0, sizeof(port_removable)); 95 for (i = 0; i < ports; i++) { 96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]); 97 /* If a device is removable, PORTSC reports a 0, same as in the 98 * hub descriptor DeviceRemovable bits. 99 */ 100 if (portsc & PORT_DEV_REMOVE) 101 /* This math is hairy because bit 0 of DeviceRemovable 102 * is reserved, and bit 1 is for port 1, etc. 103 */ 104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 105 } 106 107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 108 * ports on it. The USB 2.0 specification says that there are two 109 * variable length fields at the end of the hub descriptor: 110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 113 * 0xFF, so we initialize the both arrays (DeviceRemovable and 114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 115 * set of ports that actually exist. 116 */ 117 memset(desc->u.hs.DeviceRemovable, 0xff, 118 sizeof(desc->u.hs.DeviceRemovable)); 119 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 120 sizeof(desc->u.hs.PortPwrCtrlMask)); 121 122 for (i = 0; i < (ports + 1 + 7) / 8; i++) 123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 124 sizeof(__u8)); 125 } 126 127 /* Fill in the USB 3.0 roothub descriptor */ 128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 129 struct usb_hub_descriptor *desc) 130 { 131 int ports; 132 u16 port_removable; 133 u32 portsc; 134 unsigned int i; 135 136 ports = xhci->num_usb3_ports; 137 xhci_common_hub_descriptor(xhci, desc, ports); 138 desc->bDescriptorType = USB_DT_SS_HUB; 139 desc->bDescLength = USB_DT_SS_HUB_SIZE; 140 141 /* header decode latency should be zero for roothubs, 142 * see section 4.23.5.2. 143 */ 144 desc->u.ss.bHubHdrDecLat = 0; 145 desc->u.ss.wHubDelay = 0; 146 147 port_removable = 0; 148 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 149 for (i = 0; i < ports; i++) { 150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]); 151 if (portsc & PORT_DEV_REMOVE) 152 port_removable |= 1 << (i + 1); 153 } 154 memset(&desc->u.ss.DeviceRemovable, 155 (__force __u16) cpu_to_le16(port_removable), 156 sizeof(__u16)); 157 } 158 159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 160 struct usb_hub_descriptor *desc) 161 { 162 163 if (hcd->speed == HCD_USB3) 164 xhci_usb3_hub_descriptor(hcd, xhci, desc); 165 else 166 xhci_usb2_hub_descriptor(hcd, xhci, desc); 167 168 } 169 170 static unsigned int xhci_port_speed(unsigned int port_status) 171 { 172 if (DEV_LOWSPEED(port_status)) 173 return USB_PORT_STAT_LOW_SPEED; 174 if (DEV_HIGHSPEED(port_status)) 175 return USB_PORT_STAT_HIGH_SPEED; 176 /* 177 * FIXME: Yes, we should check for full speed, but the core uses that as 178 * a default in portspeed() in usb/core/hub.c (which is the only place 179 * USB_PORT_STAT_*_SPEED is used). 180 */ 181 return 0; 182 } 183 184 /* 185 * These bits are Read Only (RO) and should be saved and written to the 186 * registers: 0, 3, 10:13, 30 187 * connect status, over-current status, port speed, and device removable. 188 * connect status and port speed are also sticky - meaning they're in 189 * the AUX well and they aren't changed by a hot, warm, or cold reset. 190 */ 191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 192 /* 193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 194 * bits 5:8, 9, 14:15, 25:27 195 * link state, port power, port indicator state, "wake on" enable state 196 */ 197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 198 /* 199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 200 * bit 4 (port reset) 201 */ 202 #define XHCI_PORT_RW1S ((1<<4)) 203 /* 204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 205 * bits 1, 17, 18, 19, 20, 21, 22, 23 206 * port enable/disable, and 207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 208 * over-current, reset, link state, and L1 change 209 */ 210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 211 /* 212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 213 * latched in 214 */ 215 #define XHCI_PORT_RW ((1<<16)) 216 /* 217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 218 * bits 2, 24, 28:31 219 */ 220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 221 222 /* 223 * Given a port state, this function returns a value that would result in the 224 * port being in the same state, if the value was written to the port status 225 * control register. 226 * Save Read Only (RO) bits and save read/write bits where 227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 229 */ 230 u32 xhci_port_state_to_neutral(u32 state) 231 { 232 /* Save read-only status and port state */ 233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 234 } 235 236 /* 237 * find slot id based on port number. 238 * @port: The one-based port number from one of the two split roothubs. 239 */ 240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 241 u16 port) 242 { 243 int slot_id; 244 int i; 245 enum usb_device_speed speed; 246 247 slot_id = 0; 248 for (i = 0; i < MAX_HC_SLOTS; i++) { 249 if (!xhci->devs[i]) 250 continue; 251 speed = xhci->devs[i]->udev->speed; 252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 253 && xhci->devs[i]->fake_port == port) { 254 slot_id = i; 255 break; 256 } 257 } 258 259 return slot_id; 260 } 261 262 /* 263 * Stop device 264 * It issues stop endpoint command for EP 0 to 30. And wait the last command 265 * to complete. 266 * suspend will set to 1, if suspend bit need to set in command. 267 */ 268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 269 { 270 struct xhci_virt_device *virt_dev; 271 struct xhci_command *cmd; 272 unsigned long flags; 273 int timeleft; 274 int ret; 275 int i; 276 277 ret = 0; 278 virt_dev = xhci->devs[slot_id]; 279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 280 if (!cmd) { 281 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 282 return -ENOMEM; 283 } 284 285 spin_lock_irqsave(&xhci->lock, flags); 286 for (i = LAST_EP_INDEX; i > 0; i--) { 287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) 288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); 289 } 290 cmd->command_trb = xhci->cmd_ring->enqueue; 291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); 292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); 293 xhci_ring_cmd_db(xhci); 294 spin_unlock_irqrestore(&xhci->lock, flags); 295 296 /* Wait for last stop endpoint command to finish */ 297 timeleft = wait_for_completion_interruptible_timeout( 298 cmd->completion, 299 USB_CTRL_SET_TIMEOUT); 300 if (timeleft <= 0) { 301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n", 302 timeleft == 0 ? "Timeout" : "Signal"); 303 spin_lock_irqsave(&xhci->lock, flags); 304 /* The timeout might have raced with the event ring handler, so 305 * only delete from the list if the item isn't poisoned. 306 */ 307 if (cmd->cmd_list.next != LIST_POISON1) 308 list_del(&cmd->cmd_list); 309 spin_unlock_irqrestore(&xhci->lock, flags); 310 ret = -ETIME; 311 goto command_cleanup; 312 } 313 314 command_cleanup: 315 xhci_free_command(xhci, cmd); 316 return ret; 317 } 318 319 /* 320 * Ring device, it rings the all doorbells unconditionally. 321 */ 322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 323 { 324 int i; 325 326 for (i = 0; i < LAST_EP_INDEX + 1; i++) 327 if (xhci->devs[slot_id]->eps[i].ring && 328 xhci->devs[slot_id]->eps[i].ring->dequeue) 329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 330 331 return; 332 } 333 334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 u16 wIndex, __le32 __iomem *addr, u32 port_status) 336 { 337 /* Don't allow the USB core to disable SuperSpeed ports. */ 338 if (hcd->speed == HCD_USB3) { 339 xhci_dbg(xhci, "Ignoring request to disable " 340 "SuperSpeed port.\n"); 341 return; 342 } 343 344 /* Write 1 to disable the port */ 345 xhci_writel(xhci, port_status | PORT_PE, addr); 346 port_status = xhci_readl(xhci, addr); 347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 348 wIndex, port_status); 349 } 350 351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 352 u16 wIndex, __le32 __iomem *addr, u32 port_status) 353 { 354 char *port_change_bit; 355 u32 status; 356 357 switch (wValue) { 358 case USB_PORT_FEAT_C_RESET: 359 status = PORT_RC; 360 port_change_bit = "reset"; 361 break; 362 case USB_PORT_FEAT_C_BH_PORT_RESET: 363 status = PORT_WRC; 364 port_change_bit = "warm(BH) reset"; 365 break; 366 case USB_PORT_FEAT_C_CONNECTION: 367 status = PORT_CSC; 368 port_change_bit = "connect"; 369 break; 370 case USB_PORT_FEAT_C_OVER_CURRENT: 371 status = PORT_OCC; 372 port_change_bit = "over-current"; 373 break; 374 case USB_PORT_FEAT_C_ENABLE: 375 status = PORT_PEC; 376 port_change_bit = "enable/disable"; 377 break; 378 case USB_PORT_FEAT_C_SUSPEND: 379 status = PORT_PLC; 380 port_change_bit = "suspend/resume"; 381 break; 382 case USB_PORT_FEAT_C_PORT_LINK_STATE: 383 status = PORT_PLC; 384 port_change_bit = "link state"; 385 break; 386 default: 387 /* Should never happen */ 388 return; 389 } 390 /* Change bits are all write 1 to clear */ 391 xhci_writel(xhci, port_status | status, addr); 392 port_status = xhci_readl(xhci, addr); 393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 394 port_change_bit, wIndex, port_status); 395 } 396 397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 398 { 399 int max_ports; 400 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 401 402 if (hcd->speed == HCD_USB3) { 403 max_ports = xhci->num_usb3_ports; 404 *port_array = xhci->usb3_ports; 405 } else { 406 max_ports = xhci->num_usb2_ports; 407 *port_array = xhci->usb2_ports; 408 } 409 410 return max_ports; 411 } 412 413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 414 int port_id, u32 link_state) 415 { 416 u32 temp; 417 418 temp = xhci_readl(xhci, port_array[port_id]); 419 temp = xhci_port_state_to_neutral(temp); 420 temp &= ~PORT_PLS_MASK; 421 temp |= PORT_LINK_STROBE | link_state; 422 xhci_writel(xhci, temp, port_array[port_id]); 423 } 424 425 /* Test and clear port RWC bit */ 426 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 427 int port_id, u32 port_bit) 428 { 429 u32 temp; 430 431 temp = xhci_readl(xhci, port_array[port_id]); 432 if (temp & port_bit) { 433 temp = xhci_port_state_to_neutral(temp); 434 temp |= port_bit; 435 xhci_writel(xhci, temp, port_array[port_id]); 436 } 437 } 438 439 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 440 u16 wIndex, char *buf, u16 wLength) 441 { 442 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 443 int max_ports; 444 unsigned long flags; 445 u32 temp, status; 446 int retval = 0; 447 __le32 __iomem **port_array; 448 int slot_id; 449 struct xhci_bus_state *bus_state; 450 u16 link_state = 0; 451 452 max_ports = xhci_get_ports(hcd, &port_array); 453 bus_state = &xhci->bus_state[hcd_index(hcd)]; 454 455 spin_lock_irqsave(&xhci->lock, flags); 456 switch (typeReq) { 457 case GetHubStatus: 458 /* No power source, over-current reported per port */ 459 memset(buf, 0, 4); 460 break; 461 case GetHubDescriptor: 462 /* Check to make sure userspace is asking for the USB 3.0 hub 463 * descriptor for the USB 3.0 roothub. If not, we stall the 464 * endpoint, like external hubs do. 465 */ 466 if (hcd->speed == HCD_USB3 && 467 (wLength < USB_DT_SS_HUB_SIZE || 468 wValue != (USB_DT_SS_HUB << 8))) { 469 xhci_dbg(xhci, "Wrong hub descriptor type for " 470 "USB 3.0 roothub.\n"); 471 goto error; 472 } 473 xhci_hub_descriptor(hcd, xhci, 474 (struct usb_hub_descriptor *) buf); 475 break; 476 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 477 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 478 goto error; 479 480 if (hcd->speed != HCD_USB3) 481 goto error; 482 483 memcpy(buf, &usb_bos_descriptor, 484 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 485 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); 486 buf[12] = HCS_U1_LATENCY(temp); 487 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 488 489 spin_unlock_irqrestore(&xhci->lock, flags); 490 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 491 case GetPortStatus: 492 if (!wIndex || wIndex > max_ports) 493 goto error; 494 wIndex--; 495 status = 0; 496 temp = xhci_readl(xhci, port_array[wIndex]); 497 if (temp == 0xffffffff) { 498 retval = -ENODEV; 499 break; 500 } 501 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); 502 503 /* wPortChange bits */ 504 if (temp & PORT_CSC) 505 status |= USB_PORT_STAT_C_CONNECTION << 16; 506 if (temp & PORT_PEC) 507 status |= USB_PORT_STAT_C_ENABLE << 16; 508 if ((temp & PORT_OCC)) 509 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 510 if ((temp & PORT_RC)) 511 status |= USB_PORT_STAT_C_RESET << 16; 512 /* USB3.0 only */ 513 if (hcd->speed == HCD_USB3) { 514 if ((temp & PORT_PLC)) 515 status |= USB_PORT_STAT_C_LINK_STATE << 16; 516 if ((temp & PORT_WRC)) 517 status |= USB_PORT_STAT_C_BH_RESET << 16; 518 } 519 520 if (hcd->speed != HCD_USB3) { 521 if ((temp & PORT_PLS_MASK) == XDEV_U3 522 && (temp & PORT_POWER)) 523 status |= USB_PORT_STAT_SUSPEND; 524 } 525 if ((temp & PORT_PLS_MASK) == XDEV_RESUME && 526 !DEV_SUPERSPEED(temp)) { 527 if ((temp & PORT_RESET) || !(temp & PORT_PE)) 528 goto error; 529 if (time_after_eq(jiffies, 530 bus_state->resume_done[wIndex])) { 531 xhci_dbg(xhci, "Resume USB2 port %d\n", 532 wIndex + 1); 533 bus_state->resume_done[wIndex] = 0; 534 xhci_set_link_state(xhci, port_array, wIndex, 535 XDEV_U0); 536 xhci_dbg(xhci, "set port %d resume\n", 537 wIndex + 1); 538 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 539 wIndex + 1); 540 if (!slot_id) { 541 xhci_dbg(xhci, "slot_id is zero\n"); 542 goto error; 543 } 544 xhci_ring_device(xhci, slot_id); 545 bus_state->port_c_suspend |= 1 << wIndex; 546 bus_state->suspended_ports &= ~(1 << wIndex); 547 } else { 548 /* 549 * The resume has been signaling for less than 550 * 20ms. Report the port status as SUSPEND, 551 * let the usbcore check port status again 552 * and clear resume signaling later. 553 */ 554 status |= USB_PORT_STAT_SUSPEND; 555 } 556 } 557 if ((temp & PORT_PLS_MASK) == XDEV_U0 558 && (temp & PORT_POWER) 559 && (bus_state->suspended_ports & (1 << wIndex))) { 560 bus_state->suspended_ports &= ~(1 << wIndex); 561 if (hcd->speed != HCD_USB3) 562 bus_state->port_c_suspend |= 1 << wIndex; 563 } 564 if (temp & PORT_CONNECT) { 565 status |= USB_PORT_STAT_CONNECTION; 566 status |= xhci_port_speed(temp); 567 } 568 if (temp & PORT_PE) 569 status |= USB_PORT_STAT_ENABLE; 570 if (temp & PORT_OC) 571 status |= USB_PORT_STAT_OVERCURRENT; 572 if (temp & PORT_RESET) 573 status |= USB_PORT_STAT_RESET; 574 if (temp & PORT_POWER) { 575 if (hcd->speed == HCD_USB3) 576 status |= USB_SS_PORT_STAT_POWER; 577 else 578 status |= USB_PORT_STAT_POWER; 579 } 580 /* Port Link State */ 581 if (hcd->speed == HCD_USB3) { 582 /* resume state is a xHCI internal state. 583 * Do not report it to usb core. 584 */ 585 if ((temp & PORT_PLS_MASK) != XDEV_RESUME) 586 status |= (temp & PORT_PLS_MASK); 587 } 588 if (bus_state->port_c_suspend & (1 << wIndex)) 589 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 590 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 591 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 592 break; 593 case SetPortFeature: 594 if (wValue == USB_PORT_FEAT_LINK_STATE) 595 link_state = (wIndex & 0xff00) >> 3; 596 wIndex &= 0xff; 597 if (!wIndex || wIndex > max_ports) 598 goto error; 599 wIndex--; 600 temp = xhci_readl(xhci, port_array[wIndex]); 601 if (temp == 0xffffffff) { 602 retval = -ENODEV; 603 break; 604 } 605 temp = xhci_port_state_to_neutral(temp); 606 /* FIXME: What new port features do we need to support? */ 607 switch (wValue) { 608 case USB_PORT_FEAT_SUSPEND: 609 temp = xhci_readl(xhci, port_array[wIndex]); 610 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 611 /* Resume the port to U0 first */ 612 xhci_set_link_state(xhci, port_array, wIndex, 613 XDEV_U0); 614 spin_unlock_irqrestore(&xhci->lock, flags); 615 msleep(10); 616 spin_lock_irqsave(&xhci->lock, flags); 617 } 618 /* In spec software should not attempt to suspend 619 * a port unless the port reports that it is in the 620 * enabled (PED = ‘1’,PLS < ‘3’) state. 621 */ 622 temp = xhci_readl(xhci, port_array[wIndex]); 623 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 624 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 625 xhci_warn(xhci, "USB core suspending device " 626 "not in U0/U1/U2.\n"); 627 goto error; 628 } 629 630 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 631 wIndex + 1); 632 if (!slot_id) { 633 xhci_warn(xhci, "slot_id is zero\n"); 634 goto error; 635 } 636 /* unlock to execute stop endpoint commands */ 637 spin_unlock_irqrestore(&xhci->lock, flags); 638 xhci_stop_device(xhci, slot_id, 1); 639 spin_lock_irqsave(&xhci->lock, flags); 640 641 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 642 643 spin_unlock_irqrestore(&xhci->lock, flags); 644 msleep(10); /* wait device to enter */ 645 spin_lock_irqsave(&xhci->lock, flags); 646 647 temp = xhci_readl(xhci, port_array[wIndex]); 648 bus_state->suspended_ports |= 1 << wIndex; 649 break; 650 case USB_PORT_FEAT_LINK_STATE: 651 temp = xhci_readl(xhci, port_array[wIndex]); 652 /* Software should not attempt to set 653 * port link state above '5' (Rx.Detect) and the port 654 * must be enabled. 655 */ 656 if ((temp & PORT_PE) == 0 || 657 (link_state > USB_SS_PORT_LS_RX_DETECT)) { 658 xhci_warn(xhci, "Cannot set link state.\n"); 659 goto error; 660 } 661 662 if (link_state == USB_SS_PORT_LS_U3) { 663 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 664 wIndex + 1); 665 if (slot_id) { 666 /* unlock to execute stop endpoint 667 * commands */ 668 spin_unlock_irqrestore(&xhci->lock, 669 flags); 670 xhci_stop_device(xhci, slot_id, 1); 671 spin_lock_irqsave(&xhci->lock, flags); 672 } 673 } 674 675 xhci_set_link_state(xhci, port_array, wIndex, 676 link_state); 677 678 spin_unlock_irqrestore(&xhci->lock, flags); 679 msleep(20); /* wait device to enter */ 680 spin_lock_irqsave(&xhci->lock, flags); 681 682 temp = xhci_readl(xhci, port_array[wIndex]); 683 if (link_state == USB_SS_PORT_LS_U3) 684 bus_state->suspended_ports |= 1 << wIndex; 685 break; 686 case USB_PORT_FEAT_POWER: 687 /* 688 * Turn on ports, even if there isn't per-port switching. 689 * HC will report connect events even before this is set. 690 * However, khubd will ignore the roothub events until 691 * the roothub is registered. 692 */ 693 xhci_writel(xhci, temp | PORT_POWER, 694 port_array[wIndex]); 695 696 temp = xhci_readl(xhci, port_array[wIndex]); 697 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 698 break; 699 case USB_PORT_FEAT_RESET: 700 temp = (temp | PORT_RESET); 701 xhci_writel(xhci, temp, port_array[wIndex]); 702 703 temp = xhci_readl(xhci, port_array[wIndex]); 704 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 705 break; 706 case USB_PORT_FEAT_BH_PORT_RESET: 707 temp |= PORT_WR; 708 xhci_writel(xhci, temp, port_array[wIndex]); 709 710 temp = xhci_readl(xhci, port_array[wIndex]); 711 break; 712 default: 713 goto error; 714 } 715 /* unblock any posted writes */ 716 temp = xhci_readl(xhci, port_array[wIndex]); 717 break; 718 case ClearPortFeature: 719 if (!wIndex || wIndex > max_ports) 720 goto error; 721 wIndex--; 722 temp = xhci_readl(xhci, port_array[wIndex]); 723 if (temp == 0xffffffff) { 724 retval = -ENODEV; 725 break; 726 } 727 /* FIXME: What new port features do we need to support? */ 728 temp = xhci_port_state_to_neutral(temp); 729 switch (wValue) { 730 case USB_PORT_FEAT_SUSPEND: 731 temp = xhci_readl(xhci, port_array[wIndex]); 732 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 733 xhci_dbg(xhci, "PORTSC %04x\n", temp); 734 if (temp & PORT_RESET) 735 goto error; 736 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 737 if ((temp & PORT_PE) == 0) 738 goto error; 739 740 xhci_set_link_state(xhci, port_array, wIndex, 741 XDEV_RESUME); 742 spin_unlock_irqrestore(&xhci->lock, flags); 743 msleep(20); 744 spin_lock_irqsave(&xhci->lock, flags); 745 xhci_set_link_state(xhci, port_array, wIndex, 746 XDEV_U0); 747 } 748 bus_state->port_c_suspend |= 1 << wIndex; 749 750 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 751 wIndex + 1); 752 if (!slot_id) { 753 xhci_dbg(xhci, "slot_id is zero\n"); 754 goto error; 755 } 756 xhci_ring_device(xhci, slot_id); 757 break; 758 case USB_PORT_FEAT_C_SUSPEND: 759 bus_state->port_c_suspend &= ~(1 << wIndex); 760 case USB_PORT_FEAT_C_RESET: 761 case USB_PORT_FEAT_C_BH_PORT_RESET: 762 case USB_PORT_FEAT_C_CONNECTION: 763 case USB_PORT_FEAT_C_OVER_CURRENT: 764 case USB_PORT_FEAT_C_ENABLE: 765 case USB_PORT_FEAT_C_PORT_LINK_STATE: 766 xhci_clear_port_change_bit(xhci, wValue, wIndex, 767 port_array[wIndex], temp); 768 break; 769 case USB_PORT_FEAT_ENABLE: 770 xhci_disable_port(hcd, xhci, wIndex, 771 port_array[wIndex], temp); 772 break; 773 default: 774 goto error; 775 } 776 break; 777 default: 778 error: 779 /* "stall" on error */ 780 retval = -EPIPE; 781 } 782 spin_unlock_irqrestore(&xhci->lock, flags); 783 return retval; 784 } 785 786 /* 787 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 788 * Ports are 0-indexed from the HCD point of view, 789 * and 1-indexed from the USB core pointer of view. 790 * 791 * Note that the status change bits will be cleared as soon as a port status 792 * change event is generated, so we use the saved status from that event. 793 */ 794 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 795 { 796 unsigned long flags; 797 u32 temp, status; 798 u32 mask; 799 int i, retval; 800 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 801 int max_ports; 802 __le32 __iomem **port_array; 803 struct xhci_bus_state *bus_state; 804 805 max_ports = xhci_get_ports(hcd, &port_array); 806 bus_state = &xhci->bus_state[hcd_index(hcd)]; 807 808 /* Initial status is no changes */ 809 retval = (max_ports + 8) / 8; 810 memset(buf, 0, retval); 811 status = 0; 812 813 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC; 814 815 spin_lock_irqsave(&xhci->lock, flags); 816 /* For each port, did anything change? If so, set that bit in buf. */ 817 for (i = 0; i < max_ports; i++) { 818 temp = xhci_readl(xhci, port_array[i]); 819 if (temp == 0xffffffff) { 820 retval = -ENODEV; 821 break; 822 } 823 if ((temp & mask) != 0 || 824 (bus_state->port_c_suspend & 1 << i) || 825 (bus_state->resume_done[i] && time_after_eq( 826 jiffies, bus_state->resume_done[i]))) { 827 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 828 status = 1; 829 } 830 } 831 spin_unlock_irqrestore(&xhci->lock, flags); 832 return status ? retval : 0; 833 } 834 835 #ifdef CONFIG_PM 836 837 int xhci_bus_suspend(struct usb_hcd *hcd) 838 { 839 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 840 int max_ports, port_index; 841 __le32 __iomem **port_array; 842 struct xhci_bus_state *bus_state; 843 unsigned long flags; 844 845 max_ports = xhci_get_ports(hcd, &port_array); 846 bus_state = &xhci->bus_state[hcd_index(hcd)]; 847 848 spin_lock_irqsave(&xhci->lock, flags); 849 850 if (hcd->self.root_hub->do_remote_wakeup) { 851 port_index = max_ports; 852 while (port_index--) { 853 if (bus_state->resume_done[port_index] != 0) { 854 spin_unlock_irqrestore(&xhci->lock, flags); 855 xhci_dbg(xhci, "suspend failed because " 856 "port %d is resuming\n", 857 port_index + 1); 858 return -EBUSY; 859 } 860 } 861 } 862 863 port_index = max_ports; 864 bus_state->bus_suspended = 0; 865 while (port_index--) { 866 /* suspend the port if the port is not suspended */ 867 u32 t1, t2; 868 int slot_id; 869 870 t1 = xhci_readl(xhci, port_array[port_index]); 871 t2 = xhci_port_state_to_neutral(t1); 872 873 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 874 xhci_dbg(xhci, "port %d not suspended\n", port_index); 875 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 876 port_index + 1); 877 if (slot_id) { 878 spin_unlock_irqrestore(&xhci->lock, flags); 879 xhci_stop_device(xhci, slot_id, 1); 880 spin_lock_irqsave(&xhci->lock, flags); 881 } 882 t2 &= ~PORT_PLS_MASK; 883 t2 |= PORT_LINK_STROBE | XDEV_U3; 884 set_bit(port_index, &bus_state->bus_suspended); 885 } 886 if (hcd->self.root_hub->do_remote_wakeup) { 887 if (t1 & PORT_CONNECT) { 888 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 889 t2 &= ~PORT_WKCONN_E; 890 } else { 891 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 892 t2 &= ~PORT_WKDISC_E; 893 } 894 } else 895 t2 &= ~PORT_WAKE_BITS; 896 897 t1 = xhci_port_state_to_neutral(t1); 898 if (t1 != t2) 899 xhci_writel(xhci, t2, port_array[port_index]); 900 901 if (hcd->speed != HCD_USB3) { 902 /* enable remote wake up for USB 2.0 */ 903 __le32 __iomem *addr; 904 u32 tmp; 905 906 /* Add one to the port status register address to get 907 * the port power control register address. 908 */ 909 addr = port_array[port_index] + 1; 910 tmp = xhci_readl(xhci, addr); 911 tmp |= PORT_RWE; 912 xhci_writel(xhci, tmp, addr); 913 } 914 } 915 hcd->state = HC_STATE_SUSPENDED; 916 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 917 spin_unlock_irqrestore(&xhci->lock, flags); 918 return 0; 919 } 920 921 int xhci_bus_resume(struct usb_hcd *hcd) 922 { 923 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 924 int max_ports, port_index; 925 __le32 __iomem **port_array; 926 struct xhci_bus_state *bus_state; 927 u32 temp; 928 unsigned long flags; 929 930 max_ports = xhci_get_ports(hcd, &port_array); 931 bus_state = &xhci->bus_state[hcd_index(hcd)]; 932 933 if (time_before(jiffies, bus_state->next_statechange)) 934 msleep(5); 935 936 spin_lock_irqsave(&xhci->lock, flags); 937 if (!HCD_HW_ACCESSIBLE(hcd)) { 938 spin_unlock_irqrestore(&xhci->lock, flags); 939 return -ESHUTDOWN; 940 } 941 942 /* delay the irqs */ 943 temp = xhci_readl(xhci, &xhci->op_regs->command); 944 temp &= ~CMD_EIE; 945 xhci_writel(xhci, temp, &xhci->op_regs->command); 946 947 port_index = max_ports; 948 while (port_index--) { 949 /* Check whether need resume ports. If needed 950 resume port and disable remote wakeup */ 951 u32 temp; 952 int slot_id; 953 954 temp = xhci_readl(xhci, port_array[port_index]); 955 if (DEV_SUPERSPEED(temp)) 956 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 957 else 958 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 959 if (test_bit(port_index, &bus_state->bus_suspended) && 960 (temp & PORT_PLS_MASK)) { 961 if (DEV_SUPERSPEED(temp)) { 962 xhci_set_link_state(xhci, port_array, 963 port_index, XDEV_U0); 964 } else { 965 xhci_set_link_state(xhci, port_array, 966 port_index, XDEV_RESUME); 967 968 spin_unlock_irqrestore(&xhci->lock, flags); 969 msleep(20); 970 spin_lock_irqsave(&xhci->lock, flags); 971 972 xhci_set_link_state(xhci, port_array, 973 port_index, XDEV_U0); 974 } 975 /* wait for the port to enter U0 and report port link 976 * state change. 977 */ 978 spin_unlock_irqrestore(&xhci->lock, flags); 979 msleep(20); 980 spin_lock_irqsave(&xhci->lock, flags); 981 982 /* Clear PLC */ 983 xhci_test_and_clear_bit(xhci, port_array, port_index, 984 PORT_PLC); 985 986 slot_id = xhci_find_slot_id_by_port(hcd, 987 xhci, port_index + 1); 988 if (slot_id) 989 xhci_ring_device(xhci, slot_id); 990 } else 991 xhci_writel(xhci, temp, port_array[port_index]); 992 993 if (hcd->speed != HCD_USB3) { 994 /* disable remote wake up for USB 2.0 */ 995 __le32 __iomem *addr; 996 u32 tmp; 997 998 /* Add one to the port status register address to get 999 * the port power control register address. 1000 */ 1001 addr = port_array[port_index] + 1; 1002 tmp = xhci_readl(xhci, addr); 1003 tmp &= ~PORT_RWE; 1004 xhci_writel(xhci, tmp, addr); 1005 } 1006 } 1007 1008 (void) xhci_readl(xhci, &xhci->op_regs->command); 1009 1010 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1011 /* re-enable irqs */ 1012 temp = xhci_readl(xhci, &xhci->op_regs->command); 1013 temp |= CMD_EIE; 1014 xhci_writel(xhci, temp, &xhci->op_regs->command); 1015 temp = xhci_readl(xhci, &xhci->op_regs->command); 1016 1017 spin_unlock_irqrestore(&xhci->lock, flags); 1018 return 0; 1019 } 1020 1021 #endif /* CONFIG_PM */ 1022