1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 12 #include <linux/slab.h> 13 #include <linux/unaligned.h> 14 #include <linux/bitfield.h> 15 #include <linux/pci.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 20 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 21 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 22 PORT_RC | PORT_PLC | PORT_PE) 23 24 /* Default sublink speed attribute of each lane */ 25 static u32 ssp_cap_default_ssa[] = { 26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 34 }; 35 36 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, 37 u16 wLength) 38 { 39 struct usb_bos_descriptor *bos; 40 struct usb_ss_cap_descriptor *ss_cap; 41 struct usb_ssp_cap_descriptor *ssp_cap; 42 struct xhci_port_cap *port_cap = NULL; 43 u16 bcdUSB; 44 u32 reg; 45 u32 min_rate = 0; 46 u8 min_ssid; 47 u8 ssac; 48 u8 ssic; 49 int offset; 50 int i; 51 52 /* BOS descriptor */ 53 bos = (struct usb_bos_descriptor *)buf; 54 bos->bLength = USB_DT_BOS_SIZE; 55 bos->bDescriptorType = USB_DT_BOS; 56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 57 USB_DT_USB_SS_CAP_SIZE); 58 bos->bNumDeviceCaps = 1; 59 60 /* Create the descriptor for port with the highest revision */ 61 for (i = 0; i < xhci->num_port_caps; i++) { 62 u8 major = xhci->port_caps[i].maj_rev; 63 u8 minor = xhci->port_caps[i].min_rev; 64 u16 rev = (major << 8) | minor; 65 66 if (i == 0 || bcdUSB < rev) { 67 bcdUSB = rev; 68 port_cap = &xhci->port_caps[i]; 69 } 70 } 71 72 if (bcdUSB >= 0x0310) { 73 if (port_cap->psi_count) { 74 u8 num_sym_ssa = 0; 75 76 for (i = 0; i < port_cap->psi_count; i++) { 77 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM) 78 num_sym_ssa++; 79 } 80 81 ssac = port_cap->psi_count + num_sym_ssa - 1; 82 ssic = port_cap->psi_uid_count - 1; 83 } else { 84 if (bcdUSB >= 0x0320) 85 ssac = 7; 86 else 87 ssac = 3; 88 89 ssic = (ssac + 1) / 2 - 1; 90 } 91 92 bos->bNumDeviceCaps++; 93 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 94 USB_DT_USB_SS_CAP_SIZE + 95 USB_DT_USB_SSP_CAP_SIZE(ssac)); 96 } 97 98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 99 return wLength; 100 101 /* SuperSpeed USB Device Capability */ 102 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE]; 103 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; 104 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 105 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; 106 ss_cap->bmAttributes = 0; /* set later */ 107 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION); 108 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 109 ss_cap->bU1devExitLat = 0; /* set later */ 110 ss_cap->bU2DevExitLat = 0; /* set later */ 111 112 reg = readl(&xhci->cap_regs->hcc_params); 113 if (reg & HCC_LTC) 114 ss_cap->bmAttributes |= USB_LTM_SUPPORT; 115 116 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 117 reg = readl(&xhci->cap_regs->hcs_params3); 118 ss_cap->bU1devExitLat = FIELD_GET(HCS_U1_LATENCY, reg); 119 ss_cap->bU2DevExitLat = cpu_to_le16(FIELD_GET(HCS_U2_LATENCY, reg)); 120 } 121 122 if (wLength < le16_to_cpu(bos->wTotalLength)) 123 return wLength; 124 125 if (bcdUSB < 0x0310) 126 return le16_to_cpu(bos->wTotalLength); 127 128 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE + 129 USB_DT_USB_SS_CAP_SIZE]; 130 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac); 131 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 132 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE; 133 ssp_cap->bReserved = 0; 134 ssp_cap->wReserved = 0; 135 ssp_cap->bmAttributes = 136 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) | 137 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic)); 138 139 if (!port_cap->psi_count) { 140 for (i = 0; i < ssac + 1; i++) 141 ssp_cap->bmSublinkSpeedAttr[i] = 142 cpu_to_le32(ssp_cap_default_ssa[i]); 143 144 min_ssid = 4; 145 goto out; 146 } 147 148 offset = 0; 149 for (i = 0; i < port_cap->psi_count; i++) { 150 u32 psi; 151 u32 attr; 152 u8 ssid; 153 u8 lp; 154 u8 lse; 155 u8 psie; 156 u16 lane_mantissa; 157 u16 psim; 158 u16 plt; 159 160 psi = port_cap->psi[i]; 161 ssid = XHCI_EXT_PORT_PSIV(psi); 162 lp = XHCI_EXT_PORT_LP(psi); 163 psie = XHCI_EXT_PORT_PSIE(psi); 164 psim = XHCI_EXT_PORT_PSIM(psi); 165 plt = psi & PLT_MASK; 166 167 lse = psie; 168 lane_mantissa = psim; 169 170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ 171 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++) 172 psim /= 1000; 173 174 if (!min_rate || psim < min_rate) { 175 min_ssid = ssid; 176 min_rate = psim; 177 } 178 179 /* Some host controllers don't set the link protocol for SSP */ 180 if (psim >= 10) 181 lp = USB_SSP_SUBLINK_SPEED_LP_SSP; 182 183 /* 184 * PSIM and PSIE represent the total speed of PSI. The BOS 185 * descriptor SSP sublink speed attribute lane mantissa 186 * describes the lane speed. E.g. PSIM and PSIE for gen2x2 187 * is 20Gbps, but the BOS descriptor lane speed mantissa is 188 * 10Gbps. Check and modify the mantissa value to match the 189 * lane speed. 190 */ 191 if (bcdUSB == 0x0320 && plt == PLT_SYM) { 192 /* 193 * The PSI dword for gen1x2 and gen2x1 share the same 194 * values. But the lane speed for gen1x2 is 5Gbps while 195 * gen2x1 is 10Gbps. If the previous PSI dword SSID is 196 * 5 and the PSIE and PSIM match with SSID 6, let's 197 * assume that the controller follows the default speed 198 * id with SSID 6 for gen1x2. 199 */ 200 if (ssid == 6 && psie == 3 && psim == 10 && i) { 201 u32 prev = port_cap->psi[i - 1]; 202 203 if ((prev & PLT_MASK) == PLT_SYM && 204 XHCI_EXT_PORT_PSIV(prev) == 5 && 205 XHCI_EXT_PORT_PSIE(prev) == 3 && 206 XHCI_EXT_PORT_PSIM(prev) == 10) { 207 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 208 lane_mantissa = 5; 209 } 210 } 211 212 if (psie == 3 && psim > 10) { 213 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 214 lane_mantissa = 10; 215 } 216 } 217 218 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) | 219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) | 220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) | 221 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa)); 222 223 switch (plt) { 224 case PLT_SYM: 225 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 226 USB_SSP_SUBLINK_SPEED_ST_SYM_RX); 227 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 228 229 FIELD_MODIFY(USB_SSP_SUBLINK_SPEED_ST, &attr, 230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX); 231 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 232 break; 233 case PLT_ASYM_RX: 234 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX); 236 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 237 break; 238 case PLT_ASYM_TX: 239 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX); 241 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 242 break; 243 } 244 } 245 out: 246 ssp_cap->wFunctionalitySupport = 247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 248 min_ssid) | 249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) | 250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1)); 251 252 return le16_to_cpu(bos->wTotalLength); 253 } 254 255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 256 struct usb_hub_descriptor *desc, int ports) 257 { 258 u16 temp; 259 260 desc->bHubContrCurrent = 0; 261 262 desc->bNbrPorts = ports; 263 temp = 0; 264 /* Bits 1:0 - support per-port power switching, or power always on */ 265 if (xhci->hcc_params & HCC_PPC) 266 temp |= HUB_CHAR_INDV_PORT_LPSM; 267 else 268 temp |= HUB_CHAR_NO_LPSM; 269 /* Bit 2 - root hubs are not part of a compound device */ 270 /* Bits 4:3 - individual port over current protection */ 271 temp |= HUB_CHAR_INDV_PORT_OCPM; 272 /* Bits 6:5 - no TTs in root ports */ 273 /* Bit 7 - no port indicators */ 274 desc->wHubCharacteristics = cpu_to_le16(temp); 275 } 276 277 /* Fill in the USB 2.0 roothub descriptor */ 278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 279 struct usb_hub_descriptor *desc) 280 { 281 int ports; 282 u16 temp; 283 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 284 u32 portsc; 285 unsigned int i; 286 struct xhci_hub *rhub; 287 288 rhub = &xhci->usb2_rhub; 289 ports = rhub->num_ports; 290 xhci_common_hub_descriptor(xhci, desc, ports); 291 desc->bDescriptorType = USB_DT_HUB; 292 temp = 1 + (ports / 8); 293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 294 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */ 295 296 /* The Device Removable bits are reported on a byte granularity. 297 * If the port doesn't exist within that byte, the bit is set to 0. 298 */ 299 memset(port_removable, 0, sizeof(port_removable)); 300 for (i = 0; i < ports; i++) { 301 portsc = xhci_portsc_readl(rhub->ports[i]); 302 /* If a device is removable, PORTSC reports a 0, same as in the 303 * hub descriptor DeviceRemovable bits. 304 */ 305 if (portsc & PORT_DEV_REMOVE) 306 /* This math is hairy because bit 0 of DeviceRemovable 307 * is reserved, and bit 1 is for port 1, etc. 308 */ 309 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 310 } 311 312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 313 * ports on it. The USB 2.0 specification says that there are two 314 * variable length fields at the end of the hub descriptor: 315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 318 * 0xFF, so we initialize the both arrays (DeviceRemovable and 319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 320 * set of ports that actually exist. 321 */ 322 memset(desc->u.hs.DeviceRemovable, 0xff, 323 sizeof(desc->u.hs.DeviceRemovable)); 324 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 325 sizeof(desc->u.hs.PortPwrCtrlMask)); 326 327 for (i = 0; i < (ports + 1 + 7) / 8; i++) 328 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 329 sizeof(__u8)); 330 } 331 332 /* Fill in the USB 3.0 roothub descriptor */ 333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 334 struct usb_hub_descriptor *desc) 335 { 336 int ports; 337 u16 port_removable; 338 u32 portsc; 339 unsigned int i; 340 struct xhci_hub *rhub; 341 342 rhub = &xhci->usb3_rhub; 343 ports = rhub->num_ports; 344 xhci_common_hub_descriptor(xhci, desc, ports); 345 desc->bDescriptorType = USB_DT_SS_HUB; 346 desc->bDescLength = USB_DT_SS_HUB_SIZE; 347 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */ 348 349 /* header decode latency should be zero for roothubs, 350 * see section 4.23.5.2. 351 */ 352 desc->u.ss.bHubHdrDecLat = 0; 353 desc->u.ss.wHubDelay = 0; 354 355 port_removable = 0; 356 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 357 for (i = 0; i < ports; i++) { 358 portsc = xhci_portsc_readl(rhub->ports[i]); 359 if (portsc & PORT_DEV_REMOVE) 360 port_removable |= 1 << (i + 1); 361 } 362 363 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 364 } 365 366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 367 struct usb_hub_descriptor *desc) 368 { 369 370 if (hcd->speed >= HCD_USB3) 371 xhci_usb3_hub_descriptor(hcd, xhci, desc); 372 else 373 xhci_usb2_hub_descriptor(hcd, xhci, desc); 374 375 } 376 377 static unsigned int xhci_port_speed(int portsc) 378 { 379 if (DEV_LOWSPEED(portsc)) 380 return USB_PORT_STAT_LOW_SPEED; 381 if (DEV_HIGHSPEED(portsc)) 382 return USB_PORT_STAT_HIGH_SPEED; 383 /* 384 * FIXME: Yes, we should check for full speed, but the core uses that as 385 * a default in portspeed() in usb/core/hub.c (which is the only place 386 * USB_PORT_STAT_*_SPEED is used). 387 */ 388 return 0; 389 } 390 391 /* 392 * These bits are Read Only (RO) and should be saved and written to the 393 * registers: 0, 3, 10:13, 30 394 * connect status, over-current status, port speed, and device removable. 395 * connect status and port speed are also sticky - meaning they're in 396 * the AUX well and they aren't changed by a hot, warm, or cold reset. 397 */ 398 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 399 /* 400 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 401 * bits 5:8, 9, 14:15, 25:27 402 * link state, port power, port indicator state, "wake on" enable state 403 */ 404 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 405 /* 406 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 407 * bit 4 (port reset) 408 */ 409 #define XHCI_PORT_RW1S ((1<<4)) 410 /* 411 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 412 * bits 1, 17, 18, 19, 20, 21, 22, 23 413 * port enable/disable, and 414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 415 * over-current, reset, link state, and L1 change 416 */ 417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 418 /* 419 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 420 * latched in 421 */ 422 #define XHCI_PORT_RW ((1<<16)) 423 /* 424 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 425 * bits 2, 24, 28:31 426 */ 427 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 428 429 /** 430 * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable 431 * @portsc: u32 port value read from portsc register to be cleanup up 432 * 433 * Given a portsc, this function returns a value that would result in the 434 * port being in the same state, if the value was written to the port status 435 * control register. 436 * Save Read Only (RO) bits and save read/write bits where 437 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 438 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 439 * 440 * Return: u32 value that can be written back to portsc register without 441 * changing port state. 442 */ 443 444 u32 xhci_port_state_to_neutral(u32 portsc) 445 { 446 /* Save read-only status and port state */ 447 return (portsc & XHCI_PORT_RO) | (portsc & XHCI_PORT_RWS); 448 } 449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral); 450 451 /* 452 * Stop device 453 * It issues stop endpoint command for EP 0 to 30. And wait the last command 454 * to complete. 455 * suspend will set to 1, if suspend bit need to set in command. 456 */ 457 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 458 { 459 struct xhci_virt_device *virt_dev; 460 struct xhci_command *cmd; 461 unsigned long flags; 462 int ret; 463 int i; 464 465 ret = 0; 466 virt_dev = xhci->devs[slot_id]; 467 if (!virt_dev) 468 return -ENODEV; 469 470 trace_xhci_stop_device(virt_dev); 471 472 cmd = xhci_alloc_command(xhci, true, GFP_NOIO); 473 if (!cmd) 474 return -ENOMEM; 475 476 spin_lock_irqsave(&xhci->lock, flags); 477 for (i = LAST_EP_INDEX; i > 0; i--) { 478 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 479 struct xhci_ep_ctx *ep_ctx; 480 struct xhci_command *command; 481 482 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 483 484 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 485 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 486 continue; 487 488 command = xhci_alloc_command(xhci, false, GFP_NOWAIT); 489 if (!command) { 490 spin_unlock_irqrestore(&xhci->lock, flags); 491 ret = -ENOMEM; 492 goto cmd_cleanup; 493 } 494 495 ret = xhci_queue_stop_endpoint(xhci, command, slot_id, 496 i, suspend); 497 if (ret) { 498 spin_unlock_irqrestore(&xhci->lock, flags); 499 xhci_free_command(xhci, command); 500 goto cmd_cleanup; 501 } 502 } 503 } 504 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 505 if (ret) { 506 spin_unlock_irqrestore(&xhci->lock, flags); 507 goto cmd_cleanup; 508 } 509 510 xhci_ring_cmd_db(xhci); 511 spin_unlock_irqrestore(&xhci->lock, flags); 512 513 /* Wait for last stop endpoint command to finish */ 514 wait_for_completion(cmd->completion); 515 516 if (cmd->status == COMP_COMMAND_ABORTED || 517 cmd->status == COMP_COMMAND_RING_STOPPED) { 518 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 519 ret = -ETIME; 520 } 521 522 cmd_cleanup: 523 xhci_free_command(xhci, cmd); 524 return ret; 525 } 526 527 /* 528 * Ring device, it rings the all doorbells unconditionally. 529 */ 530 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 531 { 532 int i, s; 533 struct xhci_virt_ep *ep; 534 535 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 536 ep = &xhci->devs[slot_id]->eps[i]; 537 538 if (ep->ep_state & EP_HAS_STREAMS) { 539 for (s = 1; s < ep->stream_info->num_streams; s++) 540 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 541 } else if (ep->ring && ep->ring->dequeue) { 542 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 543 } 544 } 545 546 return; 547 } 548 549 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port) 550 { 551 struct usb_hcd *hcd; 552 u32 portsc; 553 554 hcd = port->rhub->hcd; 555 556 /* Don't allow the USB core to disable SuperSpeed ports. */ 557 if (hcd->speed >= HCD_USB3) { 558 xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n"); 559 return; 560 } 561 562 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 563 xhci_dbg(xhci, 564 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 565 return; 566 } 567 568 portsc = xhci_portsc_readl(port); 569 portsc = xhci_port_state_to_neutral(portsc); 570 571 /* Write 1 to disable the port */ 572 xhci_portsc_writel(port, portsc | PORT_PE); 573 574 portsc = xhci_portsc_readl(port); 575 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", 576 hcd->self.busnum, port->hcd_portnum + 1, portsc); 577 } 578 579 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, struct xhci_port *port, 580 u32 portsc) 581 { 582 char *port_change_bit; 583 u32 status; 584 585 switch (wValue) { 586 case USB_PORT_FEAT_C_RESET: 587 status = PORT_RC; 588 port_change_bit = "reset"; 589 break; 590 case USB_PORT_FEAT_C_BH_PORT_RESET: 591 status = PORT_WRC; 592 port_change_bit = "warm(BH) reset"; 593 break; 594 case USB_PORT_FEAT_C_CONNECTION: 595 status = PORT_CSC; 596 port_change_bit = "connect"; 597 break; 598 case USB_PORT_FEAT_C_OVER_CURRENT: 599 status = PORT_OCC; 600 port_change_bit = "over-current"; 601 break; 602 case USB_PORT_FEAT_C_ENABLE: 603 status = PORT_PEC; 604 port_change_bit = "enable/disable"; 605 break; 606 case USB_PORT_FEAT_C_SUSPEND: 607 status = PORT_PLC; 608 port_change_bit = "suspend/resume"; 609 break; 610 case USB_PORT_FEAT_C_PORT_LINK_STATE: 611 status = PORT_PLC; 612 port_change_bit = "link state"; 613 break; 614 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 615 status = PORT_CEC; 616 port_change_bit = "config error"; 617 break; 618 default: 619 /* Should never happen */ 620 return; 621 } 622 /* Change bits are all write 1 to clear */ 623 xhci_portsc_writel(port, portsc | status); 624 portsc = xhci_portsc_readl(port); 625 626 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", 627 port->hcd_portnum + 1, port_change_bit, portsc); 628 } 629 630 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) 631 { 632 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 633 634 if (hcd->speed >= HCD_USB3) 635 return &xhci->usb3_rhub; 636 return &xhci->usb2_rhub; 637 } 638 639 /* 640 * xhci_set_port_power() must be called with xhci->lock held. 641 * It will release and re-acquire the lock while calling ACPI 642 * method. 643 */ 644 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port, 645 bool on, unsigned long *flags) 646 __must_hold(&xhci->lock) 647 { 648 struct usb_hcd *hcd; 649 u32 temp; 650 651 hcd = port->rhub->hcd; 652 temp = xhci_portsc_readl(port); 653 654 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", 655 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); 656 657 temp = xhci_port_state_to_neutral(temp); 658 659 if (on) { 660 /* Power on */ 661 xhci_portsc_writel(port, temp | PORT_POWER); 662 xhci_portsc_readl(port); 663 } else { 664 /* Power off */ 665 xhci_portsc_writel(port, temp & ~PORT_POWER); 666 } 667 668 spin_unlock_irqrestore(&xhci->lock, *flags); 669 temp = usb_acpi_power_manageable(hcd->self.root_hub, 670 port->hcd_portnum); 671 if (temp) 672 usb_acpi_set_power_state(hcd->self.root_hub, 673 port->hcd_portnum, on); 674 spin_lock_irqsave(&xhci->lock, *flags); 675 } 676 677 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, u16 test_mode, int portnum) 678 { 679 u32 temp; 680 struct xhci_port *port; 681 682 /* xhci only supports test mode for usb2 ports */ 683 port = xhci->usb2_rhub.ports[portnum]; 684 temp = readl(&port->port_reg->portpmsc); 685 temp |= test_mode << PORT_TEST_MODE_SHIFT; 686 writel(temp, &port->port_reg->portpmsc); 687 xhci->test_mode = test_mode; 688 if (test_mode == USB_TEST_FORCE_ENABLE) 689 xhci_start(xhci); 690 } 691 692 static int xhci_enter_test_mode(struct xhci_hcd *xhci, u16 test_mode, int portnum, 693 unsigned long *flags) 694 __must_hold(&xhci->lock) 695 { 696 int i, retval; 697 698 /* Disable all Device Slots */ 699 xhci_dbg(xhci, "Disable all slots\n"); 700 spin_unlock_irqrestore(&xhci->lock, *flags); 701 for (i = 1; i <= xhci->max_slots; i++) { 702 if (!xhci->devs[i]) 703 continue; 704 705 retval = xhci_disable_and_free_slot(xhci, i); 706 if (retval) 707 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 708 i, retval); 709 } 710 spin_lock_irqsave(&xhci->lock, *flags); 711 /* Put all ports to the Disable state by clear PP */ 712 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 713 /* Power off USB3 ports*/ 714 for (i = 0; i < xhci->usb3_rhub.num_ports; i++) 715 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags); 716 /* Power off USB2 ports*/ 717 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) 718 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags); 719 /* Stop the controller */ 720 xhci_dbg(xhci, "Stop controller\n"); 721 retval = xhci_halt(xhci); 722 if (retval) 723 return retval; 724 /* Disable runtime PM for test mode */ 725 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 726 /* Set PORTPMSC.PTC field to enter selected test mode */ 727 xhci_dbg(xhci, "Enter Test Mode: %u, Port_id=%d\n", test_mode, portnum + 1); 728 xhci_port_set_test_mode(xhci, test_mode, portnum); 729 return retval; 730 } 731 732 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 733 { 734 int retval; 735 736 if (!xhci->test_mode) { 737 xhci_err(xhci, "Not in test mode, do nothing.\n"); 738 return 0; 739 } 740 if (xhci->test_mode == USB_TEST_FORCE_ENABLE && 741 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 742 retval = xhci_halt(xhci); 743 if (retval) 744 return retval; 745 } 746 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 747 xhci->test_mode = 0; 748 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC); 749 } 750 751 /** 752 * xhci_port_is_tunneled() - Check if USB3 connection is tunneled over USB4 753 * @xhci: xhci host controller 754 * @port: USB3 port to be checked. 755 * 756 * Some hosts can detect if a USB3 connection is native USB3 or tunneled over 757 * USB4. Intel hosts expose this via vendor specific extended capability 206 758 * eSS PORT registers TUNEN (tunnel enabled) bit. 759 * 760 * A USB3 device must be connected to the port to detect the tunnel. 761 * 762 * Return: link tunnel mode enum, USB_LINK_UNKNOWN if host is incapable of 763 * detecting USB3 over USB4 tunnels. USB_LINK_NATIVE or USB_LINK_TUNNELED 764 * otherwise. 765 */ 766 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 767 struct xhci_port *port) 768 { 769 struct usb_hcd *hcd; 770 void __iomem *base; 771 u32 offset; 772 773 /* Don't try and probe this capability for non-Intel hosts */ 774 hcd = xhci_to_hcd(xhci); 775 if (!dev_is_pci(hcd->self.controller) || 776 to_pci_dev(hcd->self.controller)->vendor != PCI_VENDOR_ID_INTEL) 777 return USB_LINK_UNKNOWN; 778 779 base = &xhci->cap_regs->hc_capbase; 780 offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW); 781 782 if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) { 783 offset = XHCI_INTEL_SPR_ESS_PORT_OFFSET + port->hcd_portnum * 0x20; 784 785 if (readl(base + offset) & XHCI_INTEL_SPR_TUNEN) 786 return USB_LINK_TUNNELED; 787 else 788 return USB_LINK_NATIVE; 789 } 790 791 return USB_LINK_UNKNOWN; 792 } 793 794 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 795 u32 link_state) 796 { 797 u32 temp; 798 u32 portsc; 799 800 portsc = xhci_portsc_readl(port); 801 temp = xhci_port_state_to_neutral(portsc); 802 temp &= ~PORT_PLS_MASK; 803 temp |= PORT_LINK_STROBE | link_state; 804 xhci_portsc_writel(port, temp); 805 806 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", 807 port->rhub->hcd->self.busnum, port->hcd_portnum + 1, 808 portsc, temp); 809 } 810 811 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 812 struct xhci_port *port, u16 wake_mask) 813 { 814 u32 temp; 815 816 temp = xhci_portsc_readl(port); 817 temp = xhci_port_state_to_neutral(temp); 818 819 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 820 temp |= PORT_WKCONN_E; 821 else 822 temp &= ~PORT_WKCONN_E; 823 824 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 825 temp |= PORT_WKDISC_E; 826 else 827 temp &= ~PORT_WKDISC_E; 828 829 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 830 temp |= PORT_WKOC_E; 831 else 832 temp &= ~PORT_WKOC_E; 833 834 xhci_portsc_writel(port, temp); 835 } 836 837 /* Test and clear port RWC bit */ 838 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 839 u32 port_bit) 840 { 841 u32 temp; 842 843 temp = xhci_portsc_readl(port); 844 if (temp & port_bit) { 845 temp = xhci_port_state_to_neutral(temp); 846 temp |= port_bit; 847 xhci_portsc_writel(port, temp); 848 } 849 } 850 851 /* Updates Link Status for super Speed port */ 852 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, u32 *status, u32 portsc) 853 { 854 u32 pls = portsc & PORT_PLS_MASK; 855 856 /* 857 * CAS indicates that a warm reset is required, it may be set in any 858 * link state and is only present on roothubs. 859 */ 860 if (portsc & PORT_CAS) { 861 /* 862 * If not already in Compliance or Inactive state, 863 * report Compliance Mode so the hub logic triggers a warm reset. 864 */ 865 if (pls != XDEV_COMP_MODE && pls != XDEV_INACTIVE) 866 pls = USB_SS_PORT_LS_COMP_MOD; 867 868 /* Signal a connection change to force a reset */ 869 *status |= USB_PORT_STAT_CONNECTION; 870 } else if (pls == XDEV_RESUME) { 871 /* 872 * Resume is an internal xHCI-only state and must not be exposed 873 * to usbcore. Report it as U3 so transfers are blocked. 874 */ 875 pls = USB_SS_PORT_LS_U3; 876 } else if (pls == XDEV_COMP_MODE) { 877 /* 878 * Some hardware may enter Compliance Mode without CAS. 879 * Fake a connection event so usbcore notices and resets the port. 880 */ 881 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 882 *status |= USB_PORT_STAT_CONNECTION; 883 } 884 885 /* update status field */ 886 *status |= pls; 887 } 888 889 /* 890 * Function for Compliance Mode Quirk. 891 * 892 * This Function verifies if all xhc USB3 ports have entered U0, if so, 893 * the compliance mode timer is deleted. A port won't enter 894 * compliance mode if it has previously entered U0. 895 */ 896 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 portsc, int portnum) 897 { 898 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); 899 bool port_in_u0 = ((portsc & PORT_PLS_MASK) == XDEV_U0); 900 901 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 902 return; 903 904 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 905 xhci->port_status_u0 |= 1 << portnum; 906 if (xhci->port_status_u0 == all_ports_seen_u0) { 907 timer_delete_sync(&xhci->comp_mode_recovery_timer); 908 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 909 "All USB3 ports have entered U0 already!"); 910 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 911 "Compliance Mode Recovery Timer Deleted."); 912 } 913 } 914 } 915 916 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, 917 u32 portsc, 918 unsigned long *flags) 919 { 920 struct xhci_bus_state *bus_state; 921 struct xhci_hcd *xhci; 922 struct usb_hcd *hcd; 923 int portnum; 924 925 hcd = port->rhub->hcd; 926 bus_state = &port->rhub->bus_state; 927 xhci = hcd_to_xhci(hcd); 928 portnum = port->hcd_portnum; 929 930 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { 931 return -EINVAL; 932 } 933 /* did port event handler already start resume timing? */ 934 if (!port->resume_timestamp) { 935 /* If not, maybe we are in a host initiated resume? */ 936 if (test_bit(portnum, &bus_state->resuming_ports)) { 937 /* Host initiated resume doesn't time the resume 938 * signalling using resume_done[]. 939 * It manually sets RESUME state, sleeps 20ms 940 * and sets U0 state. This should probably be 941 * changed, but not right now. 942 */ 943 } else { 944 /* port resume was discovered now and here, 945 * start resume timing 946 */ 947 unsigned long timeout = jiffies + 948 msecs_to_jiffies(USB_RESUME_TIMEOUT); 949 950 set_bit(portnum, &bus_state->resuming_ports); 951 port->resume_timestamp = timeout; 952 mod_timer(&hcd->rh_timer, timeout); 953 usb_hcd_start_port_resume(&hcd->self, portnum); 954 } 955 /* Has resume been signalled for USB_RESUME_TIME yet? */ 956 } else if (time_after_eq(jiffies, port->resume_timestamp)) { 957 int time_left; 958 959 xhci_dbg(xhci, "resume USB2 port %d-%d\n", 960 hcd->self.busnum, portnum + 1); 961 962 port->resume_timestamp = 0; 963 clear_bit(portnum, &bus_state->resuming_ports); 964 965 reinit_completion(&port->rexit_done); 966 port->rexit_active = true; 967 968 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 969 xhci_set_link_state(xhci, port, XDEV_U0); 970 971 spin_unlock_irqrestore(&xhci->lock, *flags); 972 time_left = wait_for_completion_timeout( 973 &port->rexit_done, 974 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); 975 spin_lock_irqsave(&xhci->lock, *flags); 976 977 if (time_left) { 978 if (!port->slot_id) { 979 xhci_dbg(xhci, "slot_id is zero\n"); 980 return -ENODEV; 981 } 982 xhci_ring_device(xhci, port->slot_id); 983 } else { 984 int port_status = xhci_portsc_readl(port); 985 986 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", 987 hcd->self.busnum, portnum + 1, port_status); 988 /* 989 * keep rexit_active set if U0 transition failed so we 990 * know to report PORT_STAT_SUSPEND status back to 991 * usbcore. It will be cleared later once the port is 992 * out of RESUME/U3 state 993 */ 994 } 995 996 usb_hcd_end_port_resume(&hcd->self, portnum); 997 bus_state->port_c_suspend |= 1 << portnum; 998 bus_state->suspended_ports &= ~(1 << portnum); 999 } 1000 1001 return 0; 1002 } 1003 1004 static u32 xhci_get_ext_port_status(u32 portsc, u32 port_li) 1005 { 1006 u32 ext_stat = 0; 1007 int speed_id; 1008 1009 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 1010 speed_id = DEV_PORT_SPEED(portsc); 1011 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 1012 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 1013 1014 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 1015 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 1016 1017 return ext_stat; 1018 } 1019 1020 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, 1021 u32 portsc) 1022 { 1023 struct xhci_bus_state *bus_state; 1024 struct xhci_hcd *xhci; 1025 struct usb_hcd *hcd; 1026 u32 link_state; 1027 u32 portnum; 1028 1029 bus_state = &port->rhub->bus_state; 1030 xhci = hcd_to_xhci(port->rhub->hcd); 1031 hcd = port->rhub->hcd; 1032 link_state = portsc & PORT_PLS_MASK; 1033 portnum = port->hcd_portnum; 1034 1035 /* USB3 specific wPortChange bits 1036 * 1037 * Port link change with port in resume state should not be 1038 * reported to usbcore, as this is an internal state to be 1039 * handled by xhci driver. Reporting PLC to usbcore may 1040 * cause usbcore clearing PLC first and port change event 1041 * irq won't be generated. 1042 */ 1043 1044 if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) 1045 *status |= USB_PORT_STAT_C_LINK_STATE << 16; 1046 if (portsc & PORT_WRC) 1047 *status |= USB_PORT_STAT_C_BH_RESET << 16; 1048 if (portsc & PORT_CEC) 1049 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 1050 1051 /* USB3 specific wPortStatus bits */ 1052 if (portsc & PORT_POWER) 1053 *status |= USB_SS_PORT_STAT_POWER; 1054 1055 /* no longer suspended or resuming */ 1056 if (link_state != XDEV_U3 && 1057 link_state != XDEV_RESUME && 1058 link_state != XDEV_RECOVERY) { 1059 /* remote wake resume signaling complete */ 1060 if (bus_state->port_remote_wakeup & (1 << portnum)) { 1061 bus_state->port_remote_wakeup &= ~(1 << portnum); 1062 usb_hcd_end_port_resume(&hcd->self, portnum); 1063 } 1064 bus_state->suspended_ports &= ~(1 << portnum); 1065 } 1066 1067 xhci_hub_report_usb3_link_state(xhci, status, portsc); 1068 xhci_del_comp_mod_timer(xhci, portsc, portnum); 1069 } 1070 1071 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, 1072 u32 portsc, unsigned long *flags) 1073 { 1074 struct xhci_bus_state *bus_state; 1075 u32 link_state; 1076 u32 portnum; 1077 int err; 1078 1079 bus_state = &port->rhub->bus_state; 1080 link_state = portsc & PORT_PLS_MASK; 1081 portnum = port->hcd_portnum; 1082 1083 /* USB2 wPortStatus bits */ 1084 if (portsc & PORT_POWER) { 1085 *status |= USB_PORT_STAT_POWER; 1086 1087 /* link state is only valid if port is powered */ 1088 if (link_state == XDEV_U3) 1089 *status |= USB_PORT_STAT_SUSPEND; 1090 if (link_state == XDEV_U2) 1091 *status |= USB_PORT_STAT_L1; 1092 if (link_state == XDEV_U0) { 1093 if (bus_state->suspended_ports & (1 << portnum)) { 1094 bus_state->suspended_ports &= ~(1 << portnum); 1095 bus_state->port_c_suspend |= 1 << portnum; 1096 } 1097 } 1098 if (link_state == XDEV_RESUME) { 1099 err = xhci_handle_usb2_port_link_resume(port, portsc, 1100 flags); 1101 if (err < 0) 1102 *status = 0xffffffff; 1103 else if (port->resume_timestamp || port->rexit_active) 1104 *status |= USB_PORT_STAT_SUSPEND; 1105 } 1106 } 1107 1108 /* 1109 * Clear usb2 resume signalling variables if port is no longer suspended 1110 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a 1111 * error state. Resume related variables should be cleared in all those cases. 1112 */ 1113 if (link_state != XDEV_U3 && link_state != XDEV_RESUME) { 1114 if (port->resume_timestamp || 1115 test_bit(portnum, &bus_state->resuming_ports)) { 1116 port->resume_timestamp = 0; 1117 clear_bit(portnum, &bus_state->resuming_ports); 1118 usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum); 1119 } 1120 port->rexit_active = 0; 1121 bus_state->suspended_ports &= ~(1 << portnum); 1122 } 1123 } 1124 1125 /* 1126 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 1127 * 3.0 hubs use. 1128 * 1129 * Possible side effects: 1130 * - Mark a port as being done with device resume, 1131 * and ring the endpoint doorbells. 1132 * - Stop the Synopsys redriver Compliance Mode polling. 1133 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 1134 */ 1135 static u32 xhci_get_port_status(struct usb_hcd *hcd, struct xhci_bus_state *bus_state, 1136 int portnum, u32 portsc, unsigned long *flags) 1137 __releases(&xhci->lock) 1138 __acquires(&xhci->lock) 1139 { 1140 u32 status = 0; 1141 struct xhci_hub *rhub; 1142 struct xhci_port *port; 1143 1144 rhub = xhci_get_rhub(hcd); 1145 port = rhub->ports[portnum]; 1146 1147 /* common wPortChange bits */ 1148 if (portsc & PORT_CSC) 1149 status |= USB_PORT_STAT_C_CONNECTION << 16; 1150 if (portsc & PORT_PEC) 1151 status |= USB_PORT_STAT_C_ENABLE << 16; 1152 if (portsc & PORT_OCC) 1153 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1154 if (portsc & PORT_RC) 1155 status |= USB_PORT_STAT_C_RESET << 16; 1156 1157 /* common wPortStatus bits */ 1158 if (portsc & PORT_CONNECT) { 1159 status |= USB_PORT_STAT_CONNECTION; 1160 status |= xhci_port_speed(portsc); 1161 } 1162 if (portsc & PORT_PE) 1163 status |= USB_PORT_STAT_ENABLE; 1164 if (portsc & PORT_OC) 1165 status |= USB_PORT_STAT_OVERCURRENT; 1166 if (portsc & PORT_RESET) 1167 status |= USB_PORT_STAT_RESET; 1168 1169 /* USB2 and USB3 specific bits, including Port Link State */ 1170 if (hcd->speed >= HCD_USB3) 1171 xhci_get_usb3_port_status(port, &status, portsc); 1172 else 1173 xhci_get_usb2_port_status(port, &status, portsc, flags); 1174 1175 if (bus_state->port_c_suspend & (1 << portnum)) 1176 status |= USB_PORT_STAT_C_SUSPEND << 16; 1177 1178 return status; 1179 } 1180 1181 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1182 u16 wIndex, char *buf, u16 wLength) 1183 { 1184 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1185 int max_ports; 1186 unsigned long flags; 1187 u32 portsc, portpmsc, status; 1188 int retval = 0; 1189 struct xhci_bus_state *bus_state; 1190 u16 link_state; 1191 u16 wake_mask; 1192 u8 timeout; 1193 u8 test_mode; 1194 u8 desc_type; 1195 struct xhci_hub *rhub; 1196 struct xhci_port **ports; 1197 struct xhci_port *port; 1198 int portnum; 1199 1200 rhub = xhci_get_rhub(hcd); 1201 ports = rhub->ports; 1202 max_ports = rhub->num_ports; 1203 bus_state = &rhub->bus_state; 1204 1205 spin_lock_irqsave(&xhci->lock, flags); 1206 switch (typeReq) { 1207 case GetHubStatus: 1208 /* No power source, over-current reported per port */ 1209 memset(buf, 0, 4); 1210 break; 1211 case GetHubDescriptor: 1212 desc_type = (wValue & 0xff00) >> 8; 1213 /* Check to make sure userspace is asking for the USB 3.0 hub 1214 * descriptor for the USB 3.0 roothub. If not, we stall the 1215 * endpoint, like external hubs do. 1216 */ 1217 if (hcd->speed >= HCD_USB3 && 1218 (wLength < USB_DT_SS_HUB_SIZE || desc_type != USB_DT_SS_HUB)) { 1219 xhci_dbg(xhci, "Wrong hub descriptor type for " 1220 "USB 3.0 roothub.\n"); 1221 goto error; 1222 } 1223 xhci_hub_descriptor(hcd, xhci, 1224 (struct usb_hub_descriptor *) buf); 1225 break; 1226 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1227 desc_type = (wValue & 0xff00) >> 8; 1228 if (desc_type != USB_DT_BOS) 1229 goto error; 1230 1231 if (hcd->speed < HCD_USB3) 1232 goto error; 1233 1234 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength); 1235 spin_unlock_irqrestore(&xhci->lock, flags); 1236 return retval; 1237 case GetPortStatus: 1238 portnum = (wIndex & 0xff) - 1; 1239 if (!in_range(portnum, 0, max_ports)) 1240 goto error; 1241 1242 port = ports[portnum]; 1243 portsc = xhci_portsc_readl(port); 1244 if (portsc == ~(u32)0) { 1245 xhci_hc_died(xhci); 1246 retval = -ENODEV; 1247 break; 1248 } 1249 trace_xhci_get_port_status(port, portsc); 1250 status = xhci_get_port_status(hcd, bus_state, portnum, portsc, &flags); 1251 if (status == 0xffffffff) 1252 goto error; 1253 1254 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", 1255 hcd->self.busnum, portnum + 1, portsc, status); 1256 1257 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1258 /* if USB 3.1 extended port status return additional 4 bytes */ 1259 if (wValue == HUB_EXT_PORT_STATUS) { 1260 u32 port_li; 1261 1262 if (hcd->speed < HCD_USB31 || wLength != 8) { 1263 xhci_err(xhci, "get ext port status invalid parameter\n"); 1264 retval = -EINVAL; 1265 break; 1266 } 1267 port_li = readl(&port->port_reg->portli); 1268 status = xhci_get_ext_port_status(portsc, port_li); 1269 put_unaligned_le32(status, &buf[4]); 1270 } 1271 break; 1272 case SetPortFeature: 1273 portnum = (wIndex & 0xff) - 1; 1274 if (!in_range(portnum, 0, max_ports)) 1275 goto error; 1276 1277 port = ports[portnum]; 1278 portsc = xhci_portsc_readl(port); 1279 if (portsc == ~(u32)0) { 1280 xhci_hc_died(xhci); 1281 retval = -ENODEV; 1282 break; 1283 } 1284 portsc = xhci_port_state_to_neutral(portsc); 1285 /* FIXME: What new port features do we need to support? */ 1286 switch (wValue) { 1287 case USB_PORT_FEAT_SUSPEND: 1288 portsc = xhci_portsc_readl(port); 1289 if ((portsc & PORT_PLS_MASK) != XDEV_U0) { 1290 /* Resume the port to U0 first */ 1291 xhci_set_link_state(xhci, port, XDEV_U0); 1292 spin_unlock_irqrestore(&xhci->lock, flags); 1293 msleep(10); 1294 spin_lock_irqsave(&xhci->lock, flags); 1295 } 1296 /* In spec software should not attempt to suspend 1297 * a port unless the port reports that it is in the 1298 * enabled (PED = '1',PLS < '3') state. 1299 */ 1300 portsc = xhci_portsc_readl(port); 1301 if ((portsc & PORT_PE) == 0 || (portsc & PORT_RESET) || 1302 (portsc & PORT_PLS_MASK) >= XDEV_U3) { 1303 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", 1304 hcd->self.busnum, portnum + 1); 1305 goto error; 1306 } 1307 1308 if (!port->slot_id) { 1309 xhci_warn(xhci, "slot_id is zero\n"); 1310 goto error; 1311 } 1312 /* unlock to execute stop endpoint commands */ 1313 spin_unlock_irqrestore(&xhci->lock, flags); 1314 xhci_stop_device(xhci, port->slot_id, 1); 1315 spin_lock_irqsave(&xhci->lock, flags); 1316 1317 xhci_set_link_state(xhci, port, XDEV_U3); 1318 1319 spin_unlock_irqrestore(&xhci->lock, flags); 1320 msleep(10); /* wait device to enter */ 1321 spin_lock_irqsave(&xhci->lock, flags); 1322 1323 portsc = xhci_portsc_readl(port); 1324 bus_state->suspended_ports |= 1 << portnum; 1325 break; 1326 case USB_PORT_FEAT_LINK_STATE: 1327 link_state = (wIndex & 0xff00) >> 3; 1328 portsc = xhci_portsc_readl(port); 1329 /* Disable port */ 1330 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1331 xhci_dbg(xhci, "Disable port %d-%d\n", 1332 hcd->self.busnum, portnum + 1); 1333 portsc = xhci_port_state_to_neutral(portsc); 1334 /* 1335 * Clear all change bits, so that we get a new 1336 * connection event. 1337 */ 1338 portsc |= PORT_CSC | PORT_PEC | PORT_WRC | 1339 PORT_OCC | PORT_RC | PORT_PLC | 1340 PORT_CEC; 1341 xhci_portsc_writel(port, portsc | PORT_PE); 1342 portsc = xhci_portsc_readl(port); 1343 break; 1344 } 1345 1346 /* Put link in RxDetect (enable port) */ 1347 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1348 xhci_dbg(xhci, "Enable port %d-%d\n", 1349 hcd->self.busnum, portnum + 1); 1350 xhci_set_link_state(xhci, port, XDEV_RXDETECT); 1351 portsc = xhci_portsc_readl(port); 1352 break; 1353 } 1354 1355 /* 1356 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1357 * root hub port's transition to compliance mode upon 1358 * detecting LFPS timeout may be controlled by an 1359 * Compliance Transition Enabled (CTE) flag (not 1360 * software visible). This flag is set by writing 0xA 1361 * to PORTSC PLS field which will allow transition to 1362 * compliance mode the next time LFPS timeout is 1363 * encountered. A warm reset will clear it. 1364 * 1365 * The CTE flag is only supported if the HCCPARAMS2 CTC 1366 * flag is set, otherwise, the compliance substate is 1367 * automatically entered as on 1.0 and prior. 1368 */ 1369 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1370 if (!(xhci->hcc_params2 & HCC2_CTC)) { 1371 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1372 break; 1373 } 1374 1375 if ((portsc & PORT_CONNECT)) { 1376 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1377 goto error; 1378 } 1379 1380 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", 1381 hcd->self.busnum, portnum + 1); 1382 xhci_set_link_state(xhci, port, XDEV_COMP_MODE); 1383 1384 portsc = xhci_portsc_readl(port); 1385 break; 1386 } 1387 /* Port must be enabled */ 1388 if (!(portsc & PORT_PE)) { 1389 retval = -ENODEV; 1390 break; 1391 } 1392 /* Can't set port link state above '3' (U3) */ 1393 if (link_state > USB_SS_PORT_LS_U3) { 1394 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", 1395 hcd->self.busnum, portnum + 1, link_state); 1396 goto error; 1397 } 1398 1399 /* 1400 * set link to U0, steps depend on current link state. 1401 * U3: set link to U0 and wait for u3exit completion. 1402 * U1/U2: no PLC complete event, only set link to U0. 1403 * Resume/Recovery: device initiated U0, only wait for 1404 * completion 1405 */ 1406 if (link_state == USB_SS_PORT_LS_U0) { 1407 u32 pls = portsc & PORT_PLS_MASK; 1408 bool wait_u0 = false; 1409 1410 /* already in U0 */ 1411 if (pls == XDEV_U0) 1412 break; 1413 if (pls == XDEV_U3 || 1414 pls == XDEV_RESUME || 1415 pls == XDEV_RECOVERY) { 1416 wait_u0 = true; 1417 reinit_completion(&port->u3exit_done); 1418 } 1419 if (pls <= XDEV_U3) /* U1, U2, U3 */ 1420 xhci_set_link_state(xhci, port, XDEV_U0); 1421 if (!wait_u0) { 1422 if (pls > XDEV_U3) 1423 goto error; 1424 break; 1425 } 1426 spin_unlock_irqrestore(&xhci->lock, flags); 1427 if (!wait_for_completion_timeout(&port->u3exit_done, 1428 msecs_to_jiffies(500))) 1429 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", 1430 hcd->self.busnum, portnum + 1); 1431 spin_lock_irqsave(&xhci->lock, flags); 1432 portsc = xhci_portsc_readl(port); 1433 break; 1434 } 1435 1436 if (link_state == USB_SS_PORT_LS_U3) { 1437 int retries = 16; 1438 if (port->slot_id) { 1439 /* unlock to execute stop endpoint 1440 * commands */ 1441 spin_unlock_irqrestore(&xhci->lock, 1442 flags); 1443 xhci_stop_device(xhci, port->slot_id, 1); 1444 spin_lock_irqsave(&xhci->lock, flags); 1445 } 1446 xhci_set_link_state(xhci, port, XDEV_U3); 1447 spin_unlock_irqrestore(&xhci->lock, flags); 1448 while (retries--) { 1449 usleep_range(4000, 8000); 1450 portsc = xhci_portsc_readl(port); 1451 if ((portsc & PORT_PLS_MASK) == XDEV_U3) 1452 break; 1453 } 1454 spin_lock_irqsave(&xhci->lock, flags); 1455 portsc = xhci_portsc_readl(port); 1456 bus_state->suspended_ports |= 1 << portnum; 1457 } 1458 break; 1459 case USB_PORT_FEAT_POWER: 1460 /* 1461 * Turn on ports, even if there isn't per-port switching. 1462 * HC will report connect events even before this is set. 1463 * However, hub_wq will ignore the roothub events until 1464 * the roothub is registered. 1465 */ 1466 xhci_set_port_power(xhci, port, true, &flags); 1467 break; 1468 case USB_PORT_FEAT_RESET: 1469 portsc |= PORT_RESET; 1470 xhci_portsc_writel(port, portsc); 1471 1472 portsc = xhci_portsc_readl(port); 1473 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", 1474 hcd->self.busnum, portnum + 1, portsc); 1475 break; 1476 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1477 wake_mask = wIndex & 0xff00; 1478 xhci_set_remote_wake_mask(xhci, port, wake_mask); 1479 portsc = xhci_portsc_readl(port); 1480 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", 1481 hcd->self.busnum, portnum + 1, portsc); 1482 break; 1483 case USB_PORT_FEAT_BH_PORT_RESET: 1484 portsc |= PORT_WR; 1485 xhci_portsc_writel(port, portsc); 1486 portsc = xhci_portsc_readl(port); 1487 break; 1488 case USB_PORT_FEAT_U1_TIMEOUT: 1489 if (hcd->speed < HCD_USB3) 1490 goto error; 1491 1492 timeout = (wIndex & 0xff00) >> 8; 1493 portpmsc = readl(&port->port_reg->portpmsc); 1494 portpmsc &= ~PORT_U1_TIMEOUT_MASK; 1495 portpmsc |= PORT_U1_TIMEOUT(timeout); 1496 writel(portpmsc, &port->port_reg->portpmsc); 1497 break; 1498 case USB_PORT_FEAT_U2_TIMEOUT: 1499 if (hcd->speed < HCD_USB3) 1500 goto error; 1501 1502 timeout = (wIndex & 0xff00) >> 8; 1503 portpmsc = readl(&port->port_reg->portpmsc); 1504 portpmsc &= ~PORT_U2_TIMEOUT_MASK; 1505 portpmsc |= PORT_U2_TIMEOUT(timeout); 1506 writel(portpmsc, &port->port_reg->portpmsc); 1507 break; 1508 case USB_PORT_FEAT_TEST: 1509 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1510 if (hcd->speed != HCD_USB2) 1511 goto error; 1512 1513 test_mode = (wIndex & 0xff00) >> 8; 1514 if (test_mode > USB_TEST_FORCE_ENABLE || 1515 test_mode < USB_TEST_J) 1516 goto error; 1517 retval = xhci_enter_test_mode(xhci, test_mode, portnum, &flags); 1518 break; 1519 default: 1520 goto error; 1521 } 1522 /* unblock any posted writes */ 1523 portsc = xhci_portsc_readl(port); 1524 break; 1525 case ClearPortFeature: 1526 portnum = (wIndex & 0xff) - 1; 1527 if (!in_range(portnum, 0, max_ports)) 1528 goto error; 1529 1530 port = ports[portnum]; 1531 portsc = xhci_portsc_readl(port); 1532 if (portsc == ~(u32)0) { 1533 xhci_hc_died(xhci); 1534 retval = -ENODEV; 1535 break; 1536 } 1537 /* FIXME: What new port features do we need to support? */ 1538 portsc = xhci_port_state_to_neutral(portsc); 1539 switch (wValue) { 1540 case USB_PORT_FEAT_SUSPEND: 1541 portsc = xhci_portsc_readl(port); 1542 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1543 xhci_dbg(xhci, "PORTSC %04x\n", portsc); 1544 if (portsc & PORT_RESET) 1545 goto error; 1546 if ((portsc & PORT_PLS_MASK) == XDEV_U3) { 1547 if ((portsc & PORT_PE) == 0) 1548 goto error; 1549 1550 set_bit(portnum, &bus_state->resuming_ports); 1551 usb_hcd_start_port_resume(&hcd->self, portnum); 1552 xhci_set_link_state(xhci, port, XDEV_RESUME); 1553 spin_unlock_irqrestore(&xhci->lock, flags); 1554 msleep(USB_RESUME_TIMEOUT); 1555 spin_lock_irqsave(&xhci->lock, flags); 1556 xhci_set_link_state(xhci, port, XDEV_U0); 1557 clear_bit(portnum, &bus_state->resuming_ports); 1558 usb_hcd_end_port_resume(&hcd->self, portnum); 1559 } 1560 bus_state->port_c_suspend |= 1 << portnum; 1561 1562 if (!port->slot_id) { 1563 xhci_dbg(xhci, "slot_id is zero\n"); 1564 goto error; 1565 } 1566 xhci_ring_device(xhci, port->slot_id); 1567 break; 1568 case USB_PORT_FEAT_C_SUSPEND: 1569 bus_state->port_c_suspend &= ~(1 << portnum); 1570 fallthrough; 1571 case USB_PORT_FEAT_C_RESET: 1572 case USB_PORT_FEAT_C_BH_PORT_RESET: 1573 case USB_PORT_FEAT_C_CONNECTION: 1574 case USB_PORT_FEAT_C_OVER_CURRENT: 1575 case USB_PORT_FEAT_C_ENABLE: 1576 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1577 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1578 xhci_clear_port_change_bit(xhci, wValue, port, portsc); 1579 break; 1580 case USB_PORT_FEAT_ENABLE: 1581 xhci_disable_port(xhci, port); 1582 break; 1583 case USB_PORT_FEAT_POWER: 1584 xhci_set_port_power(xhci, port, false, &flags); 1585 break; 1586 case USB_PORT_FEAT_TEST: 1587 retval = xhci_exit_test_mode(xhci); 1588 break; 1589 default: 1590 goto error; 1591 } 1592 break; 1593 default: 1594 error: 1595 /* "stall" on error */ 1596 retval = -EPIPE; 1597 } 1598 spin_unlock_irqrestore(&xhci->lock, flags); 1599 return retval; 1600 } 1601 EXPORT_SYMBOL_GPL(xhci_hub_control); 1602 1603 /* 1604 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1605 * Ports are 0-indexed from the HCD point of view, 1606 * and 1-indexed from the USB core pointer of view. 1607 * 1608 * Note that the status change bits will be cleared as soon as a port status 1609 * change event is generated, so we use the saved status from that event. 1610 */ 1611 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1612 { 1613 unsigned long flags; 1614 u32 temp, status; 1615 u32 mask; 1616 int i, retval; 1617 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1618 int max_ports; 1619 struct xhci_bus_state *bus_state; 1620 bool reset_change = false; 1621 struct xhci_hub *rhub; 1622 struct xhci_port **ports; 1623 1624 rhub = xhci_get_rhub(hcd); 1625 ports = rhub->ports; 1626 max_ports = rhub->num_ports; 1627 bus_state = &rhub->bus_state; 1628 1629 /* Initial status is no changes */ 1630 retval = (max_ports + 8) / 8; 1631 memset(buf, 0, retval); 1632 1633 /* 1634 * Inform the usbcore about resume-in-progress by returning 1635 * a non-zero value even if there are no status changes. 1636 */ 1637 spin_lock_irqsave(&xhci->lock, flags); 1638 1639 status = bus_state->resuming_ports; 1640 1641 /* 1642 * SS devices are only visible to roothub after link training completes. 1643 * Keep polling roothubs for a grace period after xHC start 1644 */ 1645 if (hcd->speed >= HCD_USB3 && xhci->run_graceperiod) { 1646 if (time_before(jiffies, xhci->run_graceperiod)) 1647 status = 1; 1648 else 1649 xhci->run_graceperiod = 0; 1650 } 1651 1652 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1653 1654 /* For each port, did anything change? If so, set that bit in buf. */ 1655 for (i = 0; i < max_ports; i++) { 1656 temp = xhci_portsc_readl(ports[i]); 1657 if (temp == ~(u32)0) { 1658 xhci_hc_died(xhci); 1659 retval = -ENODEV; 1660 break; 1661 } 1662 trace_xhci_hub_status_data(ports[i], temp); 1663 1664 if ((temp & mask) != 0 || 1665 (bus_state->port_c_suspend & 1 << i) || 1666 (ports[i]->resume_timestamp && time_after_eq( 1667 jiffies, ports[i]->resume_timestamp))) { 1668 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1669 status = 1; 1670 } 1671 if ((temp & PORT_RC)) 1672 reset_change = true; 1673 if (temp & PORT_OC) 1674 status = 1; 1675 } 1676 if (!status && !reset_change) { 1677 xhci_dbg(xhci, "%s: stopping usb%d port polling\n", 1678 __func__, hcd->self.busnum); 1679 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1680 } 1681 spin_unlock_irqrestore(&xhci->lock, flags); 1682 return status ? retval : 0; 1683 } 1684 1685 #ifdef CONFIG_PM 1686 1687 int xhci_bus_suspend(struct usb_hcd *hcd) 1688 { 1689 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1690 int max_ports, port_index; 1691 struct xhci_bus_state *bus_state; 1692 unsigned long flags; 1693 struct xhci_hub *rhub; 1694 struct xhci_port **ports; 1695 u32 portsc_buf[USB_MAXCHILDREN]; 1696 bool wake_enabled; 1697 1698 rhub = xhci_get_rhub(hcd); 1699 ports = rhub->ports; 1700 max_ports = rhub->num_ports; 1701 bus_state = &rhub->bus_state; 1702 wake_enabled = hcd->self.root_hub->do_remote_wakeup; 1703 1704 spin_lock_irqsave(&xhci->lock, flags); 1705 1706 if (wake_enabled) { 1707 if (bus_state->resuming_ports || /* USB2 */ 1708 bus_state->port_remote_wakeup) { /* USB3 */ 1709 spin_unlock_irqrestore(&xhci->lock, flags); 1710 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n", 1711 hcd->self.busnum); 1712 return -EBUSY; 1713 } 1714 } 1715 /* 1716 * Prepare ports for suspend, but don't write anything before all ports 1717 * are checked and we know bus suspend can proceed 1718 */ 1719 bus_state->bus_suspended = 0; 1720 port_index = max_ports; 1721 while (port_index--) { 1722 u32 t1, t2; 1723 int retries = 10; 1724 retry: 1725 t1 = xhci_portsc_readl(ports[port_index]); 1726 t2 = xhci_port_state_to_neutral(t1); 1727 portsc_buf[port_index] = 0; 1728 1729 /* 1730 * Give a USB3 port in link training time to finish, but don't 1731 * prevent suspend as port might be stuck 1732 */ 1733 if ((hcd->speed >= HCD_USB3) && retries-- && 1734 (t1 & PORT_PLS_MASK) == XDEV_POLLING) { 1735 spin_unlock_irqrestore(&xhci->lock, flags); 1736 msleep(XHCI_PORT_POLLING_LFPS_TIME); 1737 spin_lock_irqsave(&xhci->lock, flags); 1738 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", 1739 hcd->self.busnum, port_index + 1); 1740 goto retry; 1741 } 1742 /* bail out if port detected a over-current condition */ 1743 if (t1 & PORT_OC) { 1744 bus_state->bus_suspended = 0; 1745 spin_unlock_irqrestore(&xhci->lock, flags); 1746 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); 1747 return -EBUSY; 1748 } 1749 /* suspend ports in U0, or bail out for new connect changes */ 1750 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { 1751 if ((t1 & PORT_CSC) && wake_enabled) { 1752 bus_state->bus_suspended = 0; 1753 spin_unlock_irqrestore(&xhci->lock, flags); 1754 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); 1755 return -EBUSY; 1756 } 1757 xhci_dbg(xhci, "port %d-%d not suspended\n", 1758 hcd->self.busnum, port_index + 1); 1759 t2 &= ~PORT_PLS_MASK; 1760 t2 |= PORT_LINK_STROBE | XDEV_U3; 1761 set_bit(port_index, &bus_state->bus_suspended); 1762 } 1763 /* USB core sets remote wake mask for USB 3.0 hubs, 1764 * including the USB 3.0 roothub, but only if CONFIG_PM 1765 * is enabled, so also enable remote wake here. 1766 */ 1767 if (wake_enabled) { 1768 if (t1 & PORT_CONNECT) { 1769 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1770 t2 &= ~PORT_WKCONN_E; 1771 } else { 1772 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1773 t2 &= ~PORT_WKDISC_E; 1774 } 1775 1776 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1777 (hcd->speed < HCD_USB3)) { 1778 if (usb_amd_pt_check_port(hcd->self.controller, 1779 port_index)) 1780 t2 &= ~PORT_WAKE_BITS; 1781 } 1782 } else 1783 t2 &= ~PORT_WAKE_BITS; 1784 1785 t1 = xhci_port_state_to_neutral(t1); 1786 if (t1 != t2) 1787 portsc_buf[port_index] = t2; 1788 } 1789 1790 /* write port settings, stopping and suspending ports if needed */ 1791 port_index = max_ports; 1792 while (port_index--) { 1793 if (!portsc_buf[port_index]) 1794 continue; 1795 if (test_bit(port_index, &bus_state->bus_suspended)) { 1796 int slot_id = ports[port_index]->slot_id; 1797 if (slot_id) { 1798 spin_unlock_irqrestore(&xhci->lock, flags); 1799 xhci_stop_device(xhci, slot_id, 1); 1800 spin_lock_irqsave(&xhci->lock, flags); 1801 } 1802 } 1803 xhci_portsc_writel(ports[port_index], portsc_buf[port_index]); 1804 } 1805 hcd->state = HC_STATE_SUSPENDED; 1806 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1807 spin_unlock_irqrestore(&xhci->lock, flags); 1808 1809 if (bus_state->bus_suspended) 1810 usleep_range(5000, 10000); 1811 1812 return 0; 1813 } 1814 1815 /* 1816 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1817 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1818 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1819 */ 1820 static bool xhci_port_missing_cas_quirk(struct xhci_port *port) 1821 { 1822 u32 portsc; 1823 1824 portsc = xhci_portsc_readl(port); 1825 1826 /* if any of these are set we are not stuck */ 1827 if (portsc & (PORT_CONNECT | PORT_CAS)) 1828 return false; 1829 1830 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1831 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1832 return false; 1833 1834 /* clear wakeup/change bits, and do a warm port reset */ 1835 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1836 portsc |= PORT_WR; 1837 xhci_portsc_writel(port, portsc); 1838 /* flush write */ 1839 xhci_portsc_readl(port); 1840 return true; 1841 } 1842 1843 int xhci_bus_resume(struct usb_hcd *hcd) 1844 { 1845 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1846 struct xhci_bus_state *bus_state; 1847 unsigned long flags; 1848 int max_ports, port_index; 1849 int sret; 1850 u32 next_state; 1851 u32 portsc; 1852 struct xhci_hub *rhub; 1853 struct xhci_port **ports; 1854 bool disabled_irq = false; 1855 1856 rhub = xhci_get_rhub(hcd); 1857 ports = rhub->ports; 1858 max_ports = rhub->num_ports; 1859 bus_state = &rhub->bus_state; 1860 1861 if (time_before(jiffies, bus_state->next_statechange)) 1862 msleep(5); 1863 1864 spin_lock_irqsave(&xhci->lock, flags); 1865 if (!HCD_HW_ACCESSIBLE(hcd)) { 1866 spin_unlock_irqrestore(&xhci->lock, flags); 1867 return -ESHUTDOWN; 1868 } 1869 1870 /* bus specific resume for ports we suspended at bus_suspend */ 1871 if (hcd->speed >= HCD_USB3) { 1872 next_state = XDEV_U0; 1873 } else { 1874 next_state = XDEV_RESUME; 1875 if (bus_state->bus_suspended) { 1876 /* 1877 * prevent port event interrupts from interfering 1878 * with usb2 port resume process 1879 */ 1880 xhci_disable_interrupter(xhci, xhci->interrupters[0]); 1881 disabled_irq = true; 1882 } 1883 } 1884 port_index = max_ports; 1885 while (port_index--) { 1886 portsc = xhci_portsc_readl(ports[port_index]); 1887 1888 /* warm reset CAS limited ports stuck in polling/compliance */ 1889 if ((xhci->quirks & XHCI_MISSING_CAS) && 1890 (hcd->speed >= HCD_USB3) && 1891 xhci_port_missing_cas_quirk(ports[port_index])) { 1892 xhci_dbg(xhci, "reset stuck port %d-%d\n", 1893 hcd->self.busnum, port_index + 1); 1894 clear_bit(port_index, &bus_state->bus_suspended); 1895 continue; 1896 } 1897 /* resume if we suspended the link, and it is still suspended */ 1898 if (test_bit(port_index, &bus_state->bus_suspended)) 1899 switch (portsc & PORT_PLS_MASK) { 1900 case XDEV_U3: 1901 portsc = xhci_port_state_to_neutral(portsc); 1902 portsc &= ~PORT_PLS_MASK; 1903 portsc |= PORT_LINK_STROBE | next_state; 1904 break; 1905 case XDEV_RESUME: 1906 /* resume already initiated */ 1907 break; 1908 default: 1909 /* not in a resumable state, ignore it */ 1910 clear_bit(port_index, 1911 &bus_state->bus_suspended); 1912 break; 1913 } 1914 /* disable wake for all ports, write new link state if needed */ 1915 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1916 xhci_portsc_writel(ports[port_index], portsc); 1917 } 1918 1919 /* USB2 specific resume signaling delay and U0 link state transition */ 1920 if (hcd->speed < HCD_USB3) { 1921 if (bus_state->bus_suspended) { 1922 spin_unlock_irqrestore(&xhci->lock, flags); 1923 msleep(USB_RESUME_TIMEOUT); 1924 spin_lock_irqsave(&xhci->lock, flags); 1925 } 1926 for_each_set_bit(port_index, &bus_state->bus_suspended, 1927 BITS_PER_LONG) { 1928 /* Clear PLC to poll it later for U0 transition */ 1929 xhci_test_and_clear_bit(xhci, ports[port_index], 1930 PORT_PLC); 1931 xhci_set_link_state(xhci, ports[port_index], XDEV_U0); 1932 } 1933 } 1934 1935 /* poll for U0 link state complete, both USB2 and USB3 */ 1936 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1937 sret = xhci_handshake(&ports[port_index]->port_reg->portsc, PORT_PLC, 1938 PORT_PLC, 10 * 1000); 1939 if (sret) { 1940 xhci_warn(xhci, "port %d-%d resume PLC timeout\n", 1941 hcd->self.busnum, port_index + 1); 1942 continue; 1943 } 1944 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); 1945 if (ports[port_index]->slot_id) 1946 xhci_ring_device(xhci, ports[port_index]->slot_id); 1947 } 1948 (void) readl(&xhci->op_regs->command); 1949 1950 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1951 /* re-enable interrupter */ 1952 if (disabled_irq) 1953 xhci_enable_interrupter(xhci->interrupters[0]); 1954 1955 spin_unlock_irqrestore(&xhci->lock, flags); 1956 return 0; 1957 } 1958 1959 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) 1960 { 1961 struct xhci_hub *rhub = xhci_get_rhub(hcd); 1962 1963 /* USB3 port wakeups are reported via usb_wakeup_notification() */ 1964 return rhub->bus_state.resuming_ports; /* USB2 ports only */ 1965 } 1966 1967 #endif /* CONFIG_PM */ 1968