1 /* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 24 #include <linux/slab.h> 25 #include <asm/unaligned.h> 26 27 #include "xhci.h" 28 #include "xhci-trace.h" 29 30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 32 PORT_RC | PORT_PLC | PORT_PE) 33 34 /* USB 3 BOS descriptor and a capability descriptors, combined. 35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() 36 */ 37 static u8 usb_bos_descriptor [] = { 38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 39 USB_DT_BOS, /* __u8 bDescriptorType */ 40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 41 0x1, /* __u8 bNumDeviceCaps */ 42 /* First device capability, SuperSpeed */ 43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 46 0x00, /* bmAttributes, LTM off by default */ 47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 48 0x03, /* bFunctionalitySupport, 49 USB 3.0 speed only */ 50 0x00, /* bU1DevExitLat, set later. */ 51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ 52 /* Second device capability, SuperSpeedPlus */ 53 0x1c, /* bLength 28, will be adjusted later */ 54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ 56 0x00, /* bReserved 0 */ 57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */ 58 0x01, 0x00, /* wFunctionalitySupport */ 59 0x00, 0x00, /* wReserved 0 */ 60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */ 61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */ 62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */ 63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */ 64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */ 65 }; 66 67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, 68 u16 wLength) 69 { 70 int i, ssa_count; 71 u32 temp; 72 u16 desc_size, ssp_cap_size, ssa_size = 0; 73 bool usb3_1 = false; 74 75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; 77 78 /* does xhci support USB 3.1 Enhanced SuperSpeed */ 79 if (xhci->usb3_rhub.min_rev >= 0x01) { 80 /* does xhci provide a PSI table for SSA speed attributes? */ 81 if (xhci->usb3_rhub.psi_count) { 82 /* two SSA entries for each unique PSI ID, RX and TX */ 83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2; 84 ssa_size = ssa_count * sizeof(u32); 85 ssp_cap_size -= 16; /* skip copying the default SSA */ 86 } 87 desc_size += ssp_cap_size; 88 usb3_1 = true; 89 } 90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); 91 92 if (usb3_1) { 93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */ 94 buf[4] += 1; 95 put_unaligned_le16(desc_size + ssa_size, &buf[2]); 96 } 97 98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 99 return wLength; 100 101 /* Indicate whether the host has LTM support. */ 102 temp = readl(&xhci->cap_regs->hcc_params); 103 if (HCC_LTC(temp)) 104 buf[8] |= USB_LTM_SUPPORT; 105 106 /* Set the U1 and U2 exit latencies. */ 107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 108 temp = readl(&xhci->cap_regs->hcs_params3); 109 buf[12] = HCS_U1_LATENCY(temp); 110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 111 } 112 113 /* If PSI table exists, add the custom speed attributes from it */ 114 if (usb3_1 && xhci->usb3_rhub.psi_count) { 115 u32 ssp_cap_base, bm_attrib, psi; 116 int offset; 117 118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 119 120 if (wLength < desc_size) 121 return wLength; 122 buf[ssp_cap_base] = ssp_cap_size + ssa_size; 123 124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ 125 bm_attrib = (ssa_count - 1) & 0x1f; 126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5; 127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); 128 129 if (wLength < desc_size + ssa_size) 130 return wLength; 131 /* 132 * Create the Sublink Speed Attributes (SSA) array. 133 * The xhci PSI field and USB 3.1 SSA fields are very similar, 134 * but link type bits 7:6 differ for values 01b and 10b. 135 * xhci has also only one PSI entry for a symmetric link when 136 * USB 3.1 requires two SSA entries (RX and TX) for every link 137 */ 138 offset = desc_size; 139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) { 140 psi = xhci->usb3_rhub.psi[i]; 141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; 142 if ((psi & PLT_MASK) == PLT_SYM) { 143 /* Symmetric, create SSA RX and TX from one PSI entry */ 144 put_unaligned_le32(psi, &buf[offset]); 145 psi |= 1 << 7; /* turn entry to TX */ 146 offset += 4; 147 if (offset >= desc_size + ssa_size) 148 return desc_size + ssa_size; 149 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { 150 /* Asymetric RX, flip bits 7:6 for SSA */ 151 psi ^= PLT_MASK; 152 } 153 put_unaligned_le32(psi, &buf[offset]); 154 offset += 4; 155 if (offset >= desc_size + ssa_size) 156 return desc_size + ssa_size; 157 } 158 } 159 /* ssa_size is 0 for other than usb 3.1 hosts */ 160 return desc_size + ssa_size; 161 } 162 163 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 164 struct usb_hub_descriptor *desc, int ports) 165 { 166 u16 temp; 167 168 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 169 desc->bHubContrCurrent = 0; 170 171 desc->bNbrPorts = ports; 172 temp = 0; 173 /* Bits 1:0 - support per-port power switching, or power always on */ 174 if (HCC_PPC(xhci->hcc_params)) 175 temp |= HUB_CHAR_INDV_PORT_LPSM; 176 else 177 temp |= HUB_CHAR_NO_LPSM; 178 /* Bit 2 - root hubs are not part of a compound device */ 179 /* Bits 4:3 - individual port over current protection */ 180 temp |= HUB_CHAR_INDV_PORT_OCPM; 181 /* Bits 6:5 - no TTs in root ports */ 182 /* Bit 7 - no port indicators */ 183 desc->wHubCharacteristics = cpu_to_le16(temp); 184 } 185 186 /* Fill in the USB 2.0 roothub descriptor */ 187 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 188 struct usb_hub_descriptor *desc) 189 { 190 int ports; 191 u16 temp; 192 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 193 u32 portsc; 194 unsigned int i; 195 196 ports = xhci->num_usb2_ports; 197 198 xhci_common_hub_descriptor(xhci, desc, ports); 199 desc->bDescriptorType = USB_DT_HUB; 200 temp = 1 + (ports / 8); 201 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 202 203 /* The Device Removable bits are reported on a byte granularity. 204 * If the port doesn't exist within that byte, the bit is set to 0. 205 */ 206 memset(port_removable, 0, sizeof(port_removable)); 207 for (i = 0; i < ports; i++) { 208 portsc = readl(xhci->usb2_ports[i]); 209 /* If a device is removable, PORTSC reports a 0, same as in the 210 * hub descriptor DeviceRemovable bits. 211 */ 212 if (portsc & PORT_DEV_REMOVE) 213 /* This math is hairy because bit 0 of DeviceRemovable 214 * is reserved, and bit 1 is for port 1, etc. 215 */ 216 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 217 } 218 219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 220 * ports on it. The USB 2.0 specification says that there are two 221 * variable length fields at the end of the hub descriptor: 222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 225 * 0xFF, so we initialize the both arrays (DeviceRemovable and 226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 227 * set of ports that actually exist. 228 */ 229 memset(desc->u.hs.DeviceRemovable, 0xff, 230 sizeof(desc->u.hs.DeviceRemovable)); 231 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 232 sizeof(desc->u.hs.PortPwrCtrlMask)); 233 234 for (i = 0; i < (ports + 1 + 7) / 8; i++) 235 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 236 sizeof(__u8)); 237 } 238 239 /* Fill in the USB 3.0 roothub descriptor */ 240 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 241 struct usb_hub_descriptor *desc) 242 { 243 int ports; 244 u16 port_removable; 245 u32 portsc; 246 unsigned int i; 247 248 ports = xhci->num_usb3_ports; 249 xhci_common_hub_descriptor(xhci, desc, ports); 250 desc->bDescriptorType = USB_DT_SS_HUB; 251 desc->bDescLength = USB_DT_SS_HUB_SIZE; 252 253 /* header decode latency should be zero for roothubs, 254 * see section 4.23.5.2. 255 */ 256 desc->u.ss.bHubHdrDecLat = 0; 257 desc->u.ss.wHubDelay = 0; 258 259 port_removable = 0; 260 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 261 for (i = 0; i < ports; i++) { 262 portsc = readl(xhci->usb3_ports[i]); 263 if (portsc & PORT_DEV_REMOVE) 264 port_removable |= 1 << (i + 1); 265 } 266 267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 268 } 269 270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 271 struct usb_hub_descriptor *desc) 272 { 273 274 if (hcd->speed >= HCD_USB3) 275 xhci_usb3_hub_descriptor(hcd, xhci, desc); 276 else 277 xhci_usb2_hub_descriptor(hcd, xhci, desc); 278 279 } 280 281 static unsigned int xhci_port_speed(unsigned int port_status) 282 { 283 if (DEV_LOWSPEED(port_status)) 284 return USB_PORT_STAT_LOW_SPEED; 285 if (DEV_HIGHSPEED(port_status)) 286 return USB_PORT_STAT_HIGH_SPEED; 287 /* 288 * FIXME: Yes, we should check for full speed, but the core uses that as 289 * a default in portspeed() in usb/core/hub.c (which is the only place 290 * USB_PORT_STAT_*_SPEED is used). 291 */ 292 return 0; 293 } 294 295 /* 296 * These bits are Read Only (RO) and should be saved and written to the 297 * registers: 0, 3, 10:13, 30 298 * connect status, over-current status, port speed, and device removable. 299 * connect status and port speed are also sticky - meaning they're in 300 * the AUX well and they aren't changed by a hot, warm, or cold reset. 301 */ 302 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 303 /* 304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 305 * bits 5:8, 9, 14:15, 25:27 306 * link state, port power, port indicator state, "wake on" enable state 307 */ 308 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 309 /* 310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 311 * bit 4 (port reset) 312 */ 313 #define XHCI_PORT_RW1S ((1<<4)) 314 /* 315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 316 * bits 1, 17, 18, 19, 20, 21, 22, 23 317 * port enable/disable, and 318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 319 * over-current, reset, link state, and L1 change 320 */ 321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 322 /* 323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 324 * latched in 325 */ 326 #define XHCI_PORT_RW ((1<<16)) 327 /* 328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 329 * bits 2, 24, 28:31 330 */ 331 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 332 333 /* 334 * Given a port state, this function returns a value that would result in the 335 * port being in the same state, if the value was written to the port status 336 * control register. 337 * Save Read Only (RO) bits and save read/write bits where 338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 340 */ 341 u32 xhci_port_state_to_neutral(u32 state) 342 { 343 /* Save read-only status and port state */ 344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 345 } 346 347 /* 348 * find slot id based on port number. 349 * @port: The one-based port number from one of the two split roothubs. 350 */ 351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 352 u16 port) 353 { 354 int slot_id; 355 int i; 356 enum usb_device_speed speed; 357 358 slot_id = 0; 359 for (i = 0; i < MAX_HC_SLOTS; i++) { 360 if (!xhci->devs[i]) 361 continue; 362 speed = xhci->devs[i]->udev->speed; 363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) 364 && xhci->devs[i]->fake_port == port) { 365 slot_id = i; 366 break; 367 } 368 } 369 370 return slot_id; 371 } 372 373 /* 374 * Stop device 375 * It issues stop endpoint command for EP 0 to 30. And wait the last command 376 * to complete. 377 * suspend will set to 1, if suspend bit need to set in command. 378 */ 379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 380 { 381 struct xhci_virt_device *virt_dev; 382 struct xhci_command *cmd; 383 unsigned long flags; 384 int ret; 385 int i; 386 387 ret = 0; 388 virt_dev = xhci->devs[slot_id]; 389 if (!virt_dev) 390 return -ENODEV; 391 392 trace_xhci_stop_device(virt_dev); 393 394 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 395 if (!cmd) 396 return -ENOMEM; 397 398 spin_lock_irqsave(&xhci->lock, flags); 399 for (i = LAST_EP_INDEX; i > 0; i--) { 400 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 401 struct xhci_ep_ctx *ep_ctx; 402 struct xhci_command *command; 403 404 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 405 406 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 407 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 408 continue; 409 410 command = xhci_alloc_command(xhci, false, false, 411 GFP_NOWAIT); 412 if (!command) { 413 spin_unlock_irqrestore(&xhci->lock, flags); 414 xhci_free_command(xhci, cmd); 415 return -ENOMEM; 416 } 417 xhci_queue_stop_endpoint(xhci, command, slot_id, i, 418 suspend); 419 } 420 } 421 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 422 xhci_ring_cmd_db(xhci); 423 spin_unlock_irqrestore(&xhci->lock, flags); 424 425 /* Wait for last stop endpoint command to finish */ 426 wait_for_completion(cmd->completion); 427 428 if (cmd->status == COMP_COMMAND_ABORTED || 429 cmd->status == COMP_COMMAND_RING_STOPPED) { 430 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 431 ret = -ETIME; 432 } 433 xhci_free_command(xhci, cmd); 434 return ret; 435 } 436 437 /* 438 * Ring device, it rings the all doorbells unconditionally. 439 */ 440 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 441 { 442 int i, s; 443 struct xhci_virt_ep *ep; 444 445 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 446 ep = &xhci->devs[slot_id]->eps[i]; 447 448 if (ep->ep_state & EP_HAS_STREAMS) { 449 for (s = 1; s < ep->stream_info->num_streams; s++) 450 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 451 } else if (ep->ring && ep->ring->dequeue) { 452 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 453 } 454 } 455 456 return; 457 } 458 459 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 460 u16 wIndex, __le32 __iomem *addr, u32 port_status) 461 { 462 /* Don't allow the USB core to disable SuperSpeed ports. */ 463 if (hcd->speed >= HCD_USB3) { 464 xhci_dbg(xhci, "Ignoring request to disable " 465 "SuperSpeed port.\n"); 466 return; 467 } 468 469 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 470 xhci_dbg(xhci, 471 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 472 return; 473 } 474 475 /* Write 1 to disable the port */ 476 writel(port_status | PORT_PE, addr); 477 port_status = readl(addr); 478 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 479 wIndex, port_status); 480 } 481 482 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 483 u16 wIndex, __le32 __iomem *addr, u32 port_status) 484 { 485 char *port_change_bit; 486 u32 status; 487 488 switch (wValue) { 489 case USB_PORT_FEAT_C_RESET: 490 status = PORT_RC; 491 port_change_bit = "reset"; 492 break; 493 case USB_PORT_FEAT_C_BH_PORT_RESET: 494 status = PORT_WRC; 495 port_change_bit = "warm(BH) reset"; 496 break; 497 case USB_PORT_FEAT_C_CONNECTION: 498 status = PORT_CSC; 499 port_change_bit = "connect"; 500 break; 501 case USB_PORT_FEAT_C_OVER_CURRENT: 502 status = PORT_OCC; 503 port_change_bit = "over-current"; 504 break; 505 case USB_PORT_FEAT_C_ENABLE: 506 status = PORT_PEC; 507 port_change_bit = "enable/disable"; 508 break; 509 case USB_PORT_FEAT_C_SUSPEND: 510 status = PORT_PLC; 511 port_change_bit = "suspend/resume"; 512 break; 513 case USB_PORT_FEAT_C_PORT_LINK_STATE: 514 status = PORT_PLC; 515 port_change_bit = "link state"; 516 break; 517 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 518 status = PORT_CEC; 519 port_change_bit = "config error"; 520 break; 521 default: 522 /* Should never happen */ 523 return; 524 } 525 /* Change bits are all write 1 to clear */ 526 writel(port_status | status, addr); 527 port_status = readl(addr); 528 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 529 port_change_bit, wIndex, port_status); 530 } 531 532 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 533 { 534 int max_ports; 535 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 536 537 if (hcd->speed >= HCD_USB3) { 538 max_ports = xhci->num_usb3_ports; 539 *port_array = xhci->usb3_ports; 540 } else { 541 max_ports = xhci->num_usb2_ports; 542 *port_array = xhci->usb2_ports; 543 } 544 545 return max_ports; 546 } 547 548 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index) 549 { 550 __le32 __iomem **port_array; 551 552 xhci_get_ports(hcd, &port_array); 553 return port_array[index]; 554 } 555 556 /* 557 * xhci_set_port_power() must be called with xhci->lock held. 558 * It will release and re-aquire the lock while calling ACPI 559 * method. 560 */ 561 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, 562 u16 index, bool on, unsigned long *flags) 563 { 564 __le32 __iomem *addr; 565 u32 temp; 566 567 addr = xhci_get_port_io_addr(hcd, index); 568 temp = readl(addr); 569 temp = xhci_port_state_to_neutral(temp); 570 if (on) { 571 /* Power on */ 572 writel(temp | PORT_POWER, addr); 573 temp = readl(addr); 574 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", 575 index, temp); 576 } else { 577 /* Power off */ 578 writel(temp & ~PORT_POWER, addr); 579 } 580 581 spin_unlock_irqrestore(&xhci->lock, *flags); 582 temp = usb_acpi_power_manageable(hcd->self.root_hub, 583 index); 584 if (temp) 585 usb_acpi_set_power_state(hcd->self.root_hub, 586 index, on); 587 spin_lock_irqsave(&xhci->lock, *flags); 588 } 589 590 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, 591 u16 test_mode, u16 wIndex) 592 { 593 u32 temp; 594 __le32 __iomem *addr; 595 596 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */ 597 addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex); 598 temp = readl(addr + PORTPMSC); 599 temp |= test_mode << PORT_TEST_MODE_SHIFT; 600 writel(temp, addr + PORTPMSC); 601 xhci->test_mode = test_mode; 602 if (test_mode == TEST_FORCE_EN) 603 xhci_start(xhci); 604 } 605 606 static int xhci_enter_test_mode(struct xhci_hcd *xhci, 607 u16 test_mode, u16 wIndex, unsigned long *flags) 608 { 609 int i, retval; 610 611 /* Disable all Device Slots */ 612 xhci_dbg(xhci, "Disable all slots\n"); 613 spin_unlock_irqrestore(&xhci->lock, *flags); 614 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 615 retval = xhci_disable_slot(xhci, NULL, i); 616 if (retval) 617 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 618 i, retval); 619 } 620 spin_lock_irqsave(&xhci->lock, *flags); 621 /* Put all ports to the Disable state by clear PP */ 622 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 623 /* Power off USB3 ports*/ 624 for (i = 0; i < xhci->num_usb3_ports; i++) 625 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); 626 /* Power off USB2 ports*/ 627 for (i = 0; i < xhci->num_usb2_ports; i++) 628 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); 629 /* Stop the controller */ 630 xhci_dbg(xhci, "Stop controller\n"); 631 retval = xhci_halt(xhci); 632 if (retval) 633 return retval; 634 /* Disable runtime PM for test mode */ 635 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 636 /* Set PORTPMSC.PTC field to enter selected test mode */ 637 /* Port is selected by wIndex. port_id = wIndex + 1 */ 638 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", 639 test_mode, wIndex + 1); 640 xhci_port_set_test_mode(xhci, test_mode, wIndex); 641 return retval; 642 } 643 644 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 645 { 646 int retval; 647 648 if (!xhci->test_mode) { 649 xhci_err(xhci, "Not in test mode, do nothing.\n"); 650 return 0; 651 } 652 if (xhci->test_mode == TEST_FORCE_EN && 653 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 654 retval = xhci_halt(xhci); 655 if (retval) 656 return retval; 657 } 658 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 659 xhci->test_mode = 0; 660 return xhci_reset(xhci); 661 } 662 663 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 664 int port_id, u32 link_state) 665 { 666 u32 temp; 667 668 temp = readl(port_array[port_id]); 669 temp = xhci_port_state_to_neutral(temp); 670 temp &= ~PORT_PLS_MASK; 671 temp |= PORT_LINK_STROBE | link_state; 672 writel(temp, port_array[port_id]); 673 } 674 675 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 676 __le32 __iomem **port_array, int port_id, u16 wake_mask) 677 { 678 u32 temp; 679 680 temp = readl(port_array[port_id]); 681 temp = xhci_port_state_to_neutral(temp); 682 683 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 684 temp |= PORT_WKCONN_E; 685 else 686 temp &= ~PORT_WKCONN_E; 687 688 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 689 temp |= PORT_WKDISC_E; 690 else 691 temp &= ~PORT_WKDISC_E; 692 693 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 694 temp |= PORT_WKOC_E; 695 else 696 temp &= ~PORT_WKOC_E; 697 698 writel(temp, port_array[port_id]); 699 } 700 701 /* Test and clear port RWC bit */ 702 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 703 int port_id, u32 port_bit) 704 { 705 u32 temp; 706 707 temp = readl(port_array[port_id]); 708 if (temp & port_bit) { 709 temp = xhci_port_state_to_neutral(temp); 710 temp |= port_bit; 711 writel(temp, port_array[port_id]); 712 } 713 } 714 715 /* Updates Link Status for USB 2.1 port */ 716 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) 717 { 718 if ((status_reg & PORT_PLS_MASK) == XDEV_U2) 719 *status |= USB_PORT_STAT_L1; 720 } 721 722 /* Updates Link Status for super Speed port */ 723 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 724 u32 *status, u32 status_reg) 725 { 726 u32 pls = status_reg & PORT_PLS_MASK; 727 728 /* resume state is a xHCI internal state. 729 * Do not report it to usb core, instead, pretend to be U3, 730 * thus usb core knows it's not ready for transfer 731 */ 732 if (pls == XDEV_RESUME) { 733 *status |= USB_SS_PORT_LS_U3; 734 return; 735 } 736 737 /* When the CAS bit is set then warm reset 738 * should be performed on port 739 */ 740 if (status_reg & PORT_CAS) { 741 /* The CAS bit can be set while the port is 742 * in any link state. 743 * Only roothubs have CAS bit, so we 744 * pretend to be in compliance mode 745 * unless we're already in compliance 746 * or the inactive state. 747 */ 748 if (pls != USB_SS_PORT_LS_COMP_MOD && 749 pls != USB_SS_PORT_LS_SS_INACTIVE) { 750 pls = USB_SS_PORT_LS_COMP_MOD; 751 } 752 /* Return also connection bit - 753 * hub state machine resets port 754 * when this bit is set. 755 */ 756 pls |= USB_PORT_STAT_CONNECTION; 757 } else { 758 /* 759 * If CAS bit isn't set but the Port is already at 760 * Compliance Mode, fake a connection so the USB core 761 * notices the Compliance state and resets the port. 762 * This resolves an issue generated by the SN65LVPE502CP 763 * in which sometimes the port enters compliance mode 764 * caused by a delay on the host-device negotiation. 765 */ 766 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 767 (pls == USB_SS_PORT_LS_COMP_MOD)) 768 pls |= USB_PORT_STAT_CONNECTION; 769 } 770 771 /* update status field */ 772 *status |= pls; 773 } 774 775 /* 776 * Function for Compliance Mode Quirk. 777 * 778 * This Function verifies if all xhc USB3 ports have entered U0, if so, 779 * the compliance mode timer is deleted. A port won't enter 780 * compliance mode if it has previously entered U0. 781 */ 782 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 783 u16 wIndex) 784 { 785 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); 786 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 787 788 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 789 return; 790 791 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 792 xhci->port_status_u0 |= 1 << wIndex; 793 if (xhci->port_status_u0 == all_ports_seen_u0) { 794 del_timer_sync(&xhci->comp_mode_recovery_timer); 795 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 796 "All USB3 ports have entered U0 already!"); 797 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 798 "Compliance Mode Recovery Timer Deleted."); 799 } 800 } 801 } 802 803 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) 804 { 805 u32 ext_stat = 0; 806 int speed_id; 807 808 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 809 speed_id = DEV_PORT_SPEED(raw_port_status); 810 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 811 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 812 813 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 814 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 815 816 return ext_stat; 817 } 818 819 /* 820 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 821 * 3.0 hubs use. 822 * 823 * Possible side effects: 824 * - Mark a port as being done with device resume, 825 * and ring the endpoint doorbells. 826 * - Stop the Synopsys redriver Compliance Mode polling. 827 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 828 */ 829 static u32 xhci_get_port_status(struct usb_hcd *hcd, 830 struct xhci_bus_state *bus_state, 831 __le32 __iomem **port_array, 832 u16 wIndex, u32 raw_port_status, 833 unsigned long flags) 834 __releases(&xhci->lock) 835 __acquires(&xhci->lock) 836 { 837 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 838 u32 status = 0; 839 int slot_id; 840 841 /* wPortChange bits */ 842 if (raw_port_status & PORT_CSC) 843 status |= USB_PORT_STAT_C_CONNECTION << 16; 844 if (raw_port_status & PORT_PEC) 845 status |= USB_PORT_STAT_C_ENABLE << 16; 846 if ((raw_port_status & PORT_OCC)) 847 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 848 if ((raw_port_status & PORT_RC)) 849 status |= USB_PORT_STAT_C_RESET << 16; 850 /* USB3.0 only */ 851 if (hcd->speed >= HCD_USB3) { 852 /* Port link change with port in resume state should not be 853 * reported to usbcore, as this is an internal state to be 854 * handled by xhci driver. Reporting PLC to usbcore may 855 * cause usbcore clearing PLC first and port change event 856 * irq won't be generated. 857 */ 858 if ((raw_port_status & PORT_PLC) && 859 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) 860 status |= USB_PORT_STAT_C_LINK_STATE << 16; 861 if ((raw_port_status & PORT_WRC)) 862 status |= USB_PORT_STAT_C_BH_RESET << 16; 863 if ((raw_port_status & PORT_CEC)) 864 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 865 } 866 867 if (hcd->speed < HCD_USB3) { 868 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 869 && (raw_port_status & PORT_POWER)) 870 status |= USB_PORT_STAT_SUSPEND; 871 } 872 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && 873 !DEV_SUPERSPEED_ANY(raw_port_status)) { 874 if ((raw_port_status & PORT_RESET) || 875 !(raw_port_status & PORT_PE)) 876 return 0xffffffff; 877 /* did port event handler already start resume timing? */ 878 if (!bus_state->resume_done[wIndex]) { 879 /* If not, maybe we are in a host initated resume? */ 880 if (test_bit(wIndex, &bus_state->resuming_ports)) { 881 /* Host initated resume doesn't time the resume 882 * signalling using resume_done[]. 883 * It manually sets RESUME state, sleeps 20ms 884 * and sets U0 state. This should probably be 885 * changed, but not right now. 886 */ 887 } else { 888 /* port resume was discovered now and here, 889 * start resume timing 890 */ 891 unsigned long timeout = jiffies + 892 msecs_to_jiffies(USB_RESUME_TIMEOUT); 893 894 set_bit(wIndex, &bus_state->resuming_ports); 895 bus_state->resume_done[wIndex] = timeout; 896 mod_timer(&hcd->rh_timer, timeout); 897 } 898 /* Has resume been signalled for USB_RESUME_TIME yet? */ 899 } else if (time_after_eq(jiffies, 900 bus_state->resume_done[wIndex])) { 901 int time_left; 902 903 xhci_dbg(xhci, "Resume USB2 port %d\n", 904 wIndex + 1); 905 bus_state->resume_done[wIndex] = 0; 906 clear_bit(wIndex, &bus_state->resuming_ports); 907 908 set_bit(wIndex, &bus_state->rexit_ports); 909 910 xhci_test_and_clear_bit(xhci, port_array, wIndex, 911 PORT_PLC); 912 xhci_set_link_state(xhci, port_array, wIndex, 913 XDEV_U0); 914 915 spin_unlock_irqrestore(&xhci->lock, flags); 916 time_left = wait_for_completion_timeout( 917 &bus_state->rexit_done[wIndex], 918 msecs_to_jiffies( 919 XHCI_MAX_REXIT_TIMEOUT)); 920 spin_lock_irqsave(&xhci->lock, flags); 921 922 if (time_left) { 923 slot_id = xhci_find_slot_id_by_port(hcd, 924 xhci, wIndex + 1); 925 if (!slot_id) { 926 xhci_dbg(xhci, "slot_id is zero\n"); 927 return 0xffffffff; 928 } 929 xhci_ring_device(xhci, slot_id); 930 } else { 931 int port_status = readl(port_array[wIndex]); 932 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", 933 XHCI_MAX_REXIT_TIMEOUT, 934 port_status); 935 status |= USB_PORT_STAT_SUSPEND; 936 clear_bit(wIndex, &bus_state->rexit_ports); 937 } 938 939 bus_state->port_c_suspend |= 1 << wIndex; 940 bus_state->suspended_ports &= ~(1 << wIndex); 941 } else { 942 /* 943 * The resume has been signaling for less than 944 * USB_RESUME_TIME. Report the port status as SUSPEND, 945 * let the usbcore check port status again and clear 946 * resume signaling later. 947 */ 948 status |= USB_PORT_STAT_SUSPEND; 949 } 950 } 951 /* 952 * Clear stale usb2 resume signalling variables in case port changed 953 * state during resume signalling. For example on error 954 */ 955 if ((bus_state->resume_done[wIndex] || 956 test_bit(wIndex, &bus_state->resuming_ports)) && 957 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && 958 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { 959 bus_state->resume_done[wIndex] = 0; 960 clear_bit(wIndex, &bus_state->resuming_ports); 961 } 962 963 964 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 && 965 (raw_port_status & PORT_POWER)) { 966 if (bus_state->suspended_ports & (1 << wIndex)) { 967 bus_state->suspended_ports &= ~(1 << wIndex); 968 if (hcd->speed < HCD_USB3) 969 bus_state->port_c_suspend |= 1 << wIndex; 970 } 971 bus_state->resume_done[wIndex] = 0; 972 clear_bit(wIndex, &bus_state->resuming_ports); 973 } 974 if (raw_port_status & PORT_CONNECT) { 975 status |= USB_PORT_STAT_CONNECTION; 976 status |= xhci_port_speed(raw_port_status); 977 } 978 if (raw_port_status & PORT_PE) 979 status |= USB_PORT_STAT_ENABLE; 980 if (raw_port_status & PORT_OC) 981 status |= USB_PORT_STAT_OVERCURRENT; 982 if (raw_port_status & PORT_RESET) 983 status |= USB_PORT_STAT_RESET; 984 if (raw_port_status & PORT_POWER) { 985 if (hcd->speed >= HCD_USB3) 986 status |= USB_SS_PORT_STAT_POWER; 987 else 988 status |= USB_PORT_STAT_POWER; 989 } 990 /* Update Port Link State */ 991 if (hcd->speed >= HCD_USB3) { 992 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); 993 /* 994 * Verify if all USB3 Ports Have entered U0 already. 995 * Delete Compliance Mode Timer if so. 996 */ 997 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); 998 } else { 999 xhci_hub_report_usb2_link_state(&status, raw_port_status); 1000 } 1001 if (bus_state->port_c_suspend & (1 << wIndex)) 1002 status |= USB_PORT_STAT_C_SUSPEND << 16; 1003 1004 return status; 1005 } 1006 1007 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1008 u16 wIndex, char *buf, u16 wLength) 1009 { 1010 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1011 int max_ports; 1012 unsigned long flags; 1013 u32 temp, status; 1014 int retval = 0; 1015 __le32 __iomem **port_array; 1016 int slot_id; 1017 struct xhci_bus_state *bus_state; 1018 u16 link_state = 0; 1019 u16 wake_mask = 0; 1020 u16 timeout = 0; 1021 u16 test_mode = 0; 1022 1023 max_ports = xhci_get_ports(hcd, &port_array); 1024 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1025 1026 spin_lock_irqsave(&xhci->lock, flags); 1027 switch (typeReq) { 1028 case GetHubStatus: 1029 /* No power source, over-current reported per port */ 1030 memset(buf, 0, 4); 1031 break; 1032 case GetHubDescriptor: 1033 /* Check to make sure userspace is asking for the USB 3.0 hub 1034 * descriptor for the USB 3.0 roothub. If not, we stall the 1035 * endpoint, like external hubs do. 1036 */ 1037 if (hcd->speed >= HCD_USB3 && 1038 (wLength < USB_DT_SS_HUB_SIZE || 1039 wValue != (USB_DT_SS_HUB << 8))) { 1040 xhci_dbg(xhci, "Wrong hub descriptor type for " 1041 "USB 3.0 roothub.\n"); 1042 goto error; 1043 } 1044 xhci_hub_descriptor(hcd, xhci, 1045 (struct usb_hub_descriptor *) buf); 1046 break; 1047 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1048 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 1049 goto error; 1050 1051 if (hcd->speed < HCD_USB3) 1052 goto error; 1053 1054 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); 1055 spin_unlock_irqrestore(&xhci->lock, flags); 1056 return retval; 1057 case GetPortStatus: 1058 if (!wIndex || wIndex > max_ports) 1059 goto error; 1060 wIndex--; 1061 temp = readl(port_array[wIndex]); 1062 if (temp == ~(u32)0) { 1063 xhci_hc_died(xhci); 1064 retval = -ENODEV; 1065 break; 1066 } 1067 status = xhci_get_port_status(hcd, bus_state, port_array, 1068 wIndex, temp, flags); 1069 if (status == 0xffffffff) 1070 goto error; 1071 1072 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", 1073 wIndex, temp); 1074 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 1075 1076 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1077 /* if USB 3.1 extended port status return additional 4 bytes */ 1078 if (wValue == 0x02) { 1079 u32 port_li; 1080 1081 if (hcd->speed < HCD_USB31 || wLength != 8) { 1082 xhci_err(xhci, "get ext port status invalid parameter\n"); 1083 retval = -EINVAL; 1084 break; 1085 } 1086 port_li = readl(port_array[wIndex] + PORTLI); 1087 status = xhci_get_ext_port_status(temp, port_li); 1088 put_unaligned_le32(cpu_to_le32(status), &buf[4]); 1089 } 1090 break; 1091 case SetPortFeature: 1092 if (wValue == USB_PORT_FEAT_LINK_STATE) 1093 link_state = (wIndex & 0xff00) >> 3; 1094 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 1095 wake_mask = wIndex & 0xff00; 1096 if (wValue == USB_PORT_FEAT_TEST) 1097 test_mode = (wIndex & 0xff00) >> 8; 1098 /* The MSB of wIndex is the U1/U2 timeout */ 1099 timeout = (wIndex & 0xff00) >> 8; 1100 wIndex &= 0xff; 1101 if (!wIndex || wIndex > max_ports) 1102 goto error; 1103 wIndex--; 1104 temp = readl(port_array[wIndex]); 1105 if (temp == ~(u32)0) { 1106 xhci_hc_died(xhci); 1107 retval = -ENODEV; 1108 break; 1109 } 1110 temp = xhci_port_state_to_neutral(temp); 1111 /* FIXME: What new port features do we need to support? */ 1112 switch (wValue) { 1113 case USB_PORT_FEAT_SUSPEND: 1114 temp = readl(port_array[wIndex]); 1115 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 1116 /* Resume the port to U0 first */ 1117 xhci_set_link_state(xhci, port_array, wIndex, 1118 XDEV_U0); 1119 spin_unlock_irqrestore(&xhci->lock, flags); 1120 msleep(10); 1121 spin_lock_irqsave(&xhci->lock, flags); 1122 } 1123 /* In spec software should not attempt to suspend 1124 * a port unless the port reports that it is in the 1125 * enabled (PED = ‘1’,PLS < ‘3’) state. 1126 */ 1127 temp = readl(port_array[wIndex]); 1128 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 1129 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 1130 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n"); 1131 goto error; 1132 } 1133 1134 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1135 wIndex + 1); 1136 if (!slot_id) { 1137 xhci_warn(xhci, "slot_id is zero\n"); 1138 goto error; 1139 } 1140 /* unlock to execute stop endpoint commands */ 1141 spin_unlock_irqrestore(&xhci->lock, flags); 1142 xhci_stop_device(xhci, slot_id, 1); 1143 spin_lock_irqsave(&xhci->lock, flags); 1144 1145 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 1146 1147 spin_unlock_irqrestore(&xhci->lock, flags); 1148 msleep(10); /* wait device to enter */ 1149 spin_lock_irqsave(&xhci->lock, flags); 1150 1151 temp = readl(port_array[wIndex]); 1152 bus_state->suspended_ports |= 1 << wIndex; 1153 break; 1154 case USB_PORT_FEAT_LINK_STATE: 1155 temp = readl(port_array[wIndex]); 1156 1157 /* Disable port */ 1158 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1159 xhci_dbg(xhci, "Disable port %d\n", wIndex); 1160 temp = xhci_port_state_to_neutral(temp); 1161 /* 1162 * Clear all change bits, so that we get a new 1163 * connection event. 1164 */ 1165 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 1166 PORT_OCC | PORT_RC | PORT_PLC | 1167 PORT_CEC; 1168 writel(temp | PORT_PE, port_array[wIndex]); 1169 temp = readl(port_array[wIndex]); 1170 break; 1171 } 1172 1173 /* Put link in RxDetect (enable port) */ 1174 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1175 xhci_dbg(xhci, "Enable port %d\n", wIndex); 1176 xhci_set_link_state(xhci, port_array, wIndex, 1177 link_state); 1178 temp = readl(port_array[wIndex]); 1179 break; 1180 } 1181 1182 /* 1183 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1184 * root hub port's transition to compliance mode upon 1185 * detecting LFPS timeout may be controlled by an 1186 * Compliance Transition Enabled (CTE) flag (not 1187 * software visible). This flag is set by writing 0xA 1188 * to PORTSC PLS field which will allow transition to 1189 * compliance mode the next time LFPS timeout is 1190 * encountered. A warm reset will clear it. 1191 * 1192 * The CTE flag is only supported if the HCCPARAMS2 CTC 1193 * flag is set, otherwise, the compliance substate is 1194 * automatically entered as on 1.0 and prior. 1195 */ 1196 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1197 if (!HCC2_CTC(xhci->hcc_params2)) { 1198 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1199 break; 1200 } 1201 1202 if ((temp & PORT_CONNECT)) { 1203 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1204 goto error; 1205 } 1206 1207 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n", 1208 wIndex); 1209 xhci_set_link_state(xhci, port_array, wIndex, 1210 link_state); 1211 temp = readl(port_array[wIndex]); 1212 break; 1213 } 1214 1215 /* Software should not attempt to set 1216 * port link state above '3' (U3) and the port 1217 * must be enabled. 1218 */ 1219 if ((temp & PORT_PE) == 0 || 1220 (link_state > USB_SS_PORT_LS_U3)) { 1221 xhci_warn(xhci, "Cannot set link state.\n"); 1222 goto error; 1223 } 1224 1225 if (link_state == USB_SS_PORT_LS_U3) { 1226 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1227 wIndex + 1); 1228 if (slot_id) { 1229 /* unlock to execute stop endpoint 1230 * commands */ 1231 spin_unlock_irqrestore(&xhci->lock, 1232 flags); 1233 xhci_stop_device(xhci, slot_id, 1); 1234 spin_lock_irqsave(&xhci->lock, flags); 1235 } 1236 } 1237 1238 xhci_set_link_state(xhci, port_array, wIndex, 1239 link_state); 1240 1241 spin_unlock_irqrestore(&xhci->lock, flags); 1242 msleep(20); /* wait device to enter */ 1243 spin_lock_irqsave(&xhci->lock, flags); 1244 1245 temp = readl(port_array[wIndex]); 1246 if (link_state == USB_SS_PORT_LS_U3) 1247 bus_state->suspended_ports |= 1 << wIndex; 1248 break; 1249 case USB_PORT_FEAT_POWER: 1250 /* 1251 * Turn on ports, even if there isn't per-port switching. 1252 * HC will report connect events even before this is set. 1253 * However, hub_wq will ignore the roothub events until 1254 * the roothub is registered. 1255 */ 1256 xhci_set_port_power(xhci, hcd, wIndex, true, &flags); 1257 break; 1258 case USB_PORT_FEAT_RESET: 1259 temp = (temp | PORT_RESET); 1260 writel(temp, port_array[wIndex]); 1261 1262 temp = readl(port_array[wIndex]); 1263 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 1264 break; 1265 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1266 xhci_set_remote_wake_mask(xhci, port_array, 1267 wIndex, wake_mask); 1268 temp = readl(port_array[wIndex]); 1269 xhci_dbg(xhci, "set port remote wake mask, " 1270 "actual port %d status = 0x%x\n", 1271 wIndex, temp); 1272 break; 1273 case USB_PORT_FEAT_BH_PORT_RESET: 1274 temp |= PORT_WR; 1275 writel(temp, port_array[wIndex]); 1276 1277 temp = readl(port_array[wIndex]); 1278 break; 1279 case USB_PORT_FEAT_U1_TIMEOUT: 1280 if (hcd->speed < HCD_USB3) 1281 goto error; 1282 temp = readl(port_array[wIndex] + PORTPMSC); 1283 temp &= ~PORT_U1_TIMEOUT_MASK; 1284 temp |= PORT_U1_TIMEOUT(timeout); 1285 writel(temp, port_array[wIndex] + PORTPMSC); 1286 break; 1287 case USB_PORT_FEAT_U2_TIMEOUT: 1288 if (hcd->speed < HCD_USB3) 1289 goto error; 1290 temp = readl(port_array[wIndex] + PORTPMSC); 1291 temp &= ~PORT_U2_TIMEOUT_MASK; 1292 temp |= PORT_U2_TIMEOUT(timeout); 1293 writel(temp, port_array[wIndex] + PORTPMSC); 1294 break; 1295 case USB_PORT_FEAT_TEST: 1296 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1297 if (hcd->speed != HCD_USB2) 1298 goto error; 1299 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) 1300 goto error; 1301 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, 1302 &flags); 1303 break; 1304 default: 1305 goto error; 1306 } 1307 /* unblock any posted writes */ 1308 temp = readl(port_array[wIndex]); 1309 break; 1310 case ClearPortFeature: 1311 if (!wIndex || wIndex > max_ports) 1312 goto error; 1313 wIndex--; 1314 temp = readl(port_array[wIndex]); 1315 if (temp == ~(u32)0) { 1316 xhci_hc_died(xhci); 1317 retval = -ENODEV; 1318 break; 1319 } 1320 /* FIXME: What new port features do we need to support? */ 1321 temp = xhci_port_state_to_neutral(temp); 1322 switch (wValue) { 1323 case USB_PORT_FEAT_SUSPEND: 1324 temp = readl(port_array[wIndex]); 1325 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1326 xhci_dbg(xhci, "PORTSC %04x\n", temp); 1327 if (temp & PORT_RESET) 1328 goto error; 1329 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 1330 if ((temp & PORT_PE) == 0) 1331 goto error; 1332 1333 set_bit(wIndex, &bus_state->resuming_ports); 1334 xhci_set_link_state(xhci, port_array, wIndex, 1335 XDEV_RESUME); 1336 spin_unlock_irqrestore(&xhci->lock, flags); 1337 msleep(USB_RESUME_TIMEOUT); 1338 spin_lock_irqsave(&xhci->lock, flags); 1339 xhci_set_link_state(xhci, port_array, wIndex, 1340 XDEV_U0); 1341 clear_bit(wIndex, &bus_state->resuming_ports); 1342 } 1343 bus_state->port_c_suspend |= 1 << wIndex; 1344 1345 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1346 wIndex + 1); 1347 if (!slot_id) { 1348 xhci_dbg(xhci, "slot_id is zero\n"); 1349 goto error; 1350 } 1351 xhci_ring_device(xhci, slot_id); 1352 break; 1353 case USB_PORT_FEAT_C_SUSPEND: 1354 bus_state->port_c_suspend &= ~(1 << wIndex); 1355 case USB_PORT_FEAT_C_RESET: 1356 case USB_PORT_FEAT_C_BH_PORT_RESET: 1357 case USB_PORT_FEAT_C_CONNECTION: 1358 case USB_PORT_FEAT_C_OVER_CURRENT: 1359 case USB_PORT_FEAT_C_ENABLE: 1360 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1361 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1362 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1363 port_array[wIndex], temp); 1364 break; 1365 case USB_PORT_FEAT_ENABLE: 1366 xhci_disable_port(hcd, xhci, wIndex, 1367 port_array[wIndex], temp); 1368 break; 1369 case USB_PORT_FEAT_POWER: 1370 xhci_set_port_power(xhci, hcd, wIndex, false, &flags); 1371 break; 1372 case USB_PORT_FEAT_TEST: 1373 retval = xhci_exit_test_mode(xhci); 1374 break; 1375 default: 1376 goto error; 1377 } 1378 break; 1379 default: 1380 error: 1381 /* "stall" on error */ 1382 retval = -EPIPE; 1383 } 1384 spin_unlock_irqrestore(&xhci->lock, flags); 1385 return retval; 1386 } 1387 1388 /* 1389 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1390 * Ports are 0-indexed from the HCD point of view, 1391 * and 1-indexed from the USB core pointer of view. 1392 * 1393 * Note that the status change bits will be cleared as soon as a port status 1394 * change event is generated, so we use the saved status from that event. 1395 */ 1396 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1397 { 1398 unsigned long flags; 1399 u32 temp, status; 1400 u32 mask; 1401 int i, retval; 1402 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1403 int max_ports; 1404 __le32 __iomem **port_array; 1405 struct xhci_bus_state *bus_state; 1406 bool reset_change = false; 1407 1408 max_ports = xhci_get_ports(hcd, &port_array); 1409 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1410 1411 /* Initial status is no changes */ 1412 retval = (max_ports + 8) / 8; 1413 memset(buf, 0, retval); 1414 1415 /* 1416 * Inform the usbcore about resume-in-progress by returning 1417 * a non-zero value even if there are no status changes. 1418 */ 1419 status = bus_state->resuming_ports; 1420 1421 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1422 1423 spin_lock_irqsave(&xhci->lock, flags); 1424 /* For each port, did anything change? If so, set that bit in buf. */ 1425 for (i = 0; i < max_ports; i++) { 1426 temp = readl(port_array[i]); 1427 if (temp == ~(u32)0) { 1428 xhci_hc_died(xhci); 1429 retval = -ENODEV; 1430 break; 1431 } 1432 if ((temp & mask) != 0 || 1433 (bus_state->port_c_suspend & 1 << i) || 1434 (bus_state->resume_done[i] && time_after_eq( 1435 jiffies, bus_state->resume_done[i]))) { 1436 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1437 status = 1; 1438 } 1439 if ((temp & PORT_RC)) 1440 reset_change = true; 1441 } 1442 if (!status && !reset_change) { 1443 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); 1444 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1445 } 1446 spin_unlock_irqrestore(&xhci->lock, flags); 1447 return status ? retval : 0; 1448 } 1449 1450 #ifdef CONFIG_PM 1451 1452 int xhci_bus_suspend(struct usb_hcd *hcd) 1453 { 1454 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1455 int max_ports, port_index; 1456 __le32 __iomem **port_array; 1457 struct xhci_bus_state *bus_state; 1458 unsigned long flags; 1459 1460 max_ports = xhci_get_ports(hcd, &port_array); 1461 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1462 1463 spin_lock_irqsave(&xhci->lock, flags); 1464 1465 if (hcd->self.root_hub->do_remote_wakeup) { 1466 if (bus_state->resuming_ports || /* USB2 */ 1467 bus_state->port_remote_wakeup) { /* USB3 */ 1468 spin_unlock_irqrestore(&xhci->lock, flags); 1469 xhci_dbg(xhci, "suspend failed because a port is resuming\n"); 1470 return -EBUSY; 1471 } 1472 } 1473 1474 port_index = max_ports; 1475 bus_state->bus_suspended = 0; 1476 while (port_index--) { 1477 /* suspend the port if the port is not suspended */ 1478 u32 t1, t2; 1479 int slot_id; 1480 1481 t1 = readl(port_array[port_index]); 1482 t2 = xhci_port_state_to_neutral(t1); 1483 1484 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 1485 xhci_dbg(xhci, "port %d not suspended\n", port_index); 1486 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 1487 port_index + 1); 1488 if (slot_id) { 1489 spin_unlock_irqrestore(&xhci->lock, flags); 1490 xhci_stop_device(xhci, slot_id, 1); 1491 spin_lock_irqsave(&xhci->lock, flags); 1492 } 1493 t2 &= ~PORT_PLS_MASK; 1494 t2 |= PORT_LINK_STROBE | XDEV_U3; 1495 set_bit(port_index, &bus_state->bus_suspended); 1496 } 1497 /* USB core sets remote wake mask for USB 3.0 hubs, 1498 * including the USB 3.0 roothub, but only if CONFIG_PM 1499 * is enabled, so also enable remote wake here. 1500 */ 1501 if (hcd->self.root_hub->do_remote_wakeup) { 1502 if (t1 & PORT_CONNECT) { 1503 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1504 t2 &= ~PORT_WKCONN_E; 1505 } else { 1506 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1507 t2 &= ~PORT_WKDISC_E; 1508 } 1509 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1510 (hcd->speed < HCD_USB3)) 1511 t2 &= ~PORT_WAKE_BITS; 1512 } else 1513 t2 &= ~PORT_WAKE_BITS; 1514 1515 t1 = xhci_port_state_to_neutral(t1); 1516 if (t1 != t2) 1517 writel(t2, port_array[port_index]); 1518 } 1519 hcd->state = HC_STATE_SUSPENDED; 1520 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1521 spin_unlock_irqrestore(&xhci->lock, flags); 1522 return 0; 1523 } 1524 1525 /* 1526 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1527 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1528 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1529 */ 1530 static bool xhci_port_missing_cas_quirk(int port_index, 1531 __le32 __iomem **port_array) 1532 { 1533 u32 portsc; 1534 1535 portsc = readl(port_array[port_index]); 1536 1537 /* if any of these are set we are not stuck */ 1538 if (portsc & (PORT_CONNECT | PORT_CAS)) 1539 return false; 1540 1541 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1542 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1543 return false; 1544 1545 /* clear wakeup/change bits, and do a warm port reset */ 1546 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1547 portsc |= PORT_WR; 1548 writel(portsc, port_array[port_index]); 1549 /* flush write */ 1550 readl(port_array[port_index]); 1551 return true; 1552 } 1553 1554 int xhci_bus_resume(struct usb_hcd *hcd) 1555 { 1556 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1557 struct xhci_bus_state *bus_state; 1558 __le32 __iomem **port_array; 1559 unsigned long flags; 1560 int max_ports, port_index; 1561 int slot_id; 1562 int sret; 1563 u32 next_state; 1564 u32 temp, portsc; 1565 1566 max_ports = xhci_get_ports(hcd, &port_array); 1567 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1568 1569 if (time_before(jiffies, bus_state->next_statechange)) 1570 msleep(5); 1571 1572 spin_lock_irqsave(&xhci->lock, flags); 1573 if (!HCD_HW_ACCESSIBLE(hcd)) { 1574 spin_unlock_irqrestore(&xhci->lock, flags); 1575 return -ESHUTDOWN; 1576 } 1577 1578 /* delay the irqs */ 1579 temp = readl(&xhci->op_regs->command); 1580 temp &= ~CMD_EIE; 1581 writel(temp, &xhci->op_regs->command); 1582 1583 /* bus specific resume for ports we suspended at bus_suspend */ 1584 if (hcd->speed >= HCD_USB3) 1585 next_state = XDEV_U0; 1586 else 1587 next_state = XDEV_RESUME; 1588 1589 port_index = max_ports; 1590 while (port_index--) { 1591 portsc = readl(port_array[port_index]); 1592 1593 /* warm reset CAS limited ports stuck in polling/compliance */ 1594 if ((xhci->quirks & XHCI_MISSING_CAS) && 1595 (hcd->speed >= HCD_USB3) && 1596 xhci_port_missing_cas_quirk(port_index, port_array)) { 1597 xhci_dbg(xhci, "reset stuck port %d\n", port_index); 1598 clear_bit(port_index, &bus_state->bus_suspended); 1599 continue; 1600 } 1601 /* resume if we suspended the link, and it is still suspended */ 1602 if (test_bit(port_index, &bus_state->bus_suspended)) 1603 switch (portsc & PORT_PLS_MASK) { 1604 case XDEV_U3: 1605 portsc = xhci_port_state_to_neutral(portsc); 1606 portsc &= ~PORT_PLS_MASK; 1607 portsc |= PORT_LINK_STROBE | next_state; 1608 break; 1609 case XDEV_RESUME: 1610 /* resume already initiated */ 1611 break; 1612 default: 1613 /* not in a resumeable state, ignore it */ 1614 clear_bit(port_index, 1615 &bus_state->bus_suspended); 1616 break; 1617 } 1618 /* disable wake for all ports, write new link state if needed */ 1619 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1620 writel(portsc, port_array[port_index]); 1621 } 1622 1623 /* USB2 specific resume signaling delay and U0 link state transition */ 1624 if (hcd->speed < HCD_USB3) { 1625 if (bus_state->bus_suspended) { 1626 spin_unlock_irqrestore(&xhci->lock, flags); 1627 msleep(USB_RESUME_TIMEOUT); 1628 spin_lock_irqsave(&xhci->lock, flags); 1629 } 1630 for_each_set_bit(port_index, &bus_state->bus_suspended, 1631 BITS_PER_LONG) { 1632 /* Clear PLC to poll it later for U0 transition */ 1633 xhci_test_and_clear_bit(xhci, port_array, port_index, 1634 PORT_PLC); 1635 xhci_set_link_state(xhci, port_array, port_index, 1636 XDEV_U0); 1637 } 1638 } 1639 1640 /* poll for U0 link state complete, both USB2 and USB3 */ 1641 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1642 sret = xhci_handshake(port_array[port_index], PORT_PLC, 1643 PORT_PLC, 10 * 1000); 1644 if (sret) { 1645 xhci_warn(xhci, "port %d resume PLC timeout\n", 1646 port_index); 1647 continue; 1648 } 1649 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); 1650 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); 1651 if (slot_id) 1652 xhci_ring_device(xhci, slot_id); 1653 } 1654 (void) readl(&xhci->op_regs->command); 1655 1656 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1657 /* re-enable irqs */ 1658 temp = readl(&xhci->op_regs->command); 1659 temp |= CMD_EIE; 1660 writel(temp, &xhci->op_regs->command); 1661 temp = readl(&xhci->op_regs->command); 1662 1663 spin_unlock_irqrestore(&xhci->lock, flags); 1664 return 0; 1665 } 1666 1667 #endif /* CONFIG_PM */ 1668