1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 12 #include <linux/slab.h> 13 #include <linux/unaligned.h> 14 #include <linux/bitfield.h> 15 #include <linux/pci.h> 16 17 #include "xhci.h" 18 #include "xhci-trace.h" 19 20 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 21 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 22 PORT_RC | PORT_PLC | PORT_PE) 23 24 /* Default sublink speed attribute of each lane */ 25 static u32 ssp_cap_default_ssa[] = { 26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 34 }; 35 36 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, 37 u16 wLength) 38 { 39 struct usb_bos_descriptor *bos; 40 struct usb_ss_cap_descriptor *ss_cap; 41 struct usb_ssp_cap_descriptor *ssp_cap; 42 struct xhci_port_cap *port_cap = NULL; 43 u16 bcdUSB; 44 u32 reg; 45 u32 min_rate = 0; 46 u8 min_ssid; 47 u8 ssac; 48 u8 ssic; 49 int offset; 50 int i; 51 52 /* BOS descriptor */ 53 bos = (struct usb_bos_descriptor *)buf; 54 bos->bLength = USB_DT_BOS_SIZE; 55 bos->bDescriptorType = USB_DT_BOS; 56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 57 USB_DT_USB_SS_CAP_SIZE); 58 bos->bNumDeviceCaps = 1; 59 60 /* Create the descriptor for port with the highest revision */ 61 for (i = 0; i < xhci->num_port_caps; i++) { 62 u8 major = xhci->port_caps[i].maj_rev; 63 u8 minor = xhci->port_caps[i].min_rev; 64 u16 rev = (major << 8) | minor; 65 66 if (i == 0 || bcdUSB < rev) { 67 bcdUSB = rev; 68 port_cap = &xhci->port_caps[i]; 69 } 70 } 71 72 if (bcdUSB >= 0x0310) { 73 if (port_cap->psi_count) { 74 u8 num_sym_ssa = 0; 75 76 for (i = 0; i < port_cap->psi_count; i++) { 77 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM) 78 num_sym_ssa++; 79 } 80 81 ssac = port_cap->psi_count + num_sym_ssa - 1; 82 ssic = port_cap->psi_uid_count - 1; 83 } else { 84 if (bcdUSB >= 0x0320) 85 ssac = 7; 86 else 87 ssac = 3; 88 89 ssic = (ssac + 1) / 2 - 1; 90 } 91 92 bos->bNumDeviceCaps++; 93 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + 94 USB_DT_USB_SS_CAP_SIZE + 95 USB_DT_USB_SSP_CAP_SIZE(ssac)); 96 } 97 98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) 99 return wLength; 100 101 /* SuperSpeed USB Device Capability */ 102 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE]; 103 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE; 104 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 105 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE; 106 ss_cap->bmAttributes = 0; /* set later */ 107 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION); 108 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 109 ss_cap->bU1devExitLat = 0; /* set later */ 110 ss_cap->bU2DevExitLat = 0; /* set later */ 111 112 reg = readl(&xhci->cap_regs->hcc_params); 113 if (HCC_LTC(reg)) 114 ss_cap->bmAttributes |= USB_LTM_SUPPORT; 115 116 if ((xhci->quirks & XHCI_LPM_SUPPORT)) { 117 reg = readl(&xhci->cap_regs->hcs_params3); 118 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg); 119 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg)); 120 } 121 122 if (wLength < le16_to_cpu(bos->wTotalLength)) 123 return wLength; 124 125 if (bcdUSB < 0x0310) 126 return le16_to_cpu(bos->wTotalLength); 127 128 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE + 129 USB_DT_USB_SS_CAP_SIZE]; 130 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac); 131 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 132 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE; 133 ssp_cap->bReserved = 0; 134 ssp_cap->wReserved = 0; 135 ssp_cap->bmAttributes = 136 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) | 137 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic)); 138 139 if (!port_cap->psi_count) { 140 for (i = 0; i < ssac + 1; i++) 141 ssp_cap->bmSublinkSpeedAttr[i] = 142 cpu_to_le32(ssp_cap_default_ssa[i]); 143 144 min_ssid = 4; 145 goto out; 146 } 147 148 offset = 0; 149 for (i = 0; i < port_cap->psi_count; i++) { 150 u32 psi; 151 u32 attr; 152 u8 ssid; 153 u8 lp; 154 u8 lse; 155 u8 psie; 156 u16 lane_mantissa; 157 u16 psim; 158 u16 plt; 159 160 psi = port_cap->psi[i]; 161 ssid = XHCI_EXT_PORT_PSIV(psi); 162 lp = XHCI_EXT_PORT_LP(psi); 163 psie = XHCI_EXT_PORT_PSIE(psi); 164 psim = XHCI_EXT_PORT_PSIM(psi); 165 plt = psi & PLT_MASK; 166 167 lse = psie; 168 lane_mantissa = psim; 169 170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ 171 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++) 172 psim /= 1000; 173 174 if (!min_rate || psim < min_rate) { 175 min_ssid = ssid; 176 min_rate = psim; 177 } 178 179 /* Some host controllers don't set the link protocol for SSP */ 180 if (psim >= 10) 181 lp = USB_SSP_SUBLINK_SPEED_LP_SSP; 182 183 /* 184 * PSIM and PSIE represent the total speed of PSI. The BOS 185 * descriptor SSP sublink speed attribute lane mantissa 186 * describes the lane speed. E.g. PSIM and PSIE for gen2x2 187 * is 20Gbps, but the BOS descriptor lane speed mantissa is 188 * 10Gbps. Check and modify the mantissa value to match the 189 * lane speed. 190 */ 191 if (bcdUSB == 0x0320 && plt == PLT_SYM) { 192 /* 193 * The PSI dword for gen1x2 and gen2x1 share the same 194 * values. But the lane speed for gen1x2 is 5Gbps while 195 * gen2x1 is 10Gbps. If the previous PSI dword SSID is 196 * 5 and the PSIE and PSIM match with SSID 6, let's 197 * assume that the controller follows the default speed 198 * id with SSID 6 for gen1x2. 199 */ 200 if (ssid == 6 && psie == 3 && psim == 10 && i) { 201 u32 prev = port_cap->psi[i - 1]; 202 203 if ((prev & PLT_MASK) == PLT_SYM && 204 XHCI_EXT_PORT_PSIV(prev) == 5 && 205 XHCI_EXT_PORT_PSIE(prev) == 3 && 206 XHCI_EXT_PORT_PSIM(prev) == 10) { 207 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 208 lane_mantissa = 5; 209 } 210 } 211 212 if (psie == 3 && psim > 10) { 213 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS; 214 lane_mantissa = 10; 215 } 216 } 217 218 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) | 219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) | 220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) | 221 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa)); 222 223 switch (plt) { 224 case PLT_SYM: 225 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 226 USB_SSP_SUBLINK_SPEED_ST_SYM_RX); 227 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 228 229 attr &= ~USB_SSP_SUBLINK_SPEED_ST; 230 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 231 USB_SSP_SUBLINK_SPEED_ST_SYM_TX); 232 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 233 break; 234 case PLT_ASYM_RX: 235 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 236 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX); 237 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 238 break; 239 case PLT_ASYM_TX: 240 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, 241 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX); 242 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr); 243 break; 244 } 245 } 246 out: 247 ssp_cap->wFunctionalitySupport = 248 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 249 min_ssid) | 250 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) | 251 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1)); 252 253 return le16_to_cpu(bos->wTotalLength); 254 } 255 256 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 257 struct usb_hub_descriptor *desc, int ports) 258 { 259 u16 temp; 260 261 desc->bHubContrCurrent = 0; 262 263 desc->bNbrPorts = ports; 264 temp = 0; 265 /* Bits 1:0 - support per-port power switching, or power always on */ 266 if (HCC_PPC(xhci->hcc_params)) 267 temp |= HUB_CHAR_INDV_PORT_LPSM; 268 else 269 temp |= HUB_CHAR_NO_LPSM; 270 /* Bit 2 - root hubs are not part of a compound device */ 271 /* Bits 4:3 - individual port over current protection */ 272 temp |= HUB_CHAR_INDV_PORT_OCPM; 273 /* Bits 6:5 - no TTs in root ports */ 274 /* Bit 7 - no port indicators */ 275 desc->wHubCharacteristics = cpu_to_le16(temp); 276 } 277 278 /* Fill in the USB 2.0 roothub descriptor */ 279 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 280 struct usb_hub_descriptor *desc) 281 { 282 int ports; 283 u16 temp; 284 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 285 u32 portsc; 286 unsigned int i; 287 struct xhci_hub *rhub; 288 289 rhub = &xhci->usb2_rhub; 290 ports = rhub->num_ports; 291 xhci_common_hub_descriptor(xhci, desc, ports); 292 desc->bDescriptorType = USB_DT_HUB; 293 temp = 1 + (ports / 8); 294 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 295 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */ 296 297 /* The Device Removable bits are reported on a byte granularity. 298 * If the port doesn't exist within that byte, the bit is set to 0. 299 */ 300 memset(port_removable, 0, sizeof(port_removable)); 301 for (i = 0; i < ports; i++) { 302 portsc = readl(rhub->ports[i]->addr); 303 /* If a device is removable, PORTSC reports a 0, same as in the 304 * hub descriptor DeviceRemovable bits. 305 */ 306 if (portsc & PORT_DEV_REMOVE) 307 /* This math is hairy because bit 0 of DeviceRemovable 308 * is reserved, and bit 1 is for port 1, etc. 309 */ 310 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 311 } 312 313 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 314 * ports on it. The USB 2.0 specification says that there are two 315 * variable length fields at the end of the hub descriptor: 316 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 317 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 318 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 319 * 0xFF, so we initialize the both arrays (DeviceRemovable and 320 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 321 * set of ports that actually exist. 322 */ 323 memset(desc->u.hs.DeviceRemovable, 0xff, 324 sizeof(desc->u.hs.DeviceRemovable)); 325 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 326 sizeof(desc->u.hs.PortPwrCtrlMask)); 327 328 for (i = 0; i < (ports + 1 + 7) / 8; i++) 329 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 330 sizeof(__u8)); 331 } 332 333 /* Fill in the USB 3.0 roothub descriptor */ 334 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 struct usb_hub_descriptor *desc) 336 { 337 int ports; 338 u16 port_removable; 339 u32 portsc; 340 unsigned int i; 341 struct xhci_hub *rhub; 342 343 rhub = &xhci->usb3_rhub; 344 ports = rhub->num_ports; 345 xhci_common_hub_descriptor(xhci, desc, ports); 346 desc->bDescriptorType = USB_DT_SS_HUB; 347 desc->bDescLength = USB_DT_SS_HUB_SIZE; 348 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */ 349 350 /* header decode latency should be zero for roothubs, 351 * see section 4.23.5.2. 352 */ 353 desc->u.ss.bHubHdrDecLat = 0; 354 desc->u.ss.wHubDelay = 0; 355 356 port_removable = 0; 357 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 358 for (i = 0; i < ports; i++) { 359 portsc = readl(rhub->ports[i]->addr); 360 if (portsc & PORT_DEV_REMOVE) 361 port_removable |= 1 << (i + 1); 362 } 363 364 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); 365 } 366 367 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 368 struct usb_hub_descriptor *desc) 369 { 370 371 if (hcd->speed >= HCD_USB3) 372 xhci_usb3_hub_descriptor(hcd, xhci, desc); 373 else 374 xhci_usb2_hub_descriptor(hcd, xhci, desc); 375 376 } 377 378 static unsigned int xhci_port_speed(unsigned int port_status) 379 { 380 if (DEV_LOWSPEED(port_status)) 381 return USB_PORT_STAT_LOW_SPEED; 382 if (DEV_HIGHSPEED(port_status)) 383 return USB_PORT_STAT_HIGH_SPEED; 384 /* 385 * FIXME: Yes, we should check for full speed, but the core uses that as 386 * a default in portspeed() in usb/core/hub.c (which is the only place 387 * USB_PORT_STAT_*_SPEED is used). 388 */ 389 return 0; 390 } 391 392 /* 393 * These bits are Read Only (RO) and should be saved and written to the 394 * registers: 0, 3, 10:13, 30 395 * connect status, over-current status, port speed, and device removable. 396 * connect status and port speed are also sticky - meaning they're in 397 * the AUX well and they aren't changed by a hot, warm, or cold reset. 398 */ 399 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 400 /* 401 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 402 * bits 5:8, 9, 14:15, 25:27 403 * link state, port power, port indicator state, "wake on" enable state 404 */ 405 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 406 /* 407 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 408 * bit 4 (port reset) 409 */ 410 #define XHCI_PORT_RW1S ((1<<4)) 411 /* 412 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 413 * bits 1, 17, 18, 19, 20, 21, 22, 23 414 * port enable/disable, and 415 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 416 * over-current, reset, link state, and L1 change 417 */ 418 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 419 /* 420 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 421 * latched in 422 */ 423 #define XHCI_PORT_RW ((1<<16)) 424 /* 425 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 426 * bits 2, 24, 28:31 427 */ 428 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 429 430 /** 431 * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable 432 * @state: u32 port value read from portsc register to be cleanup up 433 * 434 * Given a port state, this function returns a value that would result in the 435 * port being in the same state, if the value was written to the port status 436 * control register. 437 * Save Read Only (RO) bits and save read/write bits where 438 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 439 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 440 * 441 * Return: u32 value that can be written back to portsc register without 442 * changing port state. 443 */ 444 445 u32 xhci_port_state_to_neutral(u32 state) 446 { 447 /* Save read-only status and port state */ 448 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 449 } 450 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral); 451 452 /* 453 * Stop device 454 * It issues stop endpoint command for EP 0 to 30. And wait the last command 455 * to complete. 456 * suspend will set to 1, if suspend bit need to set in command. 457 */ 458 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 459 { 460 struct xhci_virt_device *virt_dev; 461 struct xhci_command *cmd; 462 unsigned long flags; 463 int ret; 464 int i; 465 466 ret = 0; 467 virt_dev = xhci->devs[slot_id]; 468 if (!virt_dev) 469 return -ENODEV; 470 471 trace_xhci_stop_device(virt_dev); 472 473 cmd = xhci_alloc_command(xhci, true, GFP_NOIO); 474 if (!cmd) 475 return -ENOMEM; 476 477 spin_lock_irqsave(&xhci->lock, flags); 478 for (i = LAST_EP_INDEX; i > 0; i--) { 479 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { 480 struct xhci_ep_ctx *ep_ctx; 481 struct xhci_command *command; 482 483 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); 484 485 /* Check ep is running, required by AMD SNPS 3.1 xHC */ 486 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) 487 continue; 488 489 command = xhci_alloc_command(xhci, false, GFP_NOWAIT); 490 if (!command) { 491 spin_unlock_irqrestore(&xhci->lock, flags); 492 ret = -ENOMEM; 493 goto cmd_cleanup; 494 } 495 496 ret = xhci_queue_stop_endpoint(xhci, command, slot_id, 497 i, suspend); 498 if (ret) { 499 spin_unlock_irqrestore(&xhci->lock, flags); 500 xhci_free_command(xhci, command); 501 goto cmd_cleanup; 502 } 503 } 504 } 505 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); 506 if (ret) { 507 spin_unlock_irqrestore(&xhci->lock, flags); 508 goto cmd_cleanup; 509 } 510 511 xhci_ring_cmd_db(xhci); 512 spin_unlock_irqrestore(&xhci->lock, flags); 513 514 /* Wait for last stop endpoint command to finish */ 515 wait_for_completion(cmd->completion); 516 517 if (cmd->status == COMP_COMMAND_ABORTED || 518 cmd->status == COMP_COMMAND_RING_STOPPED) { 519 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); 520 ret = -ETIME; 521 } 522 523 cmd_cleanup: 524 xhci_free_command(xhci, cmd); 525 return ret; 526 } 527 528 /* 529 * Ring device, it rings the all doorbells unconditionally. 530 */ 531 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 532 { 533 int i, s; 534 struct xhci_virt_ep *ep; 535 536 for (i = 0; i < LAST_EP_INDEX + 1; i++) { 537 ep = &xhci->devs[slot_id]->eps[i]; 538 539 if (ep->ep_state & EP_HAS_STREAMS) { 540 for (s = 1; s < ep->stream_info->num_streams; s++) 541 xhci_ring_ep_doorbell(xhci, slot_id, i, s); 542 } else if (ep->ring && ep->ring->dequeue) { 543 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 544 } 545 } 546 547 return; 548 } 549 550 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port) 551 { 552 struct usb_hcd *hcd; 553 u32 portsc; 554 555 hcd = port->rhub->hcd; 556 557 /* Don't allow the USB core to disable SuperSpeed ports. */ 558 if (hcd->speed >= HCD_USB3) { 559 xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n"); 560 return; 561 } 562 563 if (xhci->quirks & XHCI_BROKEN_PORT_PED) { 564 xhci_dbg(xhci, 565 "Broken Port Enabled/Disabled, ignoring port disable request.\n"); 566 return; 567 } 568 569 portsc = readl(port->addr); 570 portsc = xhci_port_state_to_neutral(portsc); 571 572 /* Write 1 to disable the port */ 573 writel(portsc | PORT_PE, port->addr); 574 575 portsc = readl(port->addr); 576 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", 577 hcd->self.busnum, port->hcd_portnum + 1, portsc); 578 } 579 580 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 581 u16 wIndex, __le32 __iomem *addr, u32 port_status) 582 { 583 char *port_change_bit; 584 u32 status; 585 586 switch (wValue) { 587 case USB_PORT_FEAT_C_RESET: 588 status = PORT_RC; 589 port_change_bit = "reset"; 590 break; 591 case USB_PORT_FEAT_C_BH_PORT_RESET: 592 status = PORT_WRC; 593 port_change_bit = "warm(BH) reset"; 594 break; 595 case USB_PORT_FEAT_C_CONNECTION: 596 status = PORT_CSC; 597 port_change_bit = "connect"; 598 break; 599 case USB_PORT_FEAT_C_OVER_CURRENT: 600 status = PORT_OCC; 601 port_change_bit = "over-current"; 602 break; 603 case USB_PORT_FEAT_C_ENABLE: 604 status = PORT_PEC; 605 port_change_bit = "enable/disable"; 606 break; 607 case USB_PORT_FEAT_C_SUSPEND: 608 status = PORT_PLC; 609 port_change_bit = "suspend/resume"; 610 break; 611 case USB_PORT_FEAT_C_PORT_LINK_STATE: 612 status = PORT_PLC; 613 port_change_bit = "link state"; 614 break; 615 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 616 status = PORT_CEC; 617 port_change_bit = "config error"; 618 break; 619 default: 620 /* Should never happen */ 621 return; 622 } 623 /* Change bits are all write 1 to clear */ 624 writel(port_status | status, addr); 625 port_status = readl(addr); 626 627 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", 628 wIndex + 1, port_change_bit, port_status); 629 } 630 631 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) 632 { 633 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 634 635 if (hcd->speed >= HCD_USB3) 636 return &xhci->usb3_rhub; 637 return &xhci->usb2_rhub; 638 } 639 640 /* 641 * xhci_set_port_power() must be called with xhci->lock held. 642 * It will release and re-aquire the lock while calling ACPI 643 * method. 644 */ 645 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port, 646 bool on, unsigned long *flags) 647 __must_hold(&xhci->lock) 648 { 649 struct usb_hcd *hcd; 650 u32 temp; 651 652 hcd = port->rhub->hcd; 653 temp = readl(port->addr); 654 655 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", 656 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); 657 658 temp = xhci_port_state_to_neutral(temp); 659 660 if (on) { 661 /* Power on */ 662 writel(temp | PORT_POWER, port->addr); 663 readl(port->addr); 664 } else { 665 /* Power off */ 666 writel(temp & ~PORT_POWER, port->addr); 667 } 668 669 spin_unlock_irqrestore(&xhci->lock, *flags); 670 temp = usb_acpi_power_manageable(hcd->self.root_hub, 671 port->hcd_portnum); 672 if (temp) 673 usb_acpi_set_power_state(hcd->self.root_hub, 674 port->hcd_portnum, on); 675 spin_lock_irqsave(&xhci->lock, *flags); 676 } 677 678 static void xhci_port_set_test_mode(struct xhci_hcd *xhci, 679 u16 test_mode, u16 wIndex) 680 { 681 u32 temp; 682 struct xhci_port *port; 683 684 /* xhci only supports test mode for usb2 ports */ 685 port = xhci->usb2_rhub.ports[wIndex]; 686 temp = readl(port->addr + PORTPMSC); 687 temp |= test_mode << PORT_TEST_MODE_SHIFT; 688 writel(temp, port->addr + PORTPMSC); 689 xhci->test_mode = test_mode; 690 if (test_mode == USB_TEST_FORCE_ENABLE) 691 xhci_start(xhci); 692 } 693 694 static int xhci_enter_test_mode(struct xhci_hcd *xhci, 695 u16 test_mode, u16 wIndex, unsigned long *flags) 696 __must_hold(&xhci->lock) 697 { 698 int i, retval; 699 700 /* Disable all Device Slots */ 701 xhci_dbg(xhci, "Disable all slots\n"); 702 spin_unlock_irqrestore(&xhci->lock, *flags); 703 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 704 if (!xhci->devs[i]) 705 continue; 706 707 retval = xhci_disable_slot(xhci, i); 708 xhci_free_virt_device(xhci, i); 709 if (retval) 710 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", 711 i, retval); 712 } 713 spin_lock_irqsave(&xhci->lock, *flags); 714 /* Put all ports to the Disable state by clear PP */ 715 xhci_dbg(xhci, "Disable all port (PP = 0)\n"); 716 /* Power off USB3 ports*/ 717 for (i = 0; i < xhci->usb3_rhub.num_ports; i++) 718 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags); 719 /* Power off USB2 ports*/ 720 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) 721 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags); 722 /* Stop the controller */ 723 xhci_dbg(xhci, "Stop controller\n"); 724 retval = xhci_halt(xhci); 725 if (retval) 726 return retval; 727 /* Disable runtime PM for test mode */ 728 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); 729 /* Set PORTPMSC.PTC field to enter selected test mode */ 730 /* Port is selected by wIndex. port_id = wIndex + 1 */ 731 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", 732 test_mode, wIndex + 1); 733 xhci_port_set_test_mode(xhci, test_mode, wIndex); 734 return retval; 735 } 736 737 static int xhci_exit_test_mode(struct xhci_hcd *xhci) 738 { 739 int retval; 740 741 if (!xhci->test_mode) { 742 xhci_err(xhci, "Not in test mode, do nothing.\n"); 743 return 0; 744 } 745 if (xhci->test_mode == USB_TEST_FORCE_ENABLE && 746 !(xhci->xhc_state & XHCI_STATE_HALTED)) { 747 retval = xhci_halt(xhci); 748 if (retval) 749 return retval; 750 } 751 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); 752 xhci->test_mode = 0; 753 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC); 754 } 755 756 /** 757 * xhci_port_is_tunneled() - Check if USB3 connection is tunneled over USB4 758 * @xhci: xhci host controller 759 * @port: USB3 port to be checked. 760 * 761 * Some hosts can detect if a USB3 connection is native USB3 or tunneled over 762 * USB4. Intel hosts expose this via vendor specific extended capability 206 763 * eSS PORT registers TUNEN (tunnel enabled) bit. 764 * 765 * A USB3 device must be connected to the port to detect the tunnel. 766 * 767 * Return: link tunnel mode enum, USB_LINK_UNKNOWN if host is incapable of 768 * detecting USB3 over USB4 tunnels. USB_LINK_NATIVE or USB_LINK_TUNNELED 769 * otherwise. 770 */ 771 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 772 struct xhci_port *port) 773 { 774 struct usb_hcd *hcd; 775 void __iomem *base; 776 u32 offset; 777 778 /* Don't try and probe this capability for non-Intel hosts */ 779 hcd = xhci_to_hcd(xhci); 780 if (!dev_is_pci(hcd->self.controller) || 781 to_pci_dev(hcd->self.controller)->vendor != PCI_VENDOR_ID_INTEL) 782 return USB_LINK_UNKNOWN; 783 784 base = &xhci->cap_regs->hc_capbase; 785 offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW); 786 787 if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) { 788 offset = XHCI_INTEL_SPR_ESS_PORT_OFFSET + port->hcd_portnum * 0x20; 789 790 if (readl(base + offset) & XHCI_INTEL_SPR_TUNEN) 791 return USB_LINK_TUNNELED; 792 else 793 return USB_LINK_NATIVE; 794 } 795 796 return USB_LINK_UNKNOWN; 797 } 798 799 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 800 u32 link_state) 801 { 802 u32 temp; 803 u32 portsc; 804 805 portsc = readl(port->addr); 806 temp = xhci_port_state_to_neutral(portsc); 807 temp &= ~PORT_PLS_MASK; 808 temp |= PORT_LINK_STROBE | link_state; 809 writel(temp, port->addr); 810 811 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", 812 port->rhub->hcd->self.busnum, port->hcd_portnum + 1, 813 portsc, temp); 814 } 815 816 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 817 struct xhci_port *port, u16 wake_mask) 818 { 819 u32 temp; 820 821 temp = readl(port->addr); 822 temp = xhci_port_state_to_neutral(temp); 823 824 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 825 temp |= PORT_WKCONN_E; 826 else 827 temp &= ~PORT_WKCONN_E; 828 829 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 830 temp |= PORT_WKDISC_E; 831 else 832 temp &= ~PORT_WKDISC_E; 833 834 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 835 temp |= PORT_WKOC_E; 836 else 837 temp &= ~PORT_WKOC_E; 838 839 writel(temp, port->addr); 840 } 841 842 /* Test and clear port RWC bit */ 843 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 844 u32 port_bit) 845 { 846 u32 temp; 847 848 temp = readl(port->addr); 849 if (temp & port_bit) { 850 temp = xhci_port_state_to_neutral(temp); 851 temp |= port_bit; 852 writel(temp, port->addr); 853 } 854 } 855 856 /* Updates Link Status for super Speed port */ 857 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 858 u32 *status, u32 status_reg) 859 { 860 u32 pls = status_reg & PORT_PLS_MASK; 861 862 /* When the CAS bit is set then warm reset 863 * should be performed on port 864 */ 865 if (status_reg & PORT_CAS) { 866 /* The CAS bit can be set while the port is 867 * in any link state. 868 * Only roothubs have CAS bit, so we 869 * pretend to be in compliance mode 870 * unless we're already in compliance 871 * or the inactive state. 872 */ 873 if (pls != USB_SS_PORT_LS_COMP_MOD && 874 pls != USB_SS_PORT_LS_SS_INACTIVE) { 875 pls = USB_SS_PORT_LS_COMP_MOD; 876 } 877 /* Return also connection bit - 878 * hub state machine resets port 879 * when this bit is set. 880 */ 881 pls |= USB_PORT_STAT_CONNECTION; 882 } else { 883 /* 884 * Resume state is an xHCI internal state. Do not report it to 885 * usb core, instead, pretend to be U3, thus usb core knows 886 * it's not ready for transfer. 887 */ 888 if (pls == XDEV_RESUME) { 889 *status |= USB_SS_PORT_LS_U3; 890 return; 891 } 892 893 /* 894 * If CAS bit isn't set but the Port is already at 895 * Compliance Mode, fake a connection so the USB core 896 * notices the Compliance state and resets the port. 897 * This resolves an issue generated by the SN65LVPE502CP 898 * in which sometimes the port enters compliance mode 899 * caused by a delay on the host-device negotiation. 900 */ 901 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 902 (pls == USB_SS_PORT_LS_COMP_MOD)) 903 pls |= USB_PORT_STAT_CONNECTION; 904 } 905 906 /* update status field */ 907 *status |= pls; 908 } 909 910 /* 911 * Function for Compliance Mode Quirk. 912 * 913 * This Function verifies if all xhc USB3 ports have entered U0, if so, 914 * the compliance mode timer is deleted. A port won't enter 915 * compliance mode if it has previously entered U0. 916 */ 917 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, 918 u16 wIndex) 919 { 920 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); 921 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); 922 923 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) 924 return; 925 926 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { 927 xhci->port_status_u0 |= 1 << wIndex; 928 if (xhci->port_status_u0 == all_ports_seen_u0) { 929 del_timer_sync(&xhci->comp_mode_recovery_timer); 930 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 931 "All USB3 ports have entered U0 already!"); 932 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 933 "Compliance Mode Recovery Timer Deleted."); 934 } 935 } 936 } 937 938 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, 939 u32 portsc, 940 unsigned long *flags) 941 { 942 struct xhci_bus_state *bus_state; 943 struct xhci_hcd *xhci; 944 struct usb_hcd *hcd; 945 u32 wIndex; 946 947 hcd = port->rhub->hcd; 948 bus_state = &port->rhub->bus_state; 949 xhci = hcd_to_xhci(hcd); 950 wIndex = port->hcd_portnum; 951 952 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { 953 return -EINVAL; 954 } 955 /* did port event handler already start resume timing? */ 956 if (!port->resume_timestamp) { 957 /* If not, maybe we are in a host initiated resume? */ 958 if (test_bit(wIndex, &bus_state->resuming_ports)) { 959 /* Host initiated resume doesn't time the resume 960 * signalling using resume_done[]. 961 * It manually sets RESUME state, sleeps 20ms 962 * and sets U0 state. This should probably be 963 * changed, but not right now. 964 */ 965 } else { 966 /* port resume was discovered now and here, 967 * start resume timing 968 */ 969 unsigned long timeout = jiffies + 970 msecs_to_jiffies(USB_RESUME_TIMEOUT); 971 972 set_bit(wIndex, &bus_state->resuming_ports); 973 port->resume_timestamp = timeout; 974 mod_timer(&hcd->rh_timer, timeout); 975 usb_hcd_start_port_resume(&hcd->self, wIndex); 976 } 977 /* Has resume been signalled for USB_RESUME_TIME yet? */ 978 } else if (time_after_eq(jiffies, port->resume_timestamp)) { 979 int time_left; 980 981 xhci_dbg(xhci, "resume USB2 port %d-%d\n", 982 hcd->self.busnum, wIndex + 1); 983 984 port->resume_timestamp = 0; 985 clear_bit(wIndex, &bus_state->resuming_ports); 986 987 reinit_completion(&port->rexit_done); 988 port->rexit_active = true; 989 990 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 991 xhci_set_link_state(xhci, port, XDEV_U0); 992 993 spin_unlock_irqrestore(&xhci->lock, *flags); 994 time_left = wait_for_completion_timeout( 995 &port->rexit_done, 996 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); 997 spin_lock_irqsave(&xhci->lock, *flags); 998 999 if (time_left) { 1000 if (!port->slot_id) { 1001 xhci_dbg(xhci, "slot_id is zero\n"); 1002 return -ENODEV; 1003 } 1004 xhci_ring_device(xhci, port->slot_id); 1005 } else { 1006 int port_status = readl(port->addr); 1007 1008 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", 1009 hcd->self.busnum, wIndex + 1, port_status); 1010 /* 1011 * keep rexit_active set if U0 transition failed so we 1012 * know to report PORT_STAT_SUSPEND status back to 1013 * usbcore. It will be cleared later once the port is 1014 * out of RESUME/U3 state 1015 */ 1016 } 1017 1018 usb_hcd_end_port_resume(&hcd->self, wIndex); 1019 bus_state->port_c_suspend |= 1 << wIndex; 1020 bus_state->suspended_ports &= ~(1 << wIndex); 1021 } 1022 1023 return 0; 1024 } 1025 1026 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) 1027 { 1028 u32 ext_stat = 0; 1029 int speed_id; 1030 1031 /* only support rx and tx lane counts of 1 in usb3.1 spec */ 1032 speed_id = DEV_PORT_SPEED(raw_port_status); 1033 ext_stat |= speed_id; /* bits 3:0, RX speed id */ 1034 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ 1035 1036 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ 1037 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ 1038 1039 return ext_stat; 1040 } 1041 1042 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, 1043 u32 portsc) 1044 { 1045 struct xhci_bus_state *bus_state; 1046 struct xhci_hcd *xhci; 1047 struct usb_hcd *hcd; 1048 u32 link_state; 1049 u32 portnum; 1050 1051 bus_state = &port->rhub->bus_state; 1052 xhci = hcd_to_xhci(port->rhub->hcd); 1053 hcd = port->rhub->hcd; 1054 link_state = portsc & PORT_PLS_MASK; 1055 portnum = port->hcd_portnum; 1056 1057 /* USB3 specific wPortChange bits 1058 * 1059 * Port link change with port in resume state should not be 1060 * reported to usbcore, as this is an internal state to be 1061 * handled by xhci driver. Reporting PLC to usbcore may 1062 * cause usbcore clearing PLC first and port change event 1063 * irq won't be generated. 1064 */ 1065 1066 if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) 1067 *status |= USB_PORT_STAT_C_LINK_STATE << 16; 1068 if (portsc & PORT_WRC) 1069 *status |= USB_PORT_STAT_C_BH_RESET << 16; 1070 if (portsc & PORT_CEC) 1071 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; 1072 1073 /* USB3 specific wPortStatus bits */ 1074 if (portsc & PORT_POWER) 1075 *status |= USB_SS_PORT_STAT_POWER; 1076 1077 /* no longer suspended or resuming */ 1078 if (link_state != XDEV_U3 && 1079 link_state != XDEV_RESUME && 1080 link_state != XDEV_RECOVERY) { 1081 /* remote wake resume signaling complete */ 1082 if (bus_state->port_remote_wakeup & (1 << portnum)) { 1083 bus_state->port_remote_wakeup &= ~(1 << portnum); 1084 usb_hcd_end_port_resume(&hcd->self, portnum); 1085 } 1086 bus_state->suspended_ports &= ~(1 << portnum); 1087 } 1088 1089 xhci_hub_report_usb3_link_state(xhci, status, portsc); 1090 xhci_del_comp_mod_timer(xhci, portsc, portnum); 1091 } 1092 1093 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, 1094 u32 portsc, unsigned long *flags) 1095 { 1096 struct xhci_bus_state *bus_state; 1097 u32 link_state; 1098 u32 portnum; 1099 int err; 1100 1101 bus_state = &port->rhub->bus_state; 1102 link_state = portsc & PORT_PLS_MASK; 1103 portnum = port->hcd_portnum; 1104 1105 /* USB2 wPortStatus bits */ 1106 if (portsc & PORT_POWER) { 1107 *status |= USB_PORT_STAT_POWER; 1108 1109 /* link state is only valid if port is powered */ 1110 if (link_state == XDEV_U3) 1111 *status |= USB_PORT_STAT_SUSPEND; 1112 if (link_state == XDEV_U2) 1113 *status |= USB_PORT_STAT_L1; 1114 if (link_state == XDEV_U0) { 1115 if (bus_state->suspended_ports & (1 << portnum)) { 1116 bus_state->suspended_ports &= ~(1 << portnum); 1117 bus_state->port_c_suspend |= 1 << portnum; 1118 } 1119 } 1120 if (link_state == XDEV_RESUME) { 1121 err = xhci_handle_usb2_port_link_resume(port, portsc, 1122 flags); 1123 if (err < 0) 1124 *status = 0xffffffff; 1125 else if (port->resume_timestamp || port->rexit_active) 1126 *status |= USB_PORT_STAT_SUSPEND; 1127 } 1128 } 1129 1130 /* 1131 * Clear usb2 resume signalling variables if port is no longer suspended 1132 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a 1133 * error state. Resume related variables should be cleared in all those cases. 1134 */ 1135 if (link_state != XDEV_U3 && link_state != XDEV_RESUME) { 1136 if (port->resume_timestamp || 1137 test_bit(portnum, &bus_state->resuming_ports)) { 1138 port->resume_timestamp = 0; 1139 clear_bit(portnum, &bus_state->resuming_ports); 1140 usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum); 1141 } 1142 port->rexit_active = 0; 1143 bus_state->suspended_ports &= ~(1 << portnum); 1144 } 1145 } 1146 1147 /* 1148 * Converts a raw xHCI port status into the format that external USB 2.0 or USB 1149 * 3.0 hubs use. 1150 * 1151 * Possible side effects: 1152 * - Mark a port as being done with device resume, 1153 * and ring the endpoint doorbells. 1154 * - Stop the Synopsys redriver Compliance Mode polling. 1155 * - Drop and reacquire the xHCI lock, in order to wait for port resume. 1156 */ 1157 static u32 xhci_get_port_status(struct usb_hcd *hcd, 1158 struct xhci_bus_state *bus_state, 1159 u16 wIndex, u32 raw_port_status, 1160 unsigned long *flags) 1161 __releases(&xhci->lock) 1162 __acquires(&xhci->lock) 1163 { 1164 u32 status = 0; 1165 struct xhci_hub *rhub; 1166 struct xhci_port *port; 1167 1168 rhub = xhci_get_rhub(hcd); 1169 port = rhub->ports[wIndex]; 1170 1171 /* common wPortChange bits */ 1172 if (raw_port_status & PORT_CSC) 1173 status |= USB_PORT_STAT_C_CONNECTION << 16; 1174 if (raw_port_status & PORT_PEC) 1175 status |= USB_PORT_STAT_C_ENABLE << 16; 1176 if ((raw_port_status & PORT_OCC)) 1177 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1178 if ((raw_port_status & PORT_RC)) 1179 status |= USB_PORT_STAT_C_RESET << 16; 1180 1181 /* common wPortStatus bits */ 1182 if (raw_port_status & PORT_CONNECT) { 1183 status |= USB_PORT_STAT_CONNECTION; 1184 status |= xhci_port_speed(raw_port_status); 1185 } 1186 if (raw_port_status & PORT_PE) 1187 status |= USB_PORT_STAT_ENABLE; 1188 if (raw_port_status & PORT_OC) 1189 status |= USB_PORT_STAT_OVERCURRENT; 1190 if (raw_port_status & PORT_RESET) 1191 status |= USB_PORT_STAT_RESET; 1192 1193 /* USB2 and USB3 specific bits, including Port Link State */ 1194 if (hcd->speed >= HCD_USB3) 1195 xhci_get_usb3_port_status(port, &status, raw_port_status); 1196 else 1197 xhci_get_usb2_port_status(port, &status, raw_port_status, 1198 flags); 1199 1200 if (bus_state->port_c_suspend & (1 << wIndex)) 1201 status |= USB_PORT_STAT_C_SUSPEND << 16; 1202 1203 return status; 1204 } 1205 1206 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1207 u16 wIndex, char *buf, u16 wLength) 1208 { 1209 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1210 int max_ports; 1211 unsigned long flags; 1212 u32 temp, status; 1213 int retval = 0; 1214 struct xhci_bus_state *bus_state; 1215 u16 link_state = 0; 1216 u16 wake_mask = 0; 1217 u16 timeout = 0; 1218 u16 test_mode = 0; 1219 struct xhci_hub *rhub; 1220 struct xhci_port **ports; 1221 struct xhci_port *port; 1222 int portnum1; 1223 1224 rhub = xhci_get_rhub(hcd); 1225 ports = rhub->ports; 1226 max_ports = rhub->num_ports; 1227 bus_state = &rhub->bus_state; 1228 portnum1 = wIndex & 0xff; 1229 1230 spin_lock_irqsave(&xhci->lock, flags); 1231 switch (typeReq) { 1232 case GetHubStatus: 1233 /* No power source, over-current reported per port */ 1234 memset(buf, 0, 4); 1235 break; 1236 case GetHubDescriptor: 1237 /* Check to make sure userspace is asking for the USB 3.0 hub 1238 * descriptor for the USB 3.0 roothub. If not, we stall the 1239 * endpoint, like external hubs do. 1240 */ 1241 if (hcd->speed >= HCD_USB3 && 1242 (wLength < USB_DT_SS_HUB_SIZE || 1243 wValue != (USB_DT_SS_HUB << 8))) { 1244 xhci_dbg(xhci, "Wrong hub descriptor type for " 1245 "USB 3.0 roothub.\n"); 1246 goto error; 1247 } 1248 xhci_hub_descriptor(hcd, xhci, 1249 (struct usb_hub_descriptor *) buf); 1250 break; 1251 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 1252 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 1253 goto error; 1254 1255 if (hcd->speed < HCD_USB3) 1256 goto error; 1257 1258 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength); 1259 spin_unlock_irqrestore(&xhci->lock, flags); 1260 return retval; 1261 case GetPortStatus: 1262 if (!portnum1 || portnum1 > max_ports) 1263 goto error; 1264 1265 wIndex--; 1266 port = ports[portnum1 - 1]; 1267 temp = readl(port->addr); 1268 if (temp == ~(u32)0) { 1269 xhci_hc_died(xhci); 1270 retval = -ENODEV; 1271 break; 1272 } 1273 trace_xhci_get_port_status(port, temp); 1274 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, 1275 &flags); 1276 if (status == 0xffffffff) 1277 goto error; 1278 1279 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", 1280 hcd->self.busnum, portnum1, temp, status); 1281 1282 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1283 /* if USB 3.1 extended port status return additional 4 bytes */ 1284 if (wValue == 0x02) { 1285 u32 port_li; 1286 1287 if (hcd->speed < HCD_USB31 || wLength != 8) { 1288 xhci_err(xhci, "get ext port status invalid parameter\n"); 1289 retval = -EINVAL; 1290 break; 1291 } 1292 port_li = readl(port->addr + PORTLI); 1293 status = xhci_get_ext_port_status(temp, port_li); 1294 put_unaligned_le32(status, &buf[4]); 1295 } 1296 break; 1297 case SetPortFeature: 1298 if (wValue == USB_PORT_FEAT_LINK_STATE) 1299 link_state = (wIndex & 0xff00) >> 3; 1300 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 1301 wake_mask = wIndex & 0xff00; 1302 if (wValue == USB_PORT_FEAT_TEST) 1303 test_mode = (wIndex & 0xff00) >> 8; 1304 /* The MSB of wIndex is the U1/U2 timeout */ 1305 timeout = (wIndex & 0xff00) >> 8; 1306 1307 wIndex &= 0xff; 1308 if (!portnum1 || portnum1 > max_ports) 1309 goto error; 1310 1311 port = ports[portnum1 - 1]; 1312 wIndex--; 1313 temp = readl(port->addr); 1314 if (temp == ~(u32)0) { 1315 xhci_hc_died(xhci); 1316 retval = -ENODEV; 1317 break; 1318 } 1319 temp = xhci_port_state_to_neutral(temp); 1320 /* FIXME: What new port features do we need to support? */ 1321 switch (wValue) { 1322 case USB_PORT_FEAT_SUSPEND: 1323 temp = readl(port->addr); 1324 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 1325 /* Resume the port to U0 first */ 1326 xhci_set_link_state(xhci, port, XDEV_U0); 1327 spin_unlock_irqrestore(&xhci->lock, flags); 1328 msleep(10); 1329 spin_lock_irqsave(&xhci->lock, flags); 1330 } 1331 /* In spec software should not attempt to suspend 1332 * a port unless the port reports that it is in the 1333 * enabled (PED = ‘1’,PLS < ‘3’) state. 1334 */ 1335 temp = readl(port->addr); 1336 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 1337 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 1338 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", 1339 hcd->self.busnum, portnum1); 1340 goto error; 1341 } 1342 1343 if (!port->slot_id) { 1344 xhci_warn(xhci, "slot_id is zero\n"); 1345 goto error; 1346 } 1347 /* unlock to execute stop endpoint commands */ 1348 spin_unlock_irqrestore(&xhci->lock, flags); 1349 xhci_stop_device(xhci, port->slot_id, 1); 1350 spin_lock_irqsave(&xhci->lock, flags); 1351 1352 xhci_set_link_state(xhci, port, XDEV_U3); 1353 1354 spin_unlock_irqrestore(&xhci->lock, flags); 1355 msleep(10); /* wait device to enter */ 1356 spin_lock_irqsave(&xhci->lock, flags); 1357 1358 temp = readl(port->addr); 1359 bus_state->suspended_ports |= 1 << wIndex; 1360 break; 1361 case USB_PORT_FEAT_LINK_STATE: 1362 temp = readl(port->addr); 1363 /* Disable port */ 1364 if (link_state == USB_SS_PORT_LS_SS_DISABLED) { 1365 xhci_dbg(xhci, "Disable port %d-%d\n", 1366 hcd->self.busnum, portnum1); 1367 temp = xhci_port_state_to_neutral(temp); 1368 /* 1369 * Clear all change bits, so that we get a new 1370 * connection event. 1371 */ 1372 temp |= PORT_CSC | PORT_PEC | PORT_WRC | 1373 PORT_OCC | PORT_RC | PORT_PLC | 1374 PORT_CEC; 1375 writel(temp | PORT_PE, port->addr); 1376 temp = readl(port->addr); 1377 break; 1378 } 1379 1380 /* Put link in RxDetect (enable port) */ 1381 if (link_state == USB_SS_PORT_LS_RX_DETECT) { 1382 xhci_dbg(xhci, "Enable port %d-%d\n", 1383 hcd->self.busnum, portnum1); 1384 xhci_set_link_state(xhci, port, link_state); 1385 temp = readl(port->addr); 1386 break; 1387 } 1388 1389 /* 1390 * For xHCI 1.1 according to section 4.19.1.2.4.1 a 1391 * root hub port's transition to compliance mode upon 1392 * detecting LFPS timeout may be controlled by an 1393 * Compliance Transition Enabled (CTE) flag (not 1394 * software visible). This flag is set by writing 0xA 1395 * to PORTSC PLS field which will allow transition to 1396 * compliance mode the next time LFPS timeout is 1397 * encountered. A warm reset will clear it. 1398 * 1399 * The CTE flag is only supported if the HCCPARAMS2 CTC 1400 * flag is set, otherwise, the compliance substate is 1401 * automatically entered as on 1.0 and prior. 1402 */ 1403 if (link_state == USB_SS_PORT_LS_COMP_MOD) { 1404 if (!HCC2_CTC(xhci->hcc_params2)) { 1405 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); 1406 break; 1407 } 1408 1409 if ((temp & PORT_CONNECT)) { 1410 xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); 1411 goto error; 1412 } 1413 1414 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", 1415 hcd->self.busnum, portnum1); 1416 xhci_set_link_state(xhci, port, link_state); 1417 1418 temp = readl(port->addr); 1419 break; 1420 } 1421 /* Port must be enabled */ 1422 if (!(temp & PORT_PE)) { 1423 retval = -ENODEV; 1424 break; 1425 } 1426 /* Can't set port link state above '3' (U3) */ 1427 if (link_state > USB_SS_PORT_LS_U3) { 1428 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", 1429 hcd->self.busnum, portnum1, link_state); 1430 goto error; 1431 } 1432 1433 /* 1434 * set link to U0, steps depend on current link state. 1435 * U3: set link to U0 and wait for u3exit completion. 1436 * U1/U2: no PLC complete event, only set link to U0. 1437 * Resume/Recovery: device initiated U0, only wait for 1438 * completion 1439 */ 1440 if (link_state == USB_SS_PORT_LS_U0) { 1441 u32 pls = temp & PORT_PLS_MASK; 1442 bool wait_u0 = false; 1443 1444 /* already in U0 */ 1445 if (pls == XDEV_U0) 1446 break; 1447 if (pls == XDEV_U3 || 1448 pls == XDEV_RESUME || 1449 pls == XDEV_RECOVERY) { 1450 wait_u0 = true; 1451 reinit_completion(&port->u3exit_done); 1452 } 1453 if (pls <= XDEV_U3) /* U1, U2, U3 */ 1454 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0); 1455 if (!wait_u0) { 1456 if (pls > XDEV_U3) 1457 goto error; 1458 break; 1459 } 1460 spin_unlock_irqrestore(&xhci->lock, flags); 1461 if (!wait_for_completion_timeout(&port->u3exit_done, 1462 msecs_to_jiffies(500))) 1463 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", 1464 hcd->self.busnum, portnum1); 1465 spin_lock_irqsave(&xhci->lock, flags); 1466 temp = readl(port->addr); 1467 break; 1468 } 1469 1470 if (link_state == USB_SS_PORT_LS_U3) { 1471 int retries = 16; 1472 if (port->slot_id) { 1473 /* unlock to execute stop endpoint 1474 * commands */ 1475 spin_unlock_irqrestore(&xhci->lock, 1476 flags); 1477 xhci_stop_device(xhci, port->slot_id, 1); 1478 spin_lock_irqsave(&xhci->lock, flags); 1479 } 1480 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3); 1481 spin_unlock_irqrestore(&xhci->lock, flags); 1482 while (retries--) { 1483 usleep_range(4000, 8000); 1484 temp = readl(port->addr); 1485 if ((temp & PORT_PLS_MASK) == XDEV_U3) 1486 break; 1487 } 1488 spin_lock_irqsave(&xhci->lock, flags); 1489 temp = readl(port->addr); 1490 bus_state->suspended_ports |= 1 << wIndex; 1491 } 1492 break; 1493 case USB_PORT_FEAT_POWER: 1494 /* 1495 * Turn on ports, even if there isn't per-port switching. 1496 * HC will report connect events even before this is set. 1497 * However, hub_wq will ignore the roothub events until 1498 * the roothub is registered. 1499 */ 1500 xhci_set_port_power(xhci, port, true, &flags); 1501 break; 1502 case USB_PORT_FEAT_RESET: 1503 temp = (temp | PORT_RESET); 1504 writel(temp, port->addr); 1505 1506 temp = readl(port->addr); 1507 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", 1508 hcd->self.busnum, portnum1, temp); 1509 break; 1510 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 1511 xhci_set_remote_wake_mask(xhci, port, wake_mask); 1512 temp = readl(port->addr); 1513 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", 1514 hcd->self.busnum, portnum1, temp); 1515 break; 1516 case USB_PORT_FEAT_BH_PORT_RESET: 1517 temp |= PORT_WR; 1518 writel(temp, port->addr); 1519 temp = readl(port->addr); 1520 break; 1521 case USB_PORT_FEAT_U1_TIMEOUT: 1522 if (hcd->speed < HCD_USB3) 1523 goto error; 1524 temp = readl(port->addr + PORTPMSC); 1525 temp &= ~PORT_U1_TIMEOUT_MASK; 1526 temp |= PORT_U1_TIMEOUT(timeout); 1527 writel(temp, port->addr + PORTPMSC); 1528 break; 1529 case USB_PORT_FEAT_U2_TIMEOUT: 1530 if (hcd->speed < HCD_USB3) 1531 goto error; 1532 temp = readl(port->addr + PORTPMSC); 1533 temp &= ~PORT_U2_TIMEOUT_MASK; 1534 temp |= PORT_U2_TIMEOUT(timeout); 1535 writel(temp, port->addr + PORTPMSC); 1536 break; 1537 case USB_PORT_FEAT_TEST: 1538 /* 4.19.6 Port Test Modes (USB2 Test Mode) */ 1539 if (hcd->speed != HCD_USB2) 1540 goto error; 1541 if (test_mode > USB_TEST_FORCE_ENABLE || 1542 test_mode < USB_TEST_J) 1543 goto error; 1544 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, 1545 &flags); 1546 break; 1547 default: 1548 goto error; 1549 } 1550 /* unblock any posted writes */ 1551 temp = readl(port->addr); 1552 break; 1553 case ClearPortFeature: 1554 if (!portnum1 || portnum1 > max_ports) 1555 goto error; 1556 1557 port = ports[portnum1 - 1]; 1558 1559 wIndex--; 1560 temp = readl(port->addr); 1561 if (temp == ~(u32)0) { 1562 xhci_hc_died(xhci); 1563 retval = -ENODEV; 1564 break; 1565 } 1566 /* FIXME: What new port features do we need to support? */ 1567 temp = xhci_port_state_to_neutral(temp); 1568 switch (wValue) { 1569 case USB_PORT_FEAT_SUSPEND: 1570 temp = readl(port->addr); 1571 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 1572 xhci_dbg(xhci, "PORTSC %04x\n", temp); 1573 if (temp & PORT_RESET) 1574 goto error; 1575 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 1576 if ((temp & PORT_PE) == 0) 1577 goto error; 1578 1579 set_bit(wIndex, &bus_state->resuming_ports); 1580 usb_hcd_start_port_resume(&hcd->self, wIndex); 1581 xhci_set_link_state(xhci, port, XDEV_RESUME); 1582 spin_unlock_irqrestore(&xhci->lock, flags); 1583 msleep(USB_RESUME_TIMEOUT); 1584 spin_lock_irqsave(&xhci->lock, flags); 1585 xhci_set_link_state(xhci, port, XDEV_U0); 1586 clear_bit(wIndex, &bus_state->resuming_ports); 1587 usb_hcd_end_port_resume(&hcd->self, wIndex); 1588 } 1589 bus_state->port_c_suspend |= 1 << wIndex; 1590 1591 if (!port->slot_id) { 1592 xhci_dbg(xhci, "slot_id is zero\n"); 1593 goto error; 1594 } 1595 xhci_ring_device(xhci, port->slot_id); 1596 break; 1597 case USB_PORT_FEAT_C_SUSPEND: 1598 bus_state->port_c_suspend &= ~(1 << wIndex); 1599 fallthrough; 1600 case USB_PORT_FEAT_C_RESET: 1601 case USB_PORT_FEAT_C_BH_PORT_RESET: 1602 case USB_PORT_FEAT_C_CONNECTION: 1603 case USB_PORT_FEAT_C_OVER_CURRENT: 1604 case USB_PORT_FEAT_C_ENABLE: 1605 case USB_PORT_FEAT_C_PORT_LINK_STATE: 1606 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: 1607 xhci_clear_port_change_bit(xhci, wValue, wIndex, 1608 port->addr, temp); 1609 break; 1610 case USB_PORT_FEAT_ENABLE: 1611 xhci_disable_port(xhci, port); 1612 break; 1613 case USB_PORT_FEAT_POWER: 1614 xhci_set_port_power(xhci, port, false, &flags); 1615 break; 1616 case USB_PORT_FEAT_TEST: 1617 retval = xhci_exit_test_mode(xhci); 1618 break; 1619 default: 1620 goto error; 1621 } 1622 break; 1623 default: 1624 error: 1625 /* "stall" on error */ 1626 retval = -EPIPE; 1627 } 1628 spin_unlock_irqrestore(&xhci->lock, flags); 1629 return retval; 1630 } 1631 EXPORT_SYMBOL_GPL(xhci_hub_control); 1632 1633 /* 1634 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 1635 * Ports are 0-indexed from the HCD point of view, 1636 * and 1-indexed from the USB core pointer of view. 1637 * 1638 * Note that the status change bits will be cleared as soon as a port status 1639 * change event is generated, so we use the saved status from that event. 1640 */ 1641 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 1642 { 1643 unsigned long flags; 1644 u32 temp, status; 1645 u32 mask; 1646 int i, retval; 1647 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1648 int max_ports; 1649 struct xhci_bus_state *bus_state; 1650 bool reset_change = false; 1651 struct xhci_hub *rhub; 1652 struct xhci_port **ports; 1653 1654 rhub = xhci_get_rhub(hcd); 1655 ports = rhub->ports; 1656 max_ports = rhub->num_ports; 1657 bus_state = &rhub->bus_state; 1658 1659 /* Initial status is no changes */ 1660 retval = (max_ports + 8) / 8; 1661 memset(buf, 0, retval); 1662 1663 /* 1664 * Inform the usbcore about resume-in-progress by returning 1665 * a non-zero value even if there are no status changes. 1666 */ 1667 spin_lock_irqsave(&xhci->lock, flags); 1668 1669 status = bus_state->resuming_ports; 1670 1671 /* 1672 * SS devices are only visible to roothub after link training completes. 1673 * Keep polling roothubs for a grace period after xHC start 1674 */ 1675 if (xhci->run_graceperiod) { 1676 if (time_before(jiffies, xhci->run_graceperiod)) 1677 status = 1; 1678 else 1679 xhci->run_graceperiod = 0; 1680 } 1681 1682 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; 1683 1684 /* For each port, did anything change? If so, set that bit in buf. */ 1685 for (i = 0; i < max_ports; i++) { 1686 temp = readl(ports[i]->addr); 1687 if (temp == ~(u32)0) { 1688 xhci_hc_died(xhci); 1689 retval = -ENODEV; 1690 break; 1691 } 1692 trace_xhci_hub_status_data(ports[i], temp); 1693 1694 if ((temp & mask) != 0 || 1695 (bus_state->port_c_suspend & 1 << i) || 1696 (ports[i]->resume_timestamp && time_after_eq( 1697 jiffies, ports[i]->resume_timestamp))) { 1698 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 1699 status = 1; 1700 } 1701 if ((temp & PORT_RC)) 1702 reset_change = true; 1703 if (temp & PORT_OC) 1704 status = 1; 1705 } 1706 if (!status && !reset_change) { 1707 xhci_dbg(xhci, "%s: stopping usb%d port polling\n", 1708 __func__, hcd->self.busnum); 1709 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1710 } 1711 spin_unlock_irqrestore(&xhci->lock, flags); 1712 return status ? retval : 0; 1713 } 1714 1715 #ifdef CONFIG_PM 1716 1717 int xhci_bus_suspend(struct usb_hcd *hcd) 1718 { 1719 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1720 int max_ports, port_index; 1721 struct xhci_bus_state *bus_state; 1722 unsigned long flags; 1723 struct xhci_hub *rhub; 1724 struct xhci_port **ports; 1725 u32 portsc_buf[USB_MAXCHILDREN]; 1726 bool wake_enabled; 1727 1728 rhub = xhci_get_rhub(hcd); 1729 ports = rhub->ports; 1730 max_ports = rhub->num_ports; 1731 bus_state = &rhub->bus_state; 1732 wake_enabled = hcd->self.root_hub->do_remote_wakeup; 1733 1734 spin_lock_irqsave(&xhci->lock, flags); 1735 1736 if (wake_enabled) { 1737 if (bus_state->resuming_ports || /* USB2 */ 1738 bus_state->port_remote_wakeup) { /* USB3 */ 1739 spin_unlock_irqrestore(&xhci->lock, flags); 1740 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n", 1741 hcd->self.busnum); 1742 return -EBUSY; 1743 } 1744 } 1745 /* 1746 * Prepare ports for suspend, but don't write anything before all ports 1747 * are checked and we know bus suspend can proceed 1748 */ 1749 bus_state->bus_suspended = 0; 1750 port_index = max_ports; 1751 while (port_index--) { 1752 u32 t1, t2; 1753 int retries = 10; 1754 retry: 1755 t1 = readl(ports[port_index]->addr); 1756 t2 = xhci_port_state_to_neutral(t1); 1757 portsc_buf[port_index] = 0; 1758 1759 /* 1760 * Give a USB3 port in link training time to finish, but don't 1761 * prevent suspend as port might be stuck 1762 */ 1763 if ((hcd->speed >= HCD_USB3) && retries-- && 1764 (t1 & PORT_PLS_MASK) == XDEV_POLLING) { 1765 spin_unlock_irqrestore(&xhci->lock, flags); 1766 msleep(XHCI_PORT_POLLING_LFPS_TIME); 1767 spin_lock_irqsave(&xhci->lock, flags); 1768 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", 1769 hcd->self.busnum, port_index + 1); 1770 goto retry; 1771 } 1772 /* bail out if port detected a over-current condition */ 1773 if (t1 & PORT_OC) { 1774 bus_state->bus_suspended = 0; 1775 spin_unlock_irqrestore(&xhci->lock, flags); 1776 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); 1777 return -EBUSY; 1778 } 1779 /* suspend ports in U0, or bail out for new connect changes */ 1780 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { 1781 if ((t1 & PORT_CSC) && wake_enabled) { 1782 bus_state->bus_suspended = 0; 1783 spin_unlock_irqrestore(&xhci->lock, flags); 1784 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); 1785 return -EBUSY; 1786 } 1787 xhci_dbg(xhci, "port %d-%d not suspended\n", 1788 hcd->self.busnum, port_index + 1); 1789 t2 &= ~PORT_PLS_MASK; 1790 t2 |= PORT_LINK_STROBE | XDEV_U3; 1791 set_bit(port_index, &bus_state->bus_suspended); 1792 } 1793 /* USB core sets remote wake mask for USB 3.0 hubs, 1794 * including the USB 3.0 roothub, but only if CONFIG_PM 1795 * is enabled, so also enable remote wake here. 1796 */ 1797 if (wake_enabled) { 1798 if (t1 & PORT_CONNECT) { 1799 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 1800 t2 &= ~PORT_WKCONN_E; 1801 } else { 1802 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 1803 t2 &= ~PORT_WKDISC_E; 1804 } 1805 1806 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && 1807 (hcd->speed < HCD_USB3)) { 1808 if (usb_amd_pt_check_port(hcd->self.controller, 1809 port_index)) 1810 t2 &= ~PORT_WAKE_BITS; 1811 } 1812 } else 1813 t2 &= ~PORT_WAKE_BITS; 1814 1815 t1 = xhci_port_state_to_neutral(t1); 1816 if (t1 != t2) 1817 portsc_buf[port_index] = t2; 1818 } 1819 1820 /* write port settings, stopping and suspending ports if needed */ 1821 port_index = max_ports; 1822 while (port_index--) { 1823 if (!portsc_buf[port_index]) 1824 continue; 1825 if (test_bit(port_index, &bus_state->bus_suspended)) { 1826 int slot_id = ports[port_index]->slot_id; 1827 if (slot_id) { 1828 spin_unlock_irqrestore(&xhci->lock, flags); 1829 xhci_stop_device(xhci, slot_id, 1); 1830 spin_lock_irqsave(&xhci->lock, flags); 1831 } 1832 } 1833 writel(portsc_buf[port_index], ports[port_index]->addr); 1834 } 1835 hcd->state = HC_STATE_SUSPENDED; 1836 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 1837 spin_unlock_irqrestore(&xhci->lock, flags); 1838 1839 if (bus_state->bus_suspended) 1840 usleep_range(5000, 10000); 1841 1842 return 0; 1843 } 1844 1845 /* 1846 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. 1847 * warm reset a USB3 device stuck in polling or compliance mode after resume. 1848 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 1849 */ 1850 static bool xhci_port_missing_cas_quirk(struct xhci_port *port) 1851 { 1852 u32 portsc; 1853 1854 portsc = readl(port->addr); 1855 1856 /* if any of these are set we are not stuck */ 1857 if (portsc & (PORT_CONNECT | PORT_CAS)) 1858 return false; 1859 1860 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && 1861 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) 1862 return false; 1863 1864 /* clear wakeup/change bits, and do a warm port reset */ 1865 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1866 portsc |= PORT_WR; 1867 writel(portsc, port->addr); 1868 /* flush write */ 1869 readl(port->addr); 1870 return true; 1871 } 1872 1873 int xhci_bus_resume(struct usb_hcd *hcd) 1874 { 1875 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1876 struct xhci_bus_state *bus_state; 1877 unsigned long flags; 1878 int max_ports, port_index; 1879 int sret; 1880 u32 next_state; 1881 u32 temp, portsc; 1882 struct xhci_hub *rhub; 1883 struct xhci_port **ports; 1884 1885 rhub = xhci_get_rhub(hcd); 1886 ports = rhub->ports; 1887 max_ports = rhub->num_ports; 1888 bus_state = &rhub->bus_state; 1889 1890 if (time_before(jiffies, bus_state->next_statechange)) 1891 msleep(5); 1892 1893 spin_lock_irqsave(&xhci->lock, flags); 1894 if (!HCD_HW_ACCESSIBLE(hcd)) { 1895 spin_unlock_irqrestore(&xhci->lock, flags); 1896 return -ESHUTDOWN; 1897 } 1898 1899 /* delay the irqs */ 1900 temp = readl(&xhci->op_regs->command); 1901 temp &= ~CMD_EIE; 1902 writel(temp, &xhci->op_regs->command); 1903 1904 /* bus specific resume for ports we suspended at bus_suspend */ 1905 if (hcd->speed >= HCD_USB3) 1906 next_state = XDEV_U0; 1907 else 1908 next_state = XDEV_RESUME; 1909 1910 port_index = max_ports; 1911 while (port_index--) { 1912 portsc = readl(ports[port_index]->addr); 1913 1914 /* warm reset CAS limited ports stuck in polling/compliance */ 1915 if ((xhci->quirks & XHCI_MISSING_CAS) && 1916 (hcd->speed >= HCD_USB3) && 1917 xhci_port_missing_cas_quirk(ports[port_index])) { 1918 xhci_dbg(xhci, "reset stuck port %d-%d\n", 1919 hcd->self.busnum, port_index + 1); 1920 clear_bit(port_index, &bus_state->bus_suspended); 1921 continue; 1922 } 1923 /* resume if we suspended the link, and it is still suspended */ 1924 if (test_bit(port_index, &bus_state->bus_suspended)) 1925 switch (portsc & PORT_PLS_MASK) { 1926 case XDEV_U3: 1927 portsc = xhci_port_state_to_neutral(portsc); 1928 portsc &= ~PORT_PLS_MASK; 1929 portsc |= PORT_LINK_STROBE | next_state; 1930 break; 1931 case XDEV_RESUME: 1932 /* resume already initiated */ 1933 break; 1934 default: 1935 /* not in a resumable state, ignore it */ 1936 clear_bit(port_index, 1937 &bus_state->bus_suspended); 1938 break; 1939 } 1940 /* disable wake for all ports, write new link state if needed */ 1941 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1942 writel(portsc, ports[port_index]->addr); 1943 } 1944 1945 /* USB2 specific resume signaling delay and U0 link state transition */ 1946 if (hcd->speed < HCD_USB3) { 1947 if (bus_state->bus_suspended) { 1948 spin_unlock_irqrestore(&xhci->lock, flags); 1949 msleep(USB_RESUME_TIMEOUT); 1950 spin_lock_irqsave(&xhci->lock, flags); 1951 } 1952 for_each_set_bit(port_index, &bus_state->bus_suspended, 1953 BITS_PER_LONG) { 1954 /* Clear PLC to poll it later for U0 transition */ 1955 xhci_test_and_clear_bit(xhci, ports[port_index], 1956 PORT_PLC); 1957 xhci_set_link_state(xhci, ports[port_index], XDEV_U0); 1958 } 1959 } 1960 1961 /* poll for U0 link state complete, both USB2 and USB3 */ 1962 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { 1963 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, 1964 PORT_PLC, 10 * 1000); 1965 if (sret) { 1966 xhci_warn(xhci, "port %d-%d resume PLC timeout\n", 1967 hcd->self.busnum, port_index + 1); 1968 continue; 1969 } 1970 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); 1971 if (ports[port_index]->slot_id) 1972 xhci_ring_device(xhci, ports[port_index]->slot_id); 1973 } 1974 (void) readl(&xhci->op_regs->command); 1975 1976 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1977 /* re-enable irqs */ 1978 temp = readl(&xhci->op_regs->command); 1979 temp |= CMD_EIE; 1980 writel(temp, &xhci->op_regs->command); 1981 temp = readl(&xhci->op_regs->command); 1982 1983 spin_unlock_irqrestore(&xhci->lock, flags); 1984 return 0; 1985 } 1986 1987 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) 1988 { 1989 struct xhci_hub *rhub = xhci_get_rhub(hcd); 1990 1991 /* USB3 port wakeups are reported via usb_wakeup_notification() */ 1992 return rhub->bus_state.resuming_ports; /* USB2 ports only */ 1993 } 1994 1995 #endif /* CONFIG_PM */ 1996