1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */ 12 #define XHCI_MAX_HALT_USEC (32 * 1000) 13 /* HC not running - set to 1 when run/stop bit is cleared. */ 14 #define XHCI_STS_HALT (1<<0) 15 16 /* HCCPARAMS offset from PCI base address */ 17 #define XHCI_HCC_PARAMS_OFFSET 0x10 18 /* HCCPARAMS contains the first extended capability pointer */ 19 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 20 21 /* Command and Status registers offset from the Operational Registers address */ 22 #define XHCI_CMD_OFFSET 0x00 23 #define XHCI_STS_OFFSET 0x04 24 25 #define XHCI_MAX_EXT_CAPS 50 26 27 /* Capability Register */ 28 /* bits 7:0 - how long is the Capabilities register */ 29 #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff) 30 31 /* Extended capability register fields */ 32 #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff) 33 #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff) 34 #define XHCI_EXT_CAPS_VAL(p) ((p)>>16) 35 /* Extended capability IDs - ID 0 reserved */ 36 #define XHCI_EXT_CAPS_LEGACY 1 37 #define XHCI_EXT_CAPS_PROTOCOL 2 38 #define XHCI_EXT_CAPS_PM 3 39 #define XHCI_EXT_CAPS_VIRT 4 40 #define XHCI_EXT_CAPS_ROUTE 5 41 /* IDs 6-9 reserved */ 42 #define XHCI_EXT_CAPS_DEBUG 10 43 /* Vendor caps */ 44 #define XHCI_EXT_CAPS_VENDOR_INTEL 192 45 #define XHCI_EXT_CAPS_INTEL_SPR_SHADOW 206 46 /* USB Legacy Support Capability - section 7.1.1 */ 47 #define XHCI_HC_BIOS_OWNED (1 << 16) 48 #define XHCI_HC_OS_OWNED (1 << 24) 49 50 /* USB Legacy Support Capability - section 7.1.1 */ 51 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 52 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 53 54 /* USB Legacy Support Control and Status Register - section 7.1.2 */ 55 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 56 #define XHCI_LEGACY_CONTROL_OFFSET (0x04) 57 /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 58 #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17)) 59 #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29) 60 61 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 62 #define XHCI_L1C (1 << 16) 63 64 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 65 #define XHCI_HLC (1 << 19) 66 #define XHCI_BLC (1 << 20) 67 68 /* Intel SPR shadow capability */ 69 #define XHCI_INTEL_SPR_ESS_PORT_OFFSET 0x8ac4 /* SuperSpeed port control */ 70 #define XHCI_INTEL_SPR_TUNEN BIT(4) /* Tunnel mode enabled */ 71 72 /* command register values to disable interrupts and halt the HC */ 73 /* start/stop HC execution - do not write unless HC is halted*/ 74 #define XHCI_CMD_RUN (1 << 0) 75 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 76 #define XHCI_CMD_EIE (1 << 2) 77 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 78 #define XHCI_CMD_HSEIE (1 << 3) 79 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 80 #define XHCI_CMD_EWE (1 << 10) 81 82 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 83 84 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 85 #define XHCI_STS_CNR (1 << 11) 86 87 /** 88 * struct xhci_protocol_caps 89 * @revision: major revision, minor revision, capability ID, 90 * and next capability pointer. 91 * @name_string: Four ASCII characters to say which spec this xHC 92 * follows, typically "USB ". 93 * @port_info: Port offset, count, and protocol-defined information. 94 */ 95 struct xhci_protocol_caps { 96 u32 revision; 97 u32 name_string; 98 u32 port_info; 99 }; 100 101 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 102 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 103 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 104 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 105 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 106 107 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 108 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 109 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 110 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 111 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 112 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 113 114 #include <linux/io.h> 115 116 /** 117 * Find the offset of the extended capabilities with capability ID id. 118 * 119 * @base PCI MMIO registers base address. 120 * @start address at which to start looking, (0 or HCC_PARAMS to start at 121 * beginning of list) 122 * @id Extended capability ID to search for, or 0 for the next 123 * capability 124 * 125 * Returns the offset of the next matching extended capability structure. 126 * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL, 127 * and this provides a way to find them all. 128 */ 129 130 static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) 131 { 132 u32 val; 133 u32 next; 134 u32 offset; 135 136 offset = start; 137 if (!start || start == XHCI_HCC_PARAMS_OFFSET) { 138 val = readl(base + XHCI_HCC_PARAMS_OFFSET); 139 if (val == ~0) 140 return 0; 141 offset = XHCI_HCC_EXT_CAPS(val) << 2; 142 if (!offset) 143 return 0; 144 } 145 do { 146 val = readl(base + offset); 147 if (val == ~0) 148 return 0; 149 if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id)) 150 return offset; 151 152 next = XHCI_EXT_CAPS_NEXT(val); 153 offset += next << 2; 154 } while (next); 155 156 return 0; 157 } 158