1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */ 12 #define XHCI_MAX_HALT_USEC (32 * 1000) 13 /* HC not running - set to 1 when run/stop bit is cleared. */ 14 #define XHCI_STS_HALT (1<<0) 15 16 /* HCCPARAMS offset from PCI base address */ 17 #define XHCI_HCC_PARAMS_OFFSET 0x10 18 /* HCCPARAMS contains the first extended capability pointer */ 19 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 20 21 /* Command and Status registers offset from the Operational Registers address */ 22 #define XHCI_CMD_OFFSET 0x00 23 #define XHCI_STS_OFFSET 0x04 24 25 #define XHCI_MAX_EXT_CAPS 50 26 27 /* Capability Register */ 28 /* bits 7:0 - how long is the Capabilities register */ 29 #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff) 30 31 /* Extended capability register fields */ 32 #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff) 33 #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff) 34 #define XHCI_EXT_CAPS_VAL(p) ((p)>>16) 35 /* Extended capability IDs - ID 0 reserved */ 36 #define XHCI_EXT_CAPS_LEGACY 1 37 #define XHCI_EXT_CAPS_PROTOCOL 2 38 #define XHCI_EXT_CAPS_PM 3 39 #define XHCI_EXT_CAPS_VIRT 4 40 #define XHCI_EXT_CAPS_ROUTE 5 41 /* IDs 6-9 reserved */ 42 #define XHCI_EXT_CAPS_DEBUG 10 43 /* Vendor caps */ 44 #define XHCI_EXT_CAPS_VENDOR_INTEL 192 45 /* USB Legacy Support Capability - section 7.1.1 */ 46 #define XHCI_HC_BIOS_OWNED (1 << 16) 47 #define XHCI_HC_OS_OWNED (1 << 24) 48 49 /* USB Legacy Support Capability - section 7.1.1 */ 50 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 51 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 52 53 /* USB Legacy Support Control and Status Register - section 7.1.2 */ 54 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 55 #define XHCI_LEGACY_CONTROL_OFFSET (0x04) 56 /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 57 #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17)) 58 #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29) 59 60 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 61 #define XHCI_L1C (1 << 16) 62 63 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 64 #define XHCI_HLC (1 << 19) 65 #define XHCI_BLC (1 << 20) 66 67 /* command register values to disable interrupts and halt the HC */ 68 /* start/stop HC execution - do not write unless HC is halted*/ 69 #define XHCI_CMD_RUN (1 << 0) 70 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 71 #define XHCI_CMD_EIE (1 << 2) 72 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 73 #define XHCI_CMD_HSEIE (1 << 3) 74 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 75 #define XHCI_CMD_EWE (1 << 10) 76 77 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 78 79 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 80 #define XHCI_STS_CNR (1 << 11) 81 82 /** 83 * struct xhci_protocol_caps 84 * @revision: major revision, minor revision, capability ID, 85 * and next capability pointer. 86 * @name_string: Four ASCII characters to say which spec this xHC 87 * follows, typically "USB ". 88 * @port_info: Port offset, count, and protocol-defined information. 89 */ 90 struct xhci_protocol_caps { 91 u32 revision; 92 u32 name_string; 93 u32 port_info; 94 }; 95 96 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 97 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 98 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 99 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 100 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 101 102 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 103 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 104 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 105 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 106 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 107 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 108 109 #include <linux/io.h> 110 111 /** 112 * Find the offset of the extended capabilities with capability ID id. 113 * 114 * @base PCI MMIO registers base address. 115 * @start address at which to start looking, (0 or HCC_PARAMS to start at 116 * beginning of list) 117 * @id Extended capability ID to search for, or 0 for the next 118 * capability 119 * 120 * Returns the offset of the next matching extended capability structure. 121 * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL, 122 * and this provides a way to find them all. 123 */ 124 125 static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) 126 { 127 u32 val; 128 u32 next; 129 u32 offset; 130 131 offset = start; 132 if (!start || start == XHCI_HCC_PARAMS_OFFSET) { 133 val = readl(base + XHCI_HCC_PARAMS_OFFSET); 134 if (val == ~0) 135 return 0; 136 offset = XHCI_HCC_EXT_CAPS(val) << 2; 137 if (!offset) 138 return 0; 139 } 140 do { 141 val = readl(base + offset); 142 if (val == ~0) 143 return 0; 144 if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id)) 145 return offset; 146 147 next = XHCI_EXT_CAPS_NEXT(val); 148 offset += next << 2; 149 } while (next); 150 151 return 0; 152 } 153