xref: /linux/drivers/usb/host/uhci-hcd.h (revision f3d9478b2ce468c3115b02ecae7e975990697f15)
1 #ifndef __LINUX_UHCI_HCD_H
2 #define __LINUX_UHCI_HCD_H
3 
4 #include <linux/list.h>
5 #include <linux/usb.h>
6 
7 #define usb_packetid(pipe)	(usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8 #define PIPE_DEVEP_MASK		0x0007ff00
9 
10 
11 /*
12  * Universal Host Controller Interface data structures and defines
13  */
14 
15 /* Command register */
16 #define USBCMD		0
17 #define   USBCMD_RS		0x0001	/* Run/Stop */
18 #define   USBCMD_HCRESET	0x0002	/* Host reset */
19 #define   USBCMD_GRESET		0x0004	/* Global reset */
20 #define   USBCMD_EGSM		0x0008	/* Global Suspend Mode */
21 #define   USBCMD_FGR		0x0010	/* Force Global Resume */
22 #define   USBCMD_SWDBG		0x0020	/* SW Debug mode */
23 #define   USBCMD_CF		0x0040	/* Config Flag (sw only) */
24 #define   USBCMD_MAXP		0x0080	/* Max Packet (0 = 32, 1 = 64) */
25 
26 /* Status register */
27 #define USBSTS		2
28 #define   USBSTS_USBINT		0x0001	/* Interrupt due to IOC */
29 #define   USBSTS_ERROR		0x0002	/* Interrupt due to error */
30 #define   USBSTS_RD		0x0004	/* Resume Detect */
31 #define   USBSTS_HSE		0x0008	/* Host System Error: PCI problems */
32 #define   USBSTS_HCPE		0x0010	/* Host Controller Process Error:
33 					 * the schedule is buggy */
34 #define   USBSTS_HCH		0x0020	/* HC Halted */
35 
36 /* Interrupt enable register */
37 #define USBINTR		4
38 #define   USBINTR_TIMEOUT	0x0001	/* Timeout/CRC error enable */
39 #define   USBINTR_RESUME	0x0002	/* Resume interrupt enable */
40 #define   USBINTR_IOC		0x0004	/* Interrupt On Complete enable */
41 #define   USBINTR_SP		0x0008	/* Short packet interrupt enable */
42 
43 #define USBFRNUM	6
44 #define USBFLBASEADD	8
45 #define USBSOF		12
46 #define   USBSOF_DEFAULT	64	/* Frame length is exactly 1 ms */
47 
48 /* USB port status and control registers */
49 #define USBPORTSC1	16
50 #define USBPORTSC2	18
51 #define   USBPORTSC_CCS		0x0001	/* Current Connect Status
52 					 * ("device present") */
53 #define   USBPORTSC_CSC		0x0002	/* Connect Status Change */
54 #define   USBPORTSC_PE		0x0004	/* Port Enable */
55 #define   USBPORTSC_PEC		0x0008	/* Port Enable Change */
56 #define   USBPORTSC_DPLUS	0x0010	/* D+ high (line status) */
57 #define   USBPORTSC_DMINUS	0x0020	/* D- high (line status) */
58 #define   USBPORTSC_RD		0x0040	/* Resume Detect */
59 #define   USBPORTSC_RES1	0x0080	/* reserved, always 1 */
60 #define   USBPORTSC_LSDA	0x0100	/* Low Speed Device Attached */
61 #define   USBPORTSC_PR		0x0200	/* Port Reset */
62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
63 #define   USBPORTSC_OC		0x0400	/* Over Current condition */
64 #define   USBPORTSC_OCC		0x0800	/* Over Current Change R/WC */
65 #define   USBPORTSC_SUSP	0x1000	/* Suspend */
66 #define   USBPORTSC_RES2	0x2000	/* reserved, write zeroes */
67 #define   USBPORTSC_RES3	0x4000	/* reserved, write zeroes */
68 #define   USBPORTSC_RES4	0x8000	/* reserved, write zeroes */
69 
70 /* Legacy support register */
71 #define USBLEGSUP		0xc0
72 #define   USBLEGSUP_DEFAULT	0x2000	/* only PIRQ enable set */
73 #define   USBLEGSUP_RWC		0x8f00	/* the R/WC bits */
74 #define   USBLEGSUP_RO		0x5040	/* R/O and reserved bits */
75 
76 #define UHCI_PTR_BITS		__constant_cpu_to_le32(0x000F)
77 #define UHCI_PTR_TERM		__constant_cpu_to_le32(0x0001)
78 #define UHCI_PTR_QH		__constant_cpu_to_le32(0x0002)
79 #define UHCI_PTR_DEPTH		__constant_cpu_to_le32(0x0004)
80 #define UHCI_PTR_BREADTH	__constant_cpu_to_le32(0x0000)
81 
82 #define UHCI_NUMFRAMES		1024	/* in the frame list [array] */
83 #define UHCI_MAX_SOF_NUMBER	2047	/* in an SOF packet */
84 #define CAN_SCHEDULE_FRAMES	1000	/* how far in the future frames
85 					 * can be scheduled */
86 
87 /* When no queues need Full-Speed Bandwidth Reclamation,
88  * delay this long before turning FSBR off */
89 #define FSBR_OFF_DELAY		msecs_to_jiffies(10)
90 
91 /* If a queue hasn't advanced after this much time, assume it is stuck */
92 #define QH_WAIT_TIMEOUT		msecs_to_jiffies(200)
93 
94 
95 /*
96  *	Queue Headers
97  */
98 
99 /*
100  * One role of a QH is to hold a queue of TDs for some endpoint.  One QH goes
101  * with each endpoint, and qh->element (updated by the HC) is either:
102  *   - the next unprocessed TD in the endpoint's queue, or
103  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
104  *
105  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
106  * can easily splice a QH for some endpoint into the schedule at the right
107  * place.  Then qh->element is UHCI_PTR_TERM.
108  *
109  * In the schedule, qh->link maintains a list of QHs seen by the HC:
110  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
111  *
112  * qh->node is the software equivalent of qh->link.  The differences
113  * are that the software list is doubly-linked and QHs in the UNLINKING
114  * state are on the software list but not the hardware schedule.
115  *
116  * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
117  * but they never get added to the hardware schedule.
118  */
119 #define QH_STATE_IDLE		1	/* QH is not being used */
120 #define QH_STATE_UNLINKING	2	/* QH has been removed from the
121 					 * schedule but the hardware may
122 					 * still be using it */
123 #define QH_STATE_ACTIVE		3	/* QH is on the schedule */
124 
125 struct uhci_qh {
126 	/* Hardware fields */
127 	__le32 link;			/* Next QH in the schedule */
128 	__le32 element;			/* Queue element (TD) pointer */
129 
130 	/* Software fields */
131 	struct list_head node;		/* Node in the list of QHs */
132 	struct usb_host_endpoint *hep;	/* Endpoint information */
133 	struct usb_device *udev;
134 	struct list_head queue;		/* Queue of urbps for this QH */
135 	struct uhci_qh *skel;		/* Skeleton for this QH */
136 	struct uhci_td *dummy_td;	/* Dummy TD to end the queue */
137 	struct uhci_td *post_td;	/* Last TD completed */
138 
139 	struct usb_iso_packet_descriptor *iso_packet_desc;
140 					/* Next urb->iso_frame_desc entry */
141 	unsigned long advance_jiffies;	/* Time of last queue advance */
142 	unsigned int unlink_frame;	/* When the QH was unlinked */
143 	unsigned int period;		/* For Interrupt and Isochronous QHs */
144 	unsigned int iso_frame;		/* Frame # for iso_packet_desc */
145 	int iso_status;			/* Status for Isochronous URBs */
146 
147 	int state;			/* QH_STATE_xxx; see above */
148 	int type;			/* Queue type (control, bulk, etc) */
149 
150 	dma_addr_t dma_handle;
151 
152 	unsigned int initial_toggle:1;	/* Endpoint's current toggle value */
153 	unsigned int needs_fixup:1;	/* Must fix the TD toggle values */
154 	unsigned int is_stopped:1;	/* Queue was stopped by error/unlink */
155 	unsigned int wait_expired:1;	/* QH_WAIT_TIMEOUT has expired */
156 } __attribute__((aligned(16)));
157 
158 /*
159  * We need a special accessor for the element pointer because it is
160  * subject to asynchronous updates by the controller.
161  */
162 static inline __le32 qh_element(struct uhci_qh *qh) {
163 	__le32 element = qh->element;
164 
165 	barrier();
166 	return element;
167 }
168 
169 
170 /*
171  *	Transfer Descriptors
172  */
173 
174 /*
175  * for TD <status>:
176  */
177 #define TD_CTRL_SPD		(1 << 29)	/* Short Packet Detect */
178 #define TD_CTRL_C_ERR_MASK	(3 << 27)	/* Error Counter bits */
179 #define TD_CTRL_C_ERR_SHIFT	27
180 #define TD_CTRL_LS		(1 << 26)	/* Low Speed Device */
181 #define TD_CTRL_IOS		(1 << 25)	/* Isochronous Select */
182 #define TD_CTRL_IOC		(1 << 24)	/* Interrupt on Complete */
183 #define TD_CTRL_ACTIVE		(1 << 23)	/* TD Active */
184 #define TD_CTRL_STALLED		(1 << 22)	/* TD Stalled */
185 #define TD_CTRL_DBUFERR		(1 << 21)	/* Data Buffer Error */
186 #define TD_CTRL_BABBLE		(1 << 20)	/* Babble Detected */
187 #define TD_CTRL_NAK		(1 << 19)	/* NAK Received */
188 #define TD_CTRL_CRCTIMEO	(1 << 18)	/* CRC/Time Out Error */
189 #define TD_CTRL_BITSTUFF	(1 << 17)	/* Bit Stuff Error */
190 #define TD_CTRL_ACTLEN_MASK	0x7FF	/* actual length, encoded as n - 1 */
191 
192 #define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
193 				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
194 				 TD_CTRL_BITSTUFF)
195 
196 #define uhci_maxerr(err)		((err) << TD_CTRL_C_ERR_SHIFT)
197 #define uhci_status_bits(ctrl_sts)	((ctrl_sts) & 0xF60000)
198 #define uhci_actual_length(ctrl_sts)	(((ctrl_sts) + 1) & \
199 			TD_CTRL_ACTLEN_MASK)	/* 1-based */
200 
201 /*
202  * for TD <info>: (a.k.a. Token)
203  */
204 #define td_token(td)		le32_to_cpu((td)->token)
205 #define TD_TOKEN_DEVADDR_SHIFT	8
206 #define TD_TOKEN_TOGGLE_SHIFT	19
207 #define TD_TOKEN_TOGGLE		(1 << 19)
208 #define TD_TOKEN_EXPLEN_SHIFT	21
209 #define TD_TOKEN_EXPLEN_MASK	0x7FF	/* expected length, encoded as n-1 */
210 #define TD_TOKEN_PID_MASK	0xFF
211 
212 #define uhci_explen(len)	((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
213 					TD_TOKEN_EXPLEN_SHIFT)
214 
215 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
216 					1) & TD_TOKEN_EXPLEN_MASK)
217 #define uhci_toggle(token)	(((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
218 #define uhci_endpoint(token)	(((token) >> 15) & 0xf)
219 #define uhci_devaddr(token)	(((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
220 #define uhci_devep(token)	(((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
221 #define uhci_packetid(token)	((token) & TD_TOKEN_PID_MASK)
222 #define uhci_packetout(token)	(uhci_packetid(token) != USB_PID_IN)
223 #define uhci_packetin(token)	(uhci_packetid(token) == USB_PID_IN)
224 
225 /*
226  * The documentation says "4 words for hardware, 4 words for software".
227  *
228  * That's silly, the hardware doesn't care. The hardware only cares that
229  * the hardware words are 16-byte aligned, and we can have any amount of
230  * sw space after the TD entry.
231  *
232  * td->link points to either another TD (not necessarily for the same urb or
233  * even the same endpoint), or nothing (PTR_TERM), or a QH.
234  */
235 struct uhci_td {
236 	/* Hardware fields */
237 	__le32 link;
238 	__le32 status;
239 	__le32 token;
240 	__le32 buffer;
241 
242 	/* Software fields */
243 	dma_addr_t dma_handle;
244 
245 	struct list_head list;
246 
247 	int frame;			/* for iso: what frame? */
248 	struct list_head fl_list;
249 } __attribute__((aligned(16)));
250 
251 /*
252  * We need a special accessor for the control/status word because it is
253  * subject to asynchronous updates by the controller.
254  */
255 static inline u32 td_status(struct uhci_td *td) {
256 	__le32 status = td->status;
257 
258 	barrier();
259 	return le32_to_cpu(status);
260 }
261 
262 
263 /*
264  *	Skeleton Queue Headers
265  */
266 
267 /*
268  * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
269  * automatic queuing. To make it easy to insert entries into the schedule,
270  * we have a skeleton of QHs for each predefined Interrupt latency,
271  * low-speed control, full-speed control, bulk, and terminating QH
272  * (see explanation for the terminating QH below).
273  *
274  * When we want to add a new QH, we add it to the end of the list for the
275  * skeleton QH.  For instance, the schedule list can look like this:
276  *
277  * skel int128 QH
278  * dev 1 interrupt QH
279  * dev 5 interrupt QH
280  * skel int64 QH
281  * skel int32 QH
282  * ...
283  * skel int1 QH
284  * skel low-speed control QH
285  * dev 5 control QH
286  * skel full-speed control QH
287  * skel bulk QH
288  * dev 1 bulk QH
289  * dev 2 bulk QH
290  * skel terminating QH
291  *
292  * The terminating QH is used for 2 reasons:
293  * - To place a terminating TD which is used to workaround a PIIX bug
294  *   (see Intel errata for explanation), and
295  * - To loop back to the full-speed control queue for full-speed bandwidth
296  *   reclamation.
297  *
298  * There's a special skeleton QH for Isochronous QHs.  It never appears
299  * on the schedule, and Isochronous TDs go on the schedule before the
300  * the skeleton QHs.  The hardware accesses them directly rather than
301  * through their QH, which is used only for bookkeeping purposes.
302  * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
303  * it doesn't use them either.  And the spec says that queues never
304  * advance on an error completion status, which makes them totally
305  * unsuitable for Isochronous transfers.
306  */
307 
308 #define UHCI_NUM_SKELQH		14
309 #define skel_unlink_qh		skelqh[0]
310 #define skel_iso_qh		skelqh[1]
311 #define skel_int128_qh		skelqh[2]
312 #define skel_int64_qh		skelqh[3]
313 #define skel_int32_qh		skelqh[4]
314 #define skel_int16_qh		skelqh[5]
315 #define skel_int8_qh		skelqh[6]
316 #define skel_int4_qh		skelqh[7]
317 #define skel_int2_qh		skelqh[8]
318 #define skel_int1_qh		skelqh[9]
319 #define skel_ls_control_qh	skelqh[10]
320 #define skel_fs_control_qh	skelqh[11]
321 #define skel_bulk_qh		skelqh[12]
322 #define skel_term_qh		skelqh[13]
323 
324 /* Find the skelqh entry corresponding to an interval exponent */
325 #define UHCI_SKEL_INDEX(exponent)	(9 - exponent)
326 
327 
328 /*
329  *	The UHCI controller and root hub
330  */
331 
332 /*
333  * States for the root hub:
334  *
335  * To prevent "bouncing" in the presence of electrical noise,
336  * when there are no devices attached we delay for 1 second in the
337  * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
338  *
339  * (Note that the AUTO_STOPPED state won't be necessary once the hub
340  * driver learns to autosuspend.)
341  */
342 enum uhci_rh_state {
343 	/* In the following states the HC must be halted.
344 	 * These two must come first. */
345 	UHCI_RH_RESET,
346 	UHCI_RH_SUSPENDED,
347 
348 	UHCI_RH_AUTO_STOPPED,
349 	UHCI_RH_RESUMING,
350 
351 	/* In this state the HC changes from running to halted,
352 	 * so it can legally appear either way. */
353 	UHCI_RH_SUSPENDING,
354 
355 	/* In the following states it's an error if the HC is halted.
356 	 * These two must come last. */
357 	UHCI_RH_RUNNING,		/* The normal state */
358 	UHCI_RH_RUNNING_NODEVS,		/* Running with no devices attached */
359 };
360 
361 /*
362  * The full UHCI controller information:
363  */
364 struct uhci_hcd {
365 
366 	/* debugfs */
367 	struct dentry *dentry;
368 
369 	/* Grabbed from PCI */
370 	unsigned long io_addr;
371 
372 	struct dma_pool *qh_pool;
373 	struct dma_pool *td_pool;
374 
375 	struct uhci_td *term_td;	/* Terminating TD, see UHCI bug */
376 	struct uhci_qh *skelqh[UHCI_NUM_SKELQH];	/* Skeleton QHs */
377 	struct uhci_qh *next_qh;	/* Next QH to scan */
378 
379 	spinlock_t lock;
380 
381 	dma_addr_t frame_dma_handle;	/* Hardware frame list */
382 	__le32 *frame;
383 	void **frame_cpu;		/* CPU's frame list */
384 
385 	enum uhci_rh_state rh_state;
386 	unsigned long auto_stop_time;		/* When to AUTO_STOP */
387 
388 	unsigned int frame_number;		/* As of last check */
389 	unsigned int is_stopped;
390 #define UHCI_IS_STOPPED		9999		/* Larger than a frame # */
391 	unsigned int last_iso_frame;		/* Frame of last scan */
392 	unsigned int cur_iso_frame;		/* Frame for current scan */
393 
394 	unsigned int scan_in_progress:1;	/* Schedule scan is running */
395 	unsigned int need_rescan:1;		/* Redo the schedule scan */
396 	unsigned int dead:1;			/* Controller has died */
397 	unsigned int working_RD:1;		/* Suspended root hub doesn't
398 						   need to be polled */
399 	unsigned int is_initialized:1;		/* Data structure is usable */
400 	unsigned int fsbr_is_on:1;		/* FSBR is turned on */
401 	unsigned int fsbr_is_wanted:1;		/* Does any URB want FSBR? */
402 	unsigned int fsbr_expiring:1;		/* FSBR is timing out */
403 
404 	struct timer_list fsbr_timer;		/* For turning off FBSR */
405 
406 	/* Support for port suspend/resume/reset */
407 	unsigned long port_c_suspend;		/* Bit-arrays of ports */
408 	unsigned long resuming_ports;
409 	unsigned long ports_timeout;		/* Time to stop signalling */
410 
411 	struct list_head idle_qh_list;		/* Where the idle QHs live */
412 
413 	int rh_numports;			/* Number of root-hub ports */
414 
415 	wait_queue_head_t waitqh;		/* endpoint_disable waiters */
416 	int num_waiting;			/* Number of waiters */
417 };
418 
419 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
420 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
421 {
422 	return (struct uhci_hcd *) (hcd->hcd_priv);
423 }
424 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
425 {
426 	return container_of((void *) uhci, struct usb_hcd, hcd_priv);
427 }
428 
429 #define uhci_dev(u)	(uhci_to_hcd(u)->self.controller)
430 
431 /* Utility macro for comparing frame numbers */
432 #define uhci_frame_before_eq(f1, f2)	(0 <= (int) ((f2) - (f1)))
433 
434 
435 /*
436  *	Private per-URB data
437  */
438 struct urb_priv {
439 	struct list_head node;		/* Node in the QH's urbp list */
440 
441 	struct urb *urb;
442 
443 	struct uhci_qh *qh;		/* QH for this URB */
444 	struct list_head td_list;
445 
446 	unsigned fsbr:1;		/* URB wants FSBR */
447 };
448 
449 
450 /*
451  * Locking in uhci.c
452  *
453  * Almost everything relating to the hardware schedule and processing
454  * of URBs is protected by uhci->lock.  urb->status is protected by
455  * urb->lock; that's the one exception.
456  *
457  * To prevent deadlocks, never lock uhci->lock while holding urb->lock.
458  * The safe order of locking is:
459  *
460  * #1 uhci->lock
461  * #2 urb->lock
462  */
463 
464 
465 /* Some special IDs */
466 
467 #define PCI_VENDOR_ID_GENESYS		0x17a0
468 #define PCI_DEVICE_ID_GL880S_UHCI	0x8083
469 
470 #endif
471