1 /* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at 13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface 14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). 15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) 16 * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu 17 * 18 * Intel documents this fairly well, and as far as I know there 19 * are no royalties or anything like that, but even so there are 20 * people who decided that they want to do the same thing in a 21 * completely different way. 22 * 23 */ 24 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/kernel.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/ioport.h> 31 #include <linux/sched.h> 32 #include <linux/slab.h> 33 #include <linux/errno.h> 34 #include <linux/unistd.h> 35 #include <linux/interrupt.h> 36 #include <linux/spinlock.h> 37 #include <linux/debugfs.h> 38 #include <linux/pm.h> 39 #include <linux/dmapool.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/usb.h> 42 #include <linux/bitops.h> 43 44 #include <asm/uaccess.h> 45 #include <asm/io.h> 46 #include <asm/irq.h> 47 #include <asm/system.h> 48 49 #include "../core/hcd.h" 50 #include "uhci-hcd.h" 51 #include "pci-quirks.h" 52 53 /* 54 * Version Information 55 */ 56 #define DRIVER_VERSION "v3.0" 57 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ 58 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ 59 Alan Stern" 60 #define DRIVER_DESC "USB Universal Host Controller Interface driver" 61 62 /* 63 * debug = 0, no debugging messages 64 * debug = 1, dump failed URBs except for stalls 65 * debug = 2, dump all failed URBs (including stalls) 66 * show all queues in /debug/uhci/[pci_addr] 67 * debug = 3, show all TDs in URBs when dumping 68 */ 69 #ifdef DEBUG 70 #define DEBUG_CONFIGURED 1 71 static int debug = 1; 72 module_param(debug, int, S_IRUGO | S_IWUSR); 73 MODULE_PARM_DESC(debug, "Debug level"); 74 75 #else 76 #define DEBUG_CONFIGURED 0 77 #define debug 0 78 #endif 79 80 static char *errbuf; 81 #define ERRBUF_LEN (32 * 1024) 82 83 static kmem_cache_t *uhci_up_cachep; /* urb_priv */ 84 85 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); 86 static void wakeup_rh(struct uhci_hcd *uhci); 87 static void uhci_get_current_frame_number(struct uhci_hcd *uhci); 88 89 #include "uhci-debug.c" 90 #include "uhci-q.c" 91 #include "uhci-hub.c" 92 93 /* 94 * Finish up a host controller reset and update the recorded state. 95 */ 96 static void finish_reset(struct uhci_hcd *uhci) 97 { 98 int port; 99 100 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect 101 * bits in the port status and control registers. 102 * We have to clear them by hand. 103 */ 104 for (port = 0; port < uhci->rh_numports; ++port) 105 outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); 106 107 uhci->port_c_suspend = uhci->resuming_ports = 0; 108 uhci->rh_state = UHCI_RH_RESET; 109 uhci->is_stopped = UHCI_IS_STOPPED; 110 uhci_to_hcd(uhci)->state = HC_STATE_HALT; 111 uhci_to_hcd(uhci)->poll_rh = 0; 112 113 uhci->dead = 0; /* Full reset resurrects the controller */ 114 } 115 116 /* 117 * Last rites for a defunct/nonfunctional controller 118 * or one we don't want to use any more. 119 */ 120 static void uhci_hc_died(struct uhci_hcd *uhci) 121 { 122 uhci_get_current_frame_number(uhci); 123 uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); 124 finish_reset(uhci); 125 uhci->dead = 1; 126 127 /* The current frame may already be partway finished */ 128 ++uhci->frame_number; 129 } 130 131 /* 132 * Initialize a controller that was newly discovered or has lost power 133 * or otherwise been reset while it was suspended. In none of these cases 134 * can we be sure of its previous state. 135 */ 136 static void check_and_reset_hc(struct uhci_hcd *uhci) 137 { 138 if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr)) 139 finish_reset(uhci); 140 } 141 142 /* 143 * Store the basic register settings needed by the controller. 144 */ 145 static void configure_hc(struct uhci_hcd *uhci) 146 { 147 /* Set the frame length to the default: 1 ms exactly */ 148 outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); 149 150 /* Store the frame list base address */ 151 outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); 152 153 /* Set the current frame number */ 154 outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, 155 uhci->io_addr + USBFRNUM); 156 157 /* Mark controller as not halted before we enable interrupts */ 158 uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED; 159 mb(); 160 161 /* Enable PIRQ */ 162 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 163 USBLEGSUP_DEFAULT); 164 } 165 166 167 static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) 168 { 169 int port; 170 171 switch (to_pci_dev(uhci_dev(uhci))->vendor) { 172 default: 173 break; 174 175 case PCI_VENDOR_ID_GENESYS: 176 /* Genesys Logic's GL880S controllers don't generate 177 * resume-detect interrupts. 178 */ 179 return 1; 180 181 case PCI_VENDOR_ID_INTEL: 182 /* Some of Intel's USB controllers have a bug that causes 183 * resume-detect interrupts if any port has an over-current 184 * condition. To make matters worse, some motherboards 185 * hardwire unused USB ports' over-current inputs active! 186 * To prevent problems, we will not enable resume-detect 187 * interrupts if any ports are OC. 188 */ 189 for (port = 0; port < uhci->rh_numports; ++port) { 190 if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & 191 USBPORTSC_OC) 192 return 1; 193 } 194 break; 195 } 196 return 0; 197 } 198 199 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) 200 __releases(uhci->lock) 201 __acquires(uhci->lock) 202 { 203 int auto_stop; 204 int int_enable; 205 206 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); 207 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, 208 "%s%s\n", __FUNCTION__, 209 (auto_stop ? " (auto-stop)" : "")); 210 211 /* If we get a suspend request when we're already auto-stopped 212 * then there's nothing to do. 213 */ 214 if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) { 215 uhci->rh_state = new_state; 216 return; 217 } 218 219 /* Enable resume-detect interrupts if they work. 220 * Then enter Global Suspend mode, still configured. 221 */ 222 uhci->working_RD = 1; 223 int_enable = USBINTR_RESUME; 224 if (resume_detect_interrupts_are_broken(uhci)) { 225 uhci->working_RD = int_enable = 0; 226 } 227 outw(int_enable, uhci->io_addr + USBINTR); 228 outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD); 229 mb(); 230 udelay(5); 231 232 /* If we're auto-stopping then no devices have been attached 233 * for a while, so there shouldn't be any active URBs and the 234 * controller should stop after a few microseconds. Otherwise 235 * we will give the controller one frame to stop. 236 */ 237 if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { 238 uhci->rh_state = UHCI_RH_SUSPENDING; 239 spin_unlock_irq(&uhci->lock); 240 msleep(1); 241 spin_lock_irq(&uhci->lock); 242 if (uhci->dead) 243 return; 244 } 245 if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) 246 dev_warn(&uhci_to_hcd(uhci)->self.root_hub->dev, 247 "Controller not stopped yet!\n"); 248 249 uhci_get_current_frame_number(uhci); 250 251 uhci->rh_state = new_state; 252 uhci->is_stopped = UHCI_IS_STOPPED; 253 uhci_to_hcd(uhci)->poll_rh = !int_enable; 254 255 uhci_scan_schedule(uhci, NULL); 256 uhci_fsbr_off(uhci); 257 } 258 259 static void start_rh(struct uhci_hcd *uhci) 260 { 261 uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; 262 uhci->is_stopped = 0; 263 264 /* Mark it configured and running with a 64-byte max packet. 265 * All interrupts are enabled, even though RESUME won't do anything. 266 */ 267 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); 268 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, 269 uhci->io_addr + USBINTR); 270 mb(); 271 uhci->rh_state = UHCI_RH_RUNNING; 272 uhci_to_hcd(uhci)->poll_rh = 1; 273 } 274 275 static void wakeup_rh(struct uhci_hcd *uhci) 276 __releases(uhci->lock) 277 __acquires(uhci->lock) 278 { 279 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, 280 "%s%s\n", __FUNCTION__, 281 uhci->rh_state == UHCI_RH_AUTO_STOPPED ? 282 " (auto-start)" : ""); 283 284 /* If we are auto-stopped then no devices are attached so there's 285 * no need for wakeup signals. Otherwise we send Global Resume 286 * for 20 ms. 287 */ 288 if (uhci->rh_state == UHCI_RH_SUSPENDED) { 289 uhci->rh_state = UHCI_RH_RESUMING; 290 outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF, 291 uhci->io_addr + USBCMD); 292 spin_unlock_irq(&uhci->lock); 293 msleep(20); 294 spin_lock_irq(&uhci->lock); 295 if (uhci->dead) 296 return; 297 298 /* End Global Resume and wait for EOP to be sent */ 299 outw(USBCMD_CF, uhci->io_addr + USBCMD); 300 mb(); 301 udelay(4); 302 if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) 303 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); 304 } 305 306 start_rh(uhci); 307 308 /* Restart root hub polling */ 309 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); 310 } 311 312 static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) 313 { 314 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 315 unsigned short status; 316 unsigned long flags; 317 318 /* 319 * Read the interrupt status, and write it back to clear the 320 * interrupt cause. Contrary to the UHCI specification, the 321 * "HC Halted" status bit is persistent: it is RO, not R/WC. 322 */ 323 status = inw(uhci->io_addr + USBSTS); 324 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ 325 return IRQ_NONE; 326 outw(status, uhci->io_addr + USBSTS); /* Clear it */ 327 328 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { 329 if (status & USBSTS_HSE) 330 dev_err(uhci_dev(uhci), "host system error, " 331 "PCI problems?\n"); 332 if (status & USBSTS_HCPE) 333 dev_err(uhci_dev(uhci), "host controller process " 334 "error, something bad happened!\n"); 335 if (status & USBSTS_HCH) { 336 spin_lock_irqsave(&uhci->lock, flags); 337 if (uhci->rh_state >= UHCI_RH_RUNNING) { 338 dev_err(uhci_dev(uhci), 339 "host controller halted, " 340 "very bad!\n"); 341 if (debug > 1 && errbuf) { 342 /* Print the schedule for debugging */ 343 uhci_sprint_schedule(uhci, 344 errbuf, ERRBUF_LEN); 345 lprintk(errbuf); 346 } 347 uhci_hc_died(uhci); 348 349 /* Force a callback in case there are 350 * pending unlinks */ 351 mod_timer(&hcd->rh_timer, jiffies); 352 } 353 spin_unlock_irqrestore(&uhci->lock, flags); 354 } 355 } 356 357 if (status & USBSTS_RD) 358 usb_hcd_poll_rh_status(hcd); 359 else { 360 spin_lock_irqsave(&uhci->lock, flags); 361 uhci_scan_schedule(uhci, regs); 362 spin_unlock_irqrestore(&uhci->lock, flags); 363 } 364 365 return IRQ_HANDLED; 366 } 367 368 /* 369 * Store the current frame number in uhci->frame_number if the controller 370 * is runnning. Expand from 11 bits (of which we use only 10) to a 371 * full-sized integer. 372 * 373 * Like many other parts of the driver, this code relies on being polled 374 * more than once per second as long as the controller is running. 375 */ 376 static void uhci_get_current_frame_number(struct uhci_hcd *uhci) 377 { 378 if (!uhci->is_stopped) { 379 unsigned delta; 380 381 delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & 382 (UHCI_NUMFRAMES - 1); 383 uhci->frame_number += delta; 384 } 385 } 386 387 /* 388 * De-allocate all resources 389 */ 390 static void release_uhci(struct uhci_hcd *uhci) 391 { 392 int i; 393 394 if (DEBUG_CONFIGURED) { 395 spin_lock_irq(&uhci->lock); 396 uhci->is_initialized = 0; 397 spin_unlock_irq(&uhci->lock); 398 399 debugfs_remove(uhci->dentry); 400 } 401 402 for (i = 0; i < UHCI_NUM_SKELQH; i++) 403 uhci_free_qh(uhci, uhci->skelqh[i]); 404 405 uhci_free_td(uhci, uhci->term_td); 406 407 dma_pool_destroy(uhci->qh_pool); 408 409 dma_pool_destroy(uhci->td_pool); 410 411 kfree(uhci->frame_cpu); 412 413 dma_free_coherent(uhci_dev(uhci), 414 UHCI_NUMFRAMES * sizeof(*uhci->frame), 415 uhci->frame, uhci->frame_dma_handle); 416 } 417 418 static int uhci_init(struct usb_hcd *hcd) 419 { 420 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 421 unsigned io_size = (unsigned) hcd->rsrc_len; 422 int port; 423 424 uhci->io_addr = (unsigned long) hcd->rsrc_start; 425 426 /* The UHCI spec says devices must have 2 ports, and goes on to say 427 * they may have more but gives no way to determine how many there 428 * are. However according to the UHCI spec, Bit 7 of the port 429 * status and control register is always set to 1. So we try to 430 * use this to our advantage. Another common failure mode when 431 * a nonexistent register is addressed is to return all ones, so 432 * we test for that also. 433 */ 434 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { 435 unsigned int portstatus; 436 437 portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); 438 if (!(portstatus & 0x0080) || portstatus == 0xffff) 439 break; 440 } 441 if (debug) 442 dev_info(uhci_dev(uhci), "detected %d ports\n", port); 443 444 /* Anything greater than 7 is weird so we'll ignore it. */ 445 if (port > UHCI_RH_MAXCHILD) { 446 dev_info(uhci_dev(uhci), "port count misdetected? " 447 "forcing to 2 ports\n"); 448 port = 2; 449 } 450 uhci->rh_numports = port; 451 452 /* Kick BIOS off this hardware and reset if the controller 453 * isn't already safely quiescent. 454 */ 455 check_and_reset_hc(uhci); 456 return 0; 457 } 458 459 /* Make sure the controller is quiescent and that we're not using it 460 * any more. This is mainly for the benefit of programs which, like kexec, 461 * expect the hardware to be idle: not doing DMA or generating IRQs. 462 * 463 * This routine may be called in a damaged or failing kernel. Hence we 464 * do not acquire the spinlock before shutting down the controller. 465 */ 466 static void uhci_shutdown(struct pci_dev *pdev) 467 { 468 struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev); 469 470 uhci_hc_died(hcd_to_uhci(hcd)); 471 } 472 473 /* 474 * Allocate a frame list, and then setup the skeleton 475 * 476 * The hardware doesn't really know any difference 477 * in the queues, but the order does matter for the 478 * protocols higher up. The order is: 479 * 480 * - any isochronous events handled before any 481 * of the queues. We don't do that here, because 482 * we'll create the actual TD entries on demand. 483 * - The first queue is the interrupt queue. 484 * - The second queue is the control queue, split into low- and full-speed 485 * - The third queue is bulk queue. 486 * - The fourth queue is the bandwidth reclamation queue, which loops back 487 * to the full-speed control queue. 488 */ 489 static int uhci_start(struct usb_hcd *hcd) 490 { 491 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 492 int retval = -EBUSY; 493 int i; 494 struct dentry *dentry; 495 496 hcd->uses_new_polling = 1; 497 498 spin_lock_init(&uhci->lock); 499 setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, 500 (unsigned long) uhci); 501 INIT_LIST_HEAD(&uhci->idle_qh_list); 502 init_waitqueue_head(&uhci->waitqh); 503 504 if (DEBUG_CONFIGURED) { 505 dentry = debugfs_create_file(hcd->self.bus_name, 506 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, 507 uhci, &uhci_debug_operations); 508 if (!dentry) { 509 dev_err(uhci_dev(uhci), "couldn't create uhci " 510 "debugfs entry\n"); 511 retval = -ENOMEM; 512 goto err_create_debug_entry; 513 } 514 uhci->dentry = dentry; 515 } 516 517 uhci->frame = dma_alloc_coherent(uhci_dev(uhci), 518 UHCI_NUMFRAMES * sizeof(*uhci->frame), 519 &uhci->frame_dma_handle, 0); 520 if (!uhci->frame) { 521 dev_err(uhci_dev(uhci), "unable to allocate " 522 "consistent memory for frame list\n"); 523 goto err_alloc_frame; 524 } 525 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); 526 527 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), 528 GFP_KERNEL); 529 if (!uhci->frame_cpu) { 530 dev_err(uhci_dev(uhci), "unable to allocate " 531 "memory for frame pointers\n"); 532 goto err_alloc_frame_cpu; 533 } 534 535 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), 536 sizeof(struct uhci_td), 16, 0); 537 if (!uhci->td_pool) { 538 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); 539 goto err_create_td_pool; 540 } 541 542 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), 543 sizeof(struct uhci_qh), 16, 0); 544 if (!uhci->qh_pool) { 545 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); 546 goto err_create_qh_pool; 547 } 548 549 uhci->term_td = uhci_alloc_td(uhci); 550 if (!uhci->term_td) { 551 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); 552 goto err_alloc_term_td; 553 } 554 555 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 556 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); 557 if (!uhci->skelqh[i]) { 558 dev_err(uhci_dev(uhci), "unable to allocate QH\n"); 559 goto err_alloc_skelqh; 560 } 561 } 562 563 /* 564 * 8 Interrupt queues; link all higher int queues to int1, 565 * then link int1 to control and control to bulk 566 */ 567 uhci->skel_int128_qh->link = 568 uhci->skel_int64_qh->link = 569 uhci->skel_int32_qh->link = 570 uhci->skel_int16_qh->link = 571 uhci->skel_int8_qh->link = 572 uhci->skel_int4_qh->link = 573 uhci->skel_int2_qh->link = UHCI_PTR_QH | 574 cpu_to_le32(uhci->skel_int1_qh->dma_handle); 575 576 uhci->skel_int1_qh->link = UHCI_PTR_QH | 577 cpu_to_le32(uhci->skel_ls_control_qh->dma_handle); 578 uhci->skel_ls_control_qh->link = UHCI_PTR_QH | 579 cpu_to_le32(uhci->skel_fs_control_qh->dma_handle); 580 uhci->skel_fs_control_qh->link = UHCI_PTR_QH | 581 cpu_to_le32(uhci->skel_bulk_qh->dma_handle); 582 uhci->skel_bulk_qh->link = UHCI_PTR_QH | 583 cpu_to_le32(uhci->skel_term_qh->dma_handle); 584 585 /* This dummy TD is to work around a bug in Intel PIIX controllers */ 586 uhci_fill_td(uhci->term_td, 0, uhci_explen(0) | 587 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); 588 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); 589 590 uhci->skel_term_qh->link = UHCI_PTR_TERM; 591 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); 592 593 /* 594 * Fill the frame list: make all entries point to the proper 595 * interrupt queue. 596 * 597 * The interrupt queues will be interleaved as evenly as possible. 598 * There's not much to be done about period-1 interrupts; they have 599 * to occur in every frame. But we can schedule period-2 interrupts 600 * in odd-numbered frames, period-4 interrupts in frames congruent 601 * to 2 (mod 4), and so on. This way each frame only has two 602 * interrupt QHs, which will help spread out bandwidth utilization. 603 */ 604 for (i = 0; i < UHCI_NUMFRAMES; i++) { 605 int irq; 606 607 /* 608 * ffs (Find First bit Set) does exactly what we need: 609 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[8], 610 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[7], etc. 611 * ffs >= 7 => not on any high-period queue, so use 612 * skel_int1_qh = skelqh[9]. 613 * Add UHCI_NUMFRAMES to insure at least one bit is set. 614 */ 615 irq = 8 - (int) __ffs(i + UHCI_NUMFRAMES); 616 if (irq <= 1) 617 irq = 9; 618 619 /* Only place we don't use the frame list routines */ 620 uhci->frame[i] = UHCI_PTR_QH | 621 cpu_to_le32(uhci->skelqh[irq]->dma_handle); 622 } 623 624 /* 625 * Some architectures require a full mb() to enforce completion of 626 * the memory writes above before the I/O transfers in configure_hc(). 627 */ 628 mb(); 629 630 configure_hc(uhci); 631 uhci->is_initialized = 1; 632 start_rh(uhci); 633 return 0; 634 635 /* 636 * error exits: 637 */ 638 err_alloc_skelqh: 639 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 640 if (uhci->skelqh[i]) 641 uhci_free_qh(uhci, uhci->skelqh[i]); 642 } 643 644 uhci_free_td(uhci, uhci->term_td); 645 646 err_alloc_term_td: 647 dma_pool_destroy(uhci->qh_pool); 648 649 err_create_qh_pool: 650 dma_pool_destroy(uhci->td_pool); 651 652 err_create_td_pool: 653 kfree(uhci->frame_cpu); 654 655 err_alloc_frame_cpu: 656 dma_free_coherent(uhci_dev(uhci), 657 UHCI_NUMFRAMES * sizeof(*uhci->frame), 658 uhci->frame, uhci->frame_dma_handle); 659 660 err_alloc_frame: 661 debugfs_remove(uhci->dentry); 662 663 err_create_debug_entry: 664 return retval; 665 } 666 667 static void uhci_stop(struct usb_hcd *hcd) 668 { 669 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 670 671 spin_lock_irq(&uhci->lock); 672 if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && !uhci->dead) 673 uhci_hc_died(uhci); 674 uhci_scan_schedule(uhci, NULL); 675 spin_unlock_irq(&uhci->lock); 676 677 del_timer_sync(&uhci->fsbr_timer); 678 release_uhci(uhci); 679 } 680 681 #ifdef CONFIG_PM 682 static int uhci_rh_suspend(struct usb_hcd *hcd) 683 { 684 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 685 int rc = 0; 686 687 spin_lock_irq(&uhci->lock); 688 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) 689 rc = -ESHUTDOWN; 690 else if (!uhci->dead) 691 suspend_rh(uhci, UHCI_RH_SUSPENDED); 692 spin_unlock_irq(&uhci->lock); 693 return rc; 694 } 695 696 static int uhci_rh_resume(struct usb_hcd *hcd) 697 { 698 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 699 int rc = 0; 700 701 spin_lock_irq(&uhci->lock); 702 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 703 dev_warn(&hcd->self.root_hub->dev, "HC isn't running!\n"); 704 rc = -ESHUTDOWN; 705 } else if (!uhci->dead) 706 wakeup_rh(uhci); 707 spin_unlock_irq(&uhci->lock); 708 return rc; 709 } 710 711 static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) 712 { 713 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 714 int rc = 0; 715 716 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); 717 718 spin_lock_irq(&uhci->lock); 719 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead) 720 goto done_okay; /* Already suspended or dead */ 721 722 if (uhci->rh_state > UHCI_RH_SUSPENDED) { 723 dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); 724 rc = -EBUSY; 725 goto done; 726 }; 727 728 /* All PCI host controllers are required to disable IRQ generation 729 * at the source, so we must turn off PIRQ. 730 */ 731 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); 732 mb(); 733 hcd->poll_rh = 0; 734 735 /* FIXME: Enable non-PME# remote wakeup? */ 736 737 done_okay: 738 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 739 done: 740 spin_unlock_irq(&uhci->lock); 741 return rc; 742 } 743 744 static int uhci_resume(struct usb_hcd *hcd) 745 { 746 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 747 748 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); 749 750 /* Since we aren't in D3 any more, it's safe to set this flag 751 * even if the controller was dead. 752 */ 753 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 754 mb(); 755 756 spin_lock_irq(&uhci->lock); 757 758 /* FIXME: Disable non-PME# remote wakeup? */ 759 760 /* The firmware or a boot kernel may have changed the controller 761 * settings during a system wakeup. Check it and reconfigure 762 * to avoid problems. 763 */ 764 check_and_reset_hc(uhci); 765 766 /* If the controller was dead before, it's back alive now */ 767 configure_hc(uhci); 768 769 if (uhci->rh_state == UHCI_RH_RESET) { 770 771 /* The controller had to be reset */ 772 usb_root_hub_lost_power(hcd->self.root_hub); 773 suspend_rh(uhci, UHCI_RH_SUSPENDED); 774 } 775 776 spin_unlock_irq(&uhci->lock); 777 778 if (!uhci->working_RD) { 779 /* Suspended root hub needs to be polled */ 780 hcd->poll_rh = 1; 781 usb_hcd_poll_rh_status(hcd); 782 } 783 return 0; 784 } 785 #endif 786 787 /* Wait until a particular device/endpoint's QH is idle, and free it */ 788 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, 789 struct usb_host_endpoint *hep) 790 { 791 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 792 struct uhci_qh *qh; 793 794 spin_lock_irq(&uhci->lock); 795 qh = (struct uhci_qh *) hep->hcpriv; 796 if (qh == NULL) 797 goto done; 798 799 while (qh->state != QH_STATE_IDLE) { 800 ++uhci->num_waiting; 801 spin_unlock_irq(&uhci->lock); 802 wait_event_interruptible(uhci->waitqh, 803 qh->state == QH_STATE_IDLE); 804 spin_lock_irq(&uhci->lock); 805 --uhci->num_waiting; 806 } 807 808 uhci_free_qh(uhci, qh); 809 done: 810 spin_unlock_irq(&uhci->lock); 811 } 812 813 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) 814 { 815 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 816 unsigned frame_number; 817 unsigned delta; 818 819 /* Minimize latency by avoiding the spinlock */ 820 frame_number = uhci->frame_number; 821 barrier(); 822 delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & 823 (UHCI_NUMFRAMES - 1); 824 return frame_number + delta; 825 } 826 827 static const char hcd_name[] = "uhci_hcd"; 828 829 static const struct hc_driver uhci_driver = { 830 .description = hcd_name, 831 .product_desc = "UHCI Host Controller", 832 .hcd_priv_size = sizeof(struct uhci_hcd), 833 834 /* Generic hardware linkage */ 835 .irq = uhci_irq, 836 .flags = HCD_USB11, 837 838 /* Basic lifecycle operations */ 839 .reset = uhci_init, 840 .start = uhci_start, 841 #ifdef CONFIG_PM 842 .suspend = uhci_suspend, 843 .resume = uhci_resume, 844 .bus_suspend = uhci_rh_suspend, 845 .bus_resume = uhci_rh_resume, 846 #endif 847 .stop = uhci_stop, 848 849 .urb_enqueue = uhci_urb_enqueue, 850 .urb_dequeue = uhci_urb_dequeue, 851 852 .endpoint_disable = uhci_hcd_endpoint_disable, 853 .get_frame_number = uhci_hcd_get_frame_number, 854 855 .hub_status_data = uhci_hub_status_data, 856 .hub_control = uhci_hub_control, 857 }; 858 859 static const struct pci_device_id uhci_pci_ids[] = { { 860 /* handle any USB UHCI controller */ 861 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), 862 .driver_data = (unsigned long) &uhci_driver, 863 }, { /* end: all zeroes */ } 864 }; 865 866 MODULE_DEVICE_TABLE(pci, uhci_pci_ids); 867 868 static struct pci_driver uhci_pci_driver = { 869 .name = (char *)hcd_name, 870 .id_table = uhci_pci_ids, 871 872 .probe = usb_hcd_pci_probe, 873 .remove = usb_hcd_pci_remove, 874 .shutdown = uhci_shutdown, 875 876 #ifdef CONFIG_PM 877 .suspend = usb_hcd_pci_suspend, 878 .resume = usb_hcd_pci_resume, 879 #endif /* PM */ 880 }; 881 882 static int __init uhci_hcd_init(void) 883 { 884 int retval = -ENOMEM; 885 886 printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); 887 888 if (usb_disabled()) 889 return -ENODEV; 890 891 if (DEBUG_CONFIGURED) { 892 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); 893 if (!errbuf) 894 goto errbuf_failed; 895 uhci_debugfs_root = debugfs_create_dir("uhci", NULL); 896 if (!uhci_debugfs_root) 897 goto debug_failed; 898 } 899 900 uhci_up_cachep = kmem_cache_create("uhci_urb_priv", 901 sizeof(struct urb_priv), 0, 0, NULL, NULL); 902 if (!uhci_up_cachep) 903 goto up_failed; 904 905 retval = pci_register_driver(&uhci_pci_driver); 906 if (retval) 907 goto init_failed; 908 909 return 0; 910 911 init_failed: 912 if (kmem_cache_destroy(uhci_up_cachep)) 913 warn("not all urb_privs were freed!"); 914 915 up_failed: 916 debugfs_remove(uhci_debugfs_root); 917 918 debug_failed: 919 kfree(errbuf); 920 921 errbuf_failed: 922 923 return retval; 924 } 925 926 static void __exit uhci_hcd_cleanup(void) 927 { 928 pci_unregister_driver(&uhci_pci_driver); 929 930 if (kmem_cache_destroy(uhci_up_cachep)) 931 warn("not all urb_privs were freed!"); 932 933 debugfs_remove(uhci_debugfs_root); 934 kfree(errbuf); 935 } 936 937 module_init(uhci_hcd_init); 938 module_exit(uhci_hcd_cleanup); 939 940 MODULE_AUTHOR(DRIVER_AUTHOR); 941 MODULE_DESCRIPTION(DRIVER_DESC); 942 MODULE_LICENSE("GPL"); 943