1 /* 2 * This file contains code to reset and initialize USB host controllers. 3 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 4 * It may need to run early during booting -- before USB would normally 5 * initialize -- to ensure that Linux doesn't use any legacy modes. 6 * 7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 8 * (and others) 9 */ 10 11 #include <linux/config.h> 12 #ifdef CONFIG_USB_DEBUG 13 #define DEBUG 14 #else 15 #undef DEBUG 16 #endif 17 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/acpi.h> 24 25 26 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 27 #define UHCI_USBCMD 0 /* command register */ 28 #define UHCI_USBINTR 4 /* interrupt register */ 29 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 30 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 31 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 32 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 33 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 34 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 35 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 36 37 #define OHCI_CONTROL 0x04 38 #define OHCI_CMDSTATUS 0x08 39 #define OHCI_INTRSTATUS 0x0c 40 #define OHCI_INTRENABLE 0x10 41 #define OHCI_INTRDISABLE 0x14 42 #define OHCI_OCR (1 << 3) /* ownership change request */ 43 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 44 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 45 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 46 47 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 48 #define EHCI_USBCMD 0 /* command register */ 49 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 50 #define EHCI_USBSTS 4 /* status register */ 51 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 52 #define EHCI_USBINTR 8 /* interrupt register */ 53 #define EHCI_USBLEGSUP 0 /* legacy support register */ 54 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 55 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 56 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 57 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 58 59 60 /* 61 * Make sure the controller is completely inactive, unable to 62 * generate interrupts or do DMA. 63 */ 64 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 65 { 66 /* Turn off PIRQ enable and SMI enable. (This also turns off the 67 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 68 */ 69 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 70 71 /* Reset the HC - this will force us to get a 72 * new notification of any already connected 73 * ports due to the virtual disconnect that it 74 * implies. 75 */ 76 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 77 mb(); 78 udelay(5); 79 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 80 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 81 82 /* Just to be safe, disable interrupt requests and 83 * make sure the controller is stopped. 84 */ 85 outw(0, base + UHCI_USBINTR); 86 outw(0, base + UHCI_USBCMD); 87 } 88 EXPORT_SYMBOL_GPL(uhci_reset_hc); 89 90 /* 91 * Initialize a controller that was newly discovered or has just been 92 * resumed. In either case we can't be sure of its previous state. 93 * 94 * Returns: 1 if the controller was reset, 0 otherwise. 95 */ 96 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 97 { 98 u16 legsup; 99 unsigned int cmd, intr; 100 101 /* 102 * When restarting a suspended controller, we expect all the 103 * settings to be the same as we left them: 104 * 105 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 106 * Controller is stopped and configured with EGSM set; 107 * No interrupts enabled except possibly Resume Detect. 108 * 109 * If any of these conditions are violated we do a complete reset. 110 */ 111 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 112 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 113 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 114 __FUNCTION__, legsup); 115 goto reset_needed; 116 } 117 118 cmd = inw(base + UHCI_USBCMD); 119 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 120 !(cmd & UHCI_USBCMD_EGSM)) { 121 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 122 __FUNCTION__, cmd); 123 goto reset_needed; 124 } 125 126 intr = inw(base + UHCI_USBINTR); 127 if (intr & (~UHCI_USBINTR_RESUME)) { 128 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 129 __FUNCTION__, intr); 130 goto reset_needed; 131 } 132 return 0; 133 134 reset_needed: 135 dev_dbg(&pdev->dev, "Performing full reset\n"); 136 uhci_reset_hc(pdev, base); 137 return 1; 138 } 139 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 140 141 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 142 { 143 u16 cmd; 144 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 145 } 146 147 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 148 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 149 150 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 151 { 152 unsigned long base = 0; 153 int i; 154 155 if (!pio_enabled(pdev)) 156 return; 157 158 for (i = 0; i < PCI_ROM_RESOURCE; i++) 159 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 160 base = pci_resource_start(pdev, i); 161 break; 162 } 163 164 if (base) 165 uhci_check_and_reset_hc(pdev, base); 166 } 167 168 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) 169 { 170 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 171 } 172 173 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 174 { 175 void __iomem *base; 176 int wait_time; 177 u32 control; 178 179 if (!mmio_resource_enabled(pdev, 0)) 180 return; 181 182 base = ioremap_nocache(pci_resource_start(pdev, 0), 183 pci_resource_len(pdev, 0)); 184 if (base == NULL) return; 185 186 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 187 #ifndef __hppa__ 188 control = readl(base + OHCI_CONTROL); 189 if (control & OHCI_CTRL_IR) { 190 wait_time = 500; /* arbitrary; 5 seconds */ 191 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 192 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 193 while (wait_time > 0 && 194 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 195 wait_time -= 10; 196 msleep(10); 197 } 198 if (wait_time <= 0) 199 printk(KERN_WARNING "%s %s: early BIOS handoff " 200 "failed (BIOS bug ?)\n", 201 pdev->dev.bus_id, "OHCI"); 202 203 /* reset controller, preserving RWC */ 204 writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL); 205 } 206 #endif 207 208 /* 209 * disable interrupts 210 */ 211 writel(~(u32)0, base + OHCI_INTRDISABLE); 212 writel(~(u32)0, base + OHCI_INTRSTATUS); 213 214 iounmap(base); 215 } 216 217 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 218 { 219 int wait_time, delta; 220 void __iomem *base, *op_reg_base; 221 u32 hcc_params, val, temp; 222 u8 cap_length; 223 224 if (!mmio_resource_enabled(pdev, 0)) 225 return; 226 227 base = ioremap_nocache(pci_resource_start(pdev, 0), 228 pci_resource_len(pdev, 0)); 229 if (base == NULL) return; 230 231 cap_length = readb(base); 232 op_reg_base = base + cap_length; 233 hcc_params = readl(base + EHCI_HCC_PARAMS); 234 hcc_params = (hcc_params >> 8) & 0xff; 235 if (hcc_params) { 236 pci_read_config_dword(pdev, 237 hcc_params + EHCI_USBLEGSUP, 238 &val); 239 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) { 240 /* 241 * Ok, BIOS is in smm mode, try to hand off... 242 */ 243 pci_read_config_dword(pdev, 244 hcc_params + EHCI_USBLEGCTLSTS, 245 &temp); 246 pci_write_config_dword(pdev, 247 hcc_params + EHCI_USBLEGCTLSTS, 248 temp | EHCI_USBLEGCTLSTS_SOOE); 249 val |= EHCI_USBLEGSUP_OS; 250 pci_write_config_dword(pdev, 251 hcc_params + EHCI_USBLEGSUP, 252 val); 253 254 wait_time = 500; 255 do { 256 msleep(10); 257 wait_time -= 10; 258 pci_read_config_dword(pdev, 259 hcc_params + EHCI_USBLEGSUP, 260 &val); 261 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS)); 262 if (!wait_time) { 263 /* 264 * well, possibly buggy BIOS... 265 */ 266 printk(KERN_WARNING "%s %s: early BIOS handoff " 267 "failed (BIOS bug ?)\n", 268 pdev->dev.bus_id, "EHCI"); 269 pci_write_config_dword(pdev, 270 hcc_params + EHCI_USBLEGSUP, 271 EHCI_USBLEGSUP_OS); 272 pci_write_config_dword(pdev, 273 hcc_params + EHCI_USBLEGCTLSTS, 274 0); 275 } 276 } 277 } 278 279 /* 280 * halt EHCI & disable its interrupts in any case 281 */ 282 val = readl(op_reg_base + EHCI_USBSTS); 283 if ((val & EHCI_USBSTS_HALTED) == 0) { 284 val = readl(op_reg_base + EHCI_USBCMD); 285 val &= ~EHCI_USBCMD_RUN; 286 writel(val, op_reg_base + EHCI_USBCMD); 287 288 wait_time = 2000; 289 delta = 100; 290 do { 291 writel(0x3f, op_reg_base + EHCI_USBSTS); 292 udelay(delta); 293 wait_time -= delta; 294 val = readl(op_reg_base + EHCI_USBSTS); 295 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 296 break; 297 } 298 } while (wait_time > 0); 299 } 300 writel(0, op_reg_base + EHCI_USBINTR); 301 writel(0x3f, op_reg_base + EHCI_USBSTS); 302 303 iounmap(base); 304 305 return; 306 } 307 308 309 310 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 311 { 312 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 313 quirk_usb_handoff_uhci(pdev); 314 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 315 quirk_usb_handoff_ohci(pdev); 316 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 317 quirk_usb_disable_ehci(pdev); 318 } 319 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 320