1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * (C) Copyright 2002 Hewlett-Packard Company 7 * 8 * Bus Glue for pxa27x 9 * 10 * Written by Christopher Hoover <ch@hpl.hp.com> 11 * Based on fragments of previous driver by Russell King et al. 12 * 13 * Modified for LH7A404 from ohci-sa1111.c 14 * by Durgesh Pattamatta <pattamattad@sharpsec.com> 15 * 16 * Modified for pxa27x from ohci-lh7a404.c 17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004 18 * 19 * This file is licenced under the GPL. 20 */ 21 22 #include <linux/device.h> 23 #include <linux/signal.h> 24 #include <linux/platform_device.h> 25 #include <linux/clk.h> 26 #include <linux/of_platform.h> 27 #include <linux/of_gpio.h> 28 #include <mach/hardware.h> 29 #include <linux/platform_data/usb-ohci-pxa27x.h> 30 #include <linux/platform_data/usb-pxa3xx-ulpi.h> 31 32 /* 33 * UHC: USB Host Controller (OHCI-like) register definitions 34 */ 35 #define UHCREV (0x0000) /* UHC HCI Spec Revision */ 36 #define UHCHCON (0x0004) /* UHC Host Control Register */ 37 #define UHCCOMS (0x0008) /* UHC Command Status Register */ 38 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */ 39 #define UHCINTE (0x0010) /* UHC Interrupt Enable */ 40 #define UHCINTD (0x0014) /* UHC Interrupt Disable */ 41 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */ 42 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 43 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */ 44 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 45 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */ 46 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 47 #define UHCDHEAD (0x0030) /* UHC Done Head */ 48 #define UHCFMI (0x0034) /* UHC Frame Interval */ 49 #define UHCFMR (0x0038) /* UHC Frame Remaining */ 50 #define UHCFMN (0x003C) /* UHC Frame Number */ 51 #define UHCPERS (0x0040) /* UHC Periodic Start */ 52 #define UHCLS (0x0044) /* UHC Low Speed Threshold */ 53 54 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */ 55 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ 56 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */ 57 #define UHCRHDA_POTPGT(x) \ 58 (((x) & 0xff) << 24) /* Power On To Power Good Time */ 59 60 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */ 61 #define UHCRHS (0x0050) /* UHC Root Hub Status */ 62 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */ 63 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */ 64 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */ 65 66 #define UHCSTAT (0x0060) /* UHC Status Register */ 67 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ 68 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ 69 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ 70 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ 71 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ 72 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ 73 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ 74 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ 75 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ 76 77 #define UHCHR (0x0064) /* UHC Reset Register */ 78 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ 79 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ 80 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ 81 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ 82 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ 83 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ 84 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ 85 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ 86 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ 87 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ 88 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ 89 90 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/ 91 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ 92 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ 93 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ 94 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ 95 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort 96 Interrupt Enable*/ 97 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ 98 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ 99 100 #define UHCHIT (0x006C) /* UHC Interrupt Test register */ 101 102 #define PXA_UHC_MAX_PORTNUM 3 103 104 struct pxa27x_ohci { 105 /* must be 1st member here for hcd_to_ohci() to work */ 106 struct ohci_hcd ohci; 107 108 struct device *dev; 109 struct clk *clk; 110 void __iomem *mmio_base; 111 }; 112 113 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd) 114 115 /* 116 PMM_NPS_MODE -- PMM Non-power switching mode 117 Ports are powered continuously. 118 119 PMM_GLOBAL_MODE -- PMM global switching mode 120 All ports are powered at the same time. 121 122 PMM_PERPORT_MODE -- PMM per port switching mode 123 Ports are powered individually. 124 */ 125 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode) 126 { 127 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA); 128 uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB); 129 130 switch (mode) { 131 case PMM_NPS_MODE: 132 uhcrhda |= RH_A_NPS; 133 break; 134 case PMM_GLOBAL_MODE: 135 uhcrhda &= ~(RH_A_NPS & RH_A_PSM); 136 break; 137 case PMM_PERPORT_MODE: 138 uhcrhda &= ~(RH_A_NPS); 139 uhcrhda |= RH_A_PSM; 140 141 /* Set port power control mask bits, only 3 ports. */ 142 uhcrhdb |= (0x7<<17); 143 break; 144 default: 145 printk( KERN_ERR 146 "Invalid mode %d, set to non-power switch mode.\n", 147 mode ); 148 149 uhcrhda |= RH_A_NPS; 150 } 151 152 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA); 153 __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB); 154 return 0; 155 } 156 157 extern int usb_disabled(void); 158 159 /*-------------------------------------------------------------------------*/ 160 161 static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci, 162 struct pxaohci_platform_data *inf) 163 { 164 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR); 165 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA); 166 167 if (inf->flags & ENABLE_PORT1) 168 uhchr &= ~UHCHR_SSEP1; 169 170 if (inf->flags & ENABLE_PORT2) 171 uhchr &= ~UHCHR_SSEP2; 172 173 if (inf->flags & ENABLE_PORT3) 174 uhchr &= ~UHCHR_SSEP3; 175 176 if (inf->flags & POWER_CONTROL_LOW) 177 uhchr |= UHCHR_PCPL; 178 179 if (inf->flags & POWER_SENSE_LOW) 180 uhchr |= UHCHR_PSPL; 181 182 if (inf->flags & NO_OC_PROTECTION) 183 uhcrhda |= UHCRHDA_NOCP; 184 else 185 uhcrhda &= ~UHCRHDA_NOCP; 186 187 if (inf->flags & OC_MODE_PERPORT) 188 uhcrhda |= UHCRHDA_OCPM; 189 else 190 uhcrhda &= ~UHCRHDA_OCPM; 191 192 if (inf->power_on_delay) { 193 uhcrhda &= ~UHCRHDA_POTPGT(0xff); 194 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2); 195 } 196 197 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 198 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA); 199 } 200 201 static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci) 202 { 203 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR); 204 205 __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR); 206 udelay(11); 207 __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR); 208 } 209 210 #ifdef CONFIG_PXA27x 211 extern void pxa27x_clear_otgph(void); 212 #else 213 #define pxa27x_clear_otgph() do {} while (0) 214 #endif 215 216 static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev) 217 { 218 int retval = 0; 219 struct pxaohci_platform_data *inf; 220 uint32_t uhchr; 221 222 inf = dev_get_platdata(dev); 223 224 clk_prepare_enable(ohci->clk); 225 226 pxa27x_reset_hc(ohci); 227 228 uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR; 229 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 230 231 while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR) 232 cpu_relax(); 233 234 pxa27x_setup_hc(ohci, inf); 235 236 if (inf->init) 237 retval = inf->init(dev); 238 239 if (retval < 0) 240 return retval; 241 242 if (cpu_is_pxa3xx()) 243 pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self); 244 245 uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE; 246 __raw_writel(uhchr, ohci->mmio_base + UHCHR); 247 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE); 248 249 /* Clear any OTG Pin Hold */ 250 pxa27x_clear_otgph(); 251 return 0; 252 } 253 254 static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev) 255 { 256 struct pxaohci_platform_data *inf; 257 uint32_t uhccoms; 258 259 inf = dev_get_platdata(dev); 260 261 if (cpu_is_pxa3xx()) 262 pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self); 263 264 if (inf->exit) 265 inf->exit(dev); 266 267 pxa27x_reset_hc(ohci); 268 269 /* Host Controller Reset */ 270 uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01; 271 __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS); 272 udelay(10); 273 274 clk_disable_unprepare(ohci->clk); 275 } 276 277 #ifdef CONFIG_OF 278 static const struct of_device_id pxa_ohci_dt_ids[] = { 279 { .compatible = "marvell,pxa-ohci" }, 280 { } 281 }; 282 283 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids); 284 285 static int ohci_pxa_of_init(struct platform_device *pdev) 286 { 287 struct device_node *np = pdev->dev.of_node; 288 struct pxaohci_platform_data *pdata; 289 u32 tmp; 290 int ret; 291 292 if (!np) 293 return 0; 294 295 /* Right now device-tree probed devices don't get dma_mask set. 296 * Since shared usb code relies on it, set it here for now. 297 * Once we have dma capability bindings this can go away. 298 */ 299 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 300 if (ret) 301 return ret; 302 303 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 304 if (!pdata) 305 return -ENOMEM; 306 307 if (of_get_property(np, "marvell,enable-port1", NULL)) 308 pdata->flags |= ENABLE_PORT1; 309 if (of_get_property(np, "marvell,enable-port2", NULL)) 310 pdata->flags |= ENABLE_PORT2; 311 if (of_get_property(np, "marvell,enable-port3", NULL)) 312 pdata->flags |= ENABLE_PORT3; 313 if (of_get_property(np, "marvell,port-sense-low", NULL)) 314 pdata->flags |= POWER_SENSE_LOW; 315 if (of_get_property(np, "marvell,power-control-low", NULL)) 316 pdata->flags |= POWER_CONTROL_LOW; 317 if (of_get_property(np, "marvell,no-oc-protection", NULL)) 318 pdata->flags |= NO_OC_PROTECTION; 319 if (of_get_property(np, "marvell,oc-mode-perport", NULL)) 320 pdata->flags |= OC_MODE_PERPORT; 321 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp)) 322 pdata->power_on_delay = tmp; 323 if (!of_property_read_u32(np, "marvell,port-mode", &tmp)) 324 pdata->port_mode = tmp; 325 if (!of_property_read_u32(np, "marvell,power-budget", &tmp)) 326 pdata->power_budget = tmp; 327 328 pdev->dev.platform_data = pdata; 329 330 return 0; 331 } 332 #else 333 static int ohci_pxa_of_init(struct platform_device *pdev) 334 { 335 return 0; 336 } 337 #endif 338 339 /*-------------------------------------------------------------------------*/ 340 341 /* configure so an HC device and id are always provided */ 342 /* always called with process context; sleeping is OK */ 343 344 345 /** 346 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs 347 * Context: !in_interrupt() 348 * 349 * Allocates basic resources for this USB host controller, and 350 * then invokes the start() method for the HCD associated with it 351 * through the hotplug entry's driver_data. 352 * 353 */ 354 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev) 355 { 356 int retval, irq; 357 struct usb_hcd *hcd; 358 struct pxaohci_platform_data *inf; 359 struct pxa27x_ohci *ohci; 360 struct resource *r; 361 struct clk *usb_clk; 362 363 retval = ohci_pxa_of_init(pdev); 364 if (retval) 365 return retval; 366 367 inf = dev_get_platdata(&pdev->dev); 368 369 if (!inf) 370 return -ENODEV; 371 372 irq = platform_get_irq(pdev, 0); 373 if (irq < 0) { 374 pr_err("no resource of IORESOURCE_IRQ"); 375 return -ENXIO; 376 } 377 378 usb_clk = clk_get(&pdev->dev, NULL); 379 if (IS_ERR(usb_clk)) 380 return PTR_ERR(usb_clk); 381 382 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x"); 383 if (!hcd) { 384 retval = -ENOMEM; 385 goto err0; 386 } 387 388 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 389 if (!r) { 390 pr_err("no resource of IORESOURCE_MEM"); 391 retval = -ENXIO; 392 goto err1; 393 } 394 395 hcd->rsrc_start = r->start; 396 hcd->rsrc_len = resource_size(r); 397 398 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { 399 pr_debug("request_mem_region failed"); 400 retval = -EBUSY; 401 goto err1; 402 } 403 404 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 405 if (!hcd->regs) { 406 pr_debug("ioremap failed"); 407 retval = -ENOMEM; 408 goto err2; 409 } 410 411 /* initialize "struct pxa27x_ohci" */ 412 ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd); 413 ohci->dev = &pdev->dev; 414 ohci->clk = usb_clk; 415 ohci->mmio_base = (void __iomem *)hcd->regs; 416 417 if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) { 418 pr_debug("pxa27x_start_hc failed"); 419 goto err3; 420 } 421 422 /* Select Power Management Mode */ 423 pxa27x_ohci_select_pmm(ohci, inf->port_mode); 424 425 if (inf->power_budget) 426 hcd->power_budget = inf->power_budget; 427 428 ohci_hcd_init(hcd_to_ohci(hcd)); 429 430 retval = usb_add_hcd(hcd, irq, 0); 431 if (retval == 0) 432 return retval; 433 434 pxa27x_stop_hc(ohci, &pdev->dev); 435 err3: 436 iounmap(hcd->regs); 437 err2: 438 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 439 err1: 440 usb_put_hcd(hcd); 441 err0: 442 clk_put(usb_clk); 443 return retval; 444 } 445 446 447 /* may be called without controller electrically present */ 448 /* may be called with controller, bus, and devices active */ 449 450 /** 451 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs 452 * @dev: USB Host Controller being removed 453 * Context: !in_interrupt() 454 * 455 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking 456 * the HCD's stop() method. It is always called from a thread 457 * context, normally "rmmod", "apmd", or something similar. 458 * 459 */ 460 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev) 461 { 462 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 463 464 usb_remove_hcd(hcd); 465 pxa27x_stop_hc(ohci, &pdev->dev); 466 iounmap(hcd->regs); 467 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 468 usb_put_hcd(hcd); 469 clk_put(ohci->clk); 470 } 471 472 /*-------------------------------------------------------------------------*/ 473 474 static int 475 ohci_pxa27x_start (struct usb_hcd *hcd) 476 { 477 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 478 int ret; 479 480 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci); 481 482 /* The value of NDP in roothub_a is incorrect on this hardware */ 483 ohci->num_ports = 3; 484 485 if ((ret = ohci_init(ohci)) < 0) 486 return ret; 487 488 if ((ret = ohci_run (ohci)) < 0) { 489 dev_err(hcd->self.controller, "can't start %s", 490 hcd->self.bus_name); 491 ohci_stop (hcd); 492 return ret; 493 } 494 495 return 0; 496 } 497 498 /*-------------------------------------------------------------------------*/ 499 500 static const struct hc_driver ohci_pxa27x_hc_driver = { 501 .description = hcd_name, 502 .product_desc = "PXA27x OHCI", 503 .hcd_priv_size = sizeof(struct pxa27x_ohci), 504 505 /* 506 * generic hardware linkage 507 */ 508 .irq = ohci_irq, 509 .flags = HCD_USB11 | HCD_MEMORY, 510 511 /* 512 * basic lifecycle operations 513 */ 514 .start = ohci_pxa27x_start, 515 .stop = ohci_stop, 516 .shutdown = ohci_shutdown, 517 518 /* 519 * managing i/o requests and associated device resources 520 */ 521 .urb_enqueue = ohci_urb_enqueue, 522 .urb_dequeue = ohci_urb_dequeue, 523 .endpoint_disable = ohci_endpoint_disable, 524 525 /* 526 * scheduling support 527 */ 528 .get_frame_number = ohci_get_frame, 529 530 /* 531 * root hub support 532 */ 533 .hub_status_data = ohci_hub_status_data, 534 .hub_control = ohci_hub_control, 535 #ifdef CONFIG_PM 536 .bus_suspend = ohci_bus_suspend, 537 .bus_resume = ohci_bus_resume, 538 #endif 539 .start_port_reset = ohci_start_port_reset, 540 }; 541 542 /*-------------------------------------------------------------------------*/ 543 544 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev) 545 { 546 pr_debug ("In ohci_hcd_pxa27x_drv_probe"); 547 548 if (usb_disabled()) 549 return -ENODEV; 550 551 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev); 552 } 553 554 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev) 555 { 556 struct usb_hcd *hcd = platform_get_drvdata(pdev); 557 558 usb_hcd_pxa27x_remove(hcd, pdev); 559 return 0; 560 } 561 562 #ifdef CONFIG_PM 563 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev) 564 { 565 struct usb_hcd *hcd = dev_get_drvdata(dev); 566 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 567 568 if (time_before(jiffies, ohci->ohci.next_statechange)) 569 msleep(5); 570 ohci->ohci.next_statechange = jiffies; 571 572 pxa27x_stop_hc(ohci, dev); 573 return 0; 574 } 575 576 static int ohci_hcd_pxa27x_drv_resume(struct device *dev) 577 { 578 struct usb_hcd *hcd = dev_get_drvdata(dev); 579 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd); 580 struct pxaohci_platform_data *inf = dev_get_platdata(dev); 581 int status; 582 583 if (time_before(jiffies, ohci->ohci.next_statechange)) 584 msleep(5); 585 ohci->ohci.next_statechange = jiffies; 586 587 if ((status = pxa27x_start_hc(ohci, dev)) < 0) 588 return status; 589 590 /* Select Power Management Mode */ 591 pxa27x_ohci_select_pmm(ohci, inf->port_mode); 592 593 ohci_resume(hcd, false); 594 return 0; 595 } 596 597 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = { 598 .suspend = ohci_hcd_pxa27x_drv_suspend, 599 .resume = ohci_hcd_pxa27x_drv_resume, 600 }; 601 #endif 602 603 /* work with hotplug and coldplug */ 604 MODULE_ALIAS("platform:pxa27x-ohci"); 605 606 static struct platform_driver ohci_hcd_pxa27x_driver = { 607 .probe = ohci_hcd_pxa27x_drv_probe, 608 .remove = ohci_hcd_pxa27x_drv_remove, 609 .shutdown = usb_hcd_platform_shutdown, 610 .driver = { 611 .name = "pxa27x-ohci", 612 .owner = THIS_MODULE, 613 .of_match_table = of_match_ptr(pxa_ohci_dt_ids), 614 #ifdef CONFIG_PM 615 .pm = &ohci_hcd_pxa27x_pm_ops, 616 #endif 617 }, 618 }; 619 620