1 /* 2 * driver for NXP USB Host devices 3 * 4 * Currently supported OHCI host devices: 5 * - Philips PNX4008 6 * - NXP LPC32xx 7 * 8 * Authors: Dmitry Chigirev <source@mvista.com> 9 * Vitaly Wool <vitalywool@gmail.com> 10 * 11 * register initialization is based on code examples provided by Philips 12 * Copyright (c) 2005 Koninklijke Philips Electronics N.V. 13 * 14 * NOTE: This driver does not have suspend/resume functionality 15 * This driver is intended for engineering development purposes only 16 * 17 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under 18 * the terms of the GNU General Public License version 2. This program 19 * is licensed "as is" without any warranty of any kind, whether express 20 * or implied. 21 */ 22 #include <linux/clk.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/of.h> 26 #include <linux/usb/isp1301.h> 27 28 #include <mach/hardware.h> 29 #include <asm/mach-types.h> 30 #include <asm/io.h> 31 32 #include <mach/platform.h> 33 #include <mach/irqs.h> 34 35 #define USB_CONFIG_BASE 0x31020000 36 #define PWRMAN_BASE 0x40004000 37 38 #define USB_CTRL IO_ADDRESS(PWRMAN_BASE + 0x64) 39 40 /* USB_CTRL bit defines */ 41 #define USB_SLAVE_HCLK_EN (1 << 24) 42 #define USB_DEV_NEED_CLK_EN (1 << 22) 43 #define USB_HOST_NEED_CLK_EN (1 << 21) 44 #define PAD_CONTROL_LAST_DRIVEN (1 << 19) 45 46 #define USB_OTG_CLK_CTRL IO_ADDRESS(USB_CONFIG_BASE + 0xFF4) 47 #define USB_OTG_CLK_STAT IO_ADDRESS(USB_CONFIG_BASE + 0xFF8) 48 49 /* USB_OTG_CLK_CTRL bit defines */ 50 #define AHB_M_CLOCK_ON (1 << 4) 51 #define OTG_CLOCK_ON (1 << 3) 52 #define I2C_CLOCK_ON (1 << 2) 53 #define DEV_CLOCK_ON (1 << 1) 54 #define HOST_CLOCK_ON (1 << 0) 55 56 #define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110) 57 58 /* USB_OTG_STAT_CONTROL bit defines */ 59 #define TRANSPARENT_I2C_EN (1 << 7) 60 #define HOST_EN (1 << 0) 61 62 /* On LPC32xx, those are undefined */ 63 #ifndef start_int_set_falling_edge 64 #define start_int_set_falling_edge(irq) 65 #define start_int_set_rising_edge(irq) 66 #define start_int_ack(irq) 67 #define start_int_mask(irq) 68 #define start_int_umask(irq) 69 #endif 70 71 static struct i2c_client *isp1301_i2c_client; 72 73 extern int usb_disabled(void); 74 75 static struct clk *usb_clk; 76 77 static void isp1301_configure_pnx4008(void) 78 { 79 /* PNX4008 only supports DAT_SE0 USB mode */ 80 /* PNX4008 R2A requires setting the MAX603 to output 3.6V */ 81 /* Power up externel charge-pump */ 82 83 i2c_smbus_write_byte_data(isp1301_i2c_client, 84 ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG); 85 i2c_smbus_write_byte_data(isp1301_i2c_client, 86 ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 87 ~(MC1_DAT_SE0 | MC1_SPEED_REG)); 88 i2c_smbus_write_byte_data(isp1301_i2c_client, 89 ISP1301_I2C_MODE_CONTROL_2, 90 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); 91 i2c_smbus_write_byte_data(isp1301_i2c_client, 92 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, 93 ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL)); 94 i2c_smbus_write_byte_data(isp1301_i2c_client, 95 ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); 96 i2c_smbus_write_byte_data(isp1301_i2c_client, 97 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 98 ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 99 i2c_smbus_write_byte_data(isp1301_i2c_client, 100 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF); 101 i2c_smbus_write_byte_data(isp1301_i2c_client, 102 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, 103 0xFF); 104 i2c_smbus_write_byte_data(isp1301_i2c_client, 105 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, 106 0xFF); 107 } 108 109 static void isp1301_configure_lpc32xx(void) 110 { 111 /* LPC32XX only supports DAT_SE0 USB mode */ 112 /* This sequence is important */ 113 114 /* Disable transparent UART mode first */ 115 i2c_smbus_write_byte_data(isp1301_i2c_client, 116 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 117 MC1_UART_EN); 118 i2c_smbus_write_byte_data(isp1301_i2c_client, 119 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 120 ~MC1_SPEED_REG); 121 i2c_smbus_write_byte_data(isp1301_i2c_client, 122 ISP1301_I2C_MODE_CONTROL_1, MC1_SPEED_REG); 123 i2c_smbus_write_byte_data(isp1301_i2c_client, 124 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), 125 ~0); 126 i2c_smbus_write_byte_data(isp1301_i2c_client, 127 ISP1301_I2C_MODE_CONTROL_2, 128 (MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL)); 129 i2c_smbus_write_byte_data(isp1301_i2c_client, 130 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 131 i2c_smbus_write_byte_data(isp1301_i2c_client, 132 ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0); 133 i2c_smbus_write_byte_data(isp1301_i2c_client, 134 ISP1301_I2C_OTG_CONTROL_1, 135 (OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 136 i2c_smbus_write_byte_data(isp1301_i2c_client, 137 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 138 (OTG1_DM_PULLUP | OTG1_DP_PULLUP)); 139 i2c_smbus_write_byte_data(isp1301_i2c_client, 140 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 141 i2c_smbus_write_byte_data(isp1301_i2c_client, 142 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, 143 ~0); 144 i2c_smbus_write_byte_data(isp1301_i2c_client, 145 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 146 147 /* Enable usb_need_clk clock after transceiver is initialized */ 148 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); 149 150 printk(KERN_INFO "ISP1301 Vendor ID : 0x%04x\n", 151 i2c_smbus_read_word_data(isp1301_i2c_client, 0x00)); 152 printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n", 153 i2c_smbus_read_word_data(isp1301_i2c_client, 0x02)); 154 printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n", 155 i2c_smbus_read_word_data(isp1301_i2c_client, 0x14)); 156 } 157 158 static void isp1301_configure(void) 159 { 160 if (machine_is_pnx4008()) 161 isp1301_configure_pnx4008(); 162 else 163 isp1301_configure_lpc32xx(); 164 } 165 166 static inline void isp1301_vbus_on(void) 167 { 168 i2c_smbus_write_byte_data(isp1301_i2c_client, ISP1301_I2C_OTG_CONTROL_1, 169 OTG1_VBUS_DRV); 170 } 171 172 static inline void isp1301_vbus_off(void) 173 { 174 i2c_smbus_write_byte_data(isp1301_i2c_client, 175 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 176 OTG1_VBUS_DRV); 177 } 178 179 static void nxp_start_hc(void) 180 { 181 unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; 182 __raw_writel(tmp, USB_OTG_STAT_CONTROL); 183 isp1301_vbus_on(); 184 } 185 186 static void nxp_stop_hc(void) 187 { 188 unsigned long tmp; 189 isp1301_vbus_off(); 190 tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; 191 __raw_writel(tmp, USB_OTG_STAT_CONTROL); 192 } 193 194 static int __devinit ohci_nxp_start(struct usb_hcd *hcd) 195 { 196 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 197 int ret; 198 199 if ((ret = ohci_init(ohci)) < 0) 200 return ret; 201 202 if ((ret = ohci_run(ohci)) < 0) { 203 dev_err(hcd->self.controller, "can't start\n"); 204 ohci_stop(hcd); 205 return ret; 206 } 207 return 0; 208 } 209 210 static const struct hc_driver ohci_nxp_hc_driver = { 211 .description = hcd_name, 212 .product_desc = "nxp OHCI", 213 214 /* 215 * generic hardware linkage 216 */ 217 .irq = ohci_irq, 218 .flags = HCD_USB11 | HCD_MEMORY, 219 220 .hcd_priv_size = sizeof(struct ohci_hcd), 221 /* 222 * basic lifecycle operations 223 */ 224 .start = ohci_nxp_start, 225 .stop = ohci_stop, 226 .shutdown = ohci_shutdown, 227 228 /* 229 * managing i/o requests and associated device resources 230 */ 231 .urb_enqueue = ohci_urb_enqueue, 232 .urb_dequeue = ohci_urb_dequeue, 233 .endpoint_disable = ohci_endpoint_disable, 234 235 /* 236 * scheduling support 237 */ 238 .get_frame_number = ohci_get_frame, 239 240 /* 241 * root hub support 242 */ 243 .hub_status_data = ohci_hub_status_data, 244 .hub_control = ohci_hub_control, 245 #ifdef CONFIG_PM 246 .bus_suspend = ohci_bus_suspend, 247 .bus_resume = ohci_bus_resume, 248 #endif 249 .start_port_reset = ohci_start_port_reset, 250 }; 251 252 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON) 253 254 static void nxp_set_usb_bits(void) 255 { 256 if (machine_is_pnx4008()) { 257 start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N); 258 start_int_ack(SE_USB_OTG_ATX_INT_N); 259 start_int_umask(SE_USB_OTG_ATX_INT_N); 260 261 start_int_set_rising_edge(SE_USB_OTG_TIMER_INT); 262 start_int_ack(SE_USB_OTG_TIMER_INT); 263 start_int_umask(SE_USB_OTG_TIMER_INT); 264 265 start_int_set_rising_edge(SE_USB_I2C_INT); 266 start_int_ack(SE_USB_I2C_INT); 267 start_int_umask(SE_USB_I2C_INT); 268 269 start_int_set_rising_edge(SE_USB_INT); 270 start_int_ack(SE_USB_INT); 271 start_int_umask(SE_USB_INT); 272 273 start_int_set_rising_edge(SE_USB_NEED_CLK_INT); 274 start_int_ack(SE_USB_NEED_CLK_INT); 275 start_int_umask(SE_USB_NEED_CLK_INT); 276 277 start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT); 278 start_int_ack(SE_USB_AHB_NEED_CLK_INT); 279 start_int_umask(SE_USB_AHB_NEED_CLK_INT); 280 } 281 } 282 283 static void nxp_unset_usb_bits(void) 284 { 285 if (machine_is_pnx4008()) { 286 start_int_mask(SE_USB_OTG_ATX_INT_N); 287 start_int_mask(SE_USB_OTG_TIMER_INT); 288 start_int_mask(SE_USB_I2C_INT); 289 start_int_mask(SE_USB_INT); 290 start_int_mask(SE_USB_NEED_CLK_INT); 291 start_int_mask(SE_USB_AHB_NEED_CLK_INT); 292 } 293 } 294 295 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) 296 { 297 struct usb_hcd *hcd = 0; 298 struct ohci_hcd *ohci; 299 const struct hc_driver *driver = &ohci_nxp_hc_driver; 300 struct resource *res; 301 int ret = 0, irq; 302 struct device_node *isp1301_node; 303 304 if (pdev->dev.of_node) { 305 isp1301_node = of_parse_phandle(pdev->dev.of_node, 306 "transceiver", 0); 307 } else { 308 isp1301_node = NULL; 309 } 310 311 isp1301_i2c_client = isp1301_get_client(isp1301_node); 312 if (!isp1301_i2c_client) { 313 ret = -EPROBE_DEFER; 314 goto out; 315 } 316 317 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 318 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 319 320 dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name); 321 if (usb_disabled()) { 322 dev_err(&pdev->dev, "USB is disabled\n"); 323 ret = -ENODEV; 324 goto out; 325 } 326 327 /* Enable AHB slave USB clock, needed for further USB clock control */ 328 __raw_writel(USB_SLAVE_HCLK_EN | PAD_CONTROL_LAST_DRIVEN, USB_CTRL); 329 330 isp1301_configure(); 331 332 /* Enable USB PLL */ 333 usb_clk = clk_get(&pdev->dev, "ck_pll5"); 334 if (IS_ERR(usb_clk)) { 335 dev_err(&pdev->dev, "failed to acquire USB PLL\n"); 336 ret = PTR_ERR(usb_clk); 337 goto out1; 338 } 339 340 ret = clk_enable(usb_clk); 341 if (ret < 0) { 342 dev_err(&pdev->dev, "failed to start USB PLL\n"); 343 goto out2; 344 } 345 346 ret = clk_set_rate(usb_clk, 48000); 347 if (ret < 0) { 348 dev_err(&pdev->dev, "failed to set USB clock rate\n"); 349 goto out3; 350 } 351 352 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); 353 354 /* Set to enable all needed USB clocks */ 355 __raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL); 356 357 while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) != 358 USB_CLOCK_MASK) ; 359 360 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); 361 if (!hcd) { 362 dev_err(&pdev->dev, "Failed to allocate HC buffer\n"); 363 ret = -ENOMEM; 364 goto out3; 365 } 366 367 /* Set all USB bits in the Start Enable register */ 368 nxp_set_usb_bits(); 369 370 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 371 if (!res) { 372 dev_err(&pdev->dev, "Failed to get MEM resource\n"); 373 ret = -ENOMEM; 374 goto out4; 375 } 376 377 hcd->regs = devm_request_and_ioremap(&pdev->dev, res); 378 if (!hcd->regs) { 379 dev_err(&pdev->dev, "Failed to devm_request_and_ioremap\n"); 380 ret = -ENOMEM; 381 goto out4; 382 } 383 hcd->rsrc_start = res->start; 384 hcd->rsrc_len = resource_size(res); 385 386 irq = platform_get_irq(pdev, 0); 387 if (irq < 0) { 388 ret = -ENXIO; 389 goto out4; 390 } 391 392 nxp_start_hc(); 393 platform_set_drvdata(pdev, hcd); 394 ohci = hcd_to_ohci(hcd); 395 ohci_hcd_init(ohci); 396 397 dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq); 398 ret = usb_add_hcd(hcd, irq, 0); 399 if (ret == 0) 400 return ret; 401 402 nxp_stop_hc(); 403 out4: 404 nxp_unset_usb_bits(); 405 usb_put_hcd(hcd); 406 out3: 407 clk_disable(usb_clk); 408 out2: 409 clk_put(usb_clk); 410 out1: 411 isp1301_i2c_client = NULL; 412 out: 413 return ret; 414 } 415 416 static int usb_hcd_nxp_remove(struct platform_device *pdev) 417 { 418 struct usb_hcd *hcd = platform_get_drvdata(pdev); 419 420 usb_remove_hcd(hcd); 421 nxp_stop_hc(); 422 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 423 usb_put_hcd(hcd); 424 nxp_unset_usb_bits(); 425 clk_disable(usb_clk); 426 clk_put(usb_clk); 427 i2c_unregister_device(isp1301_i2c_client); 428 isp1301_i2c_client = NULL; 429 430 platform_set_drvdata(pdev, NULL); 431 432 return 0; 433 } 434 435 /* work with hotplug and coldplug */ 436 MODULE_ALIAS("platform:usb-ohci"); 437 438 #ifdef CONFIG_OF 439 static const struct of_device_id usb_hcd_nxp_match[] = { 440 { .compatible = "nxp,ohci-nxp" }, 441 {}, 442 }; 443 MODULE_DEVICE_TABLE(of, usb_hcd_nxp_match); 444 #endif 445 446 static struct platform_driver usb_hcd_nxp_driver = { 447 .driver = { 448 .name = "usb-ohci", 449 .owner = THIS_MODULE, 450 .of_match_table = of_match_ptr(usb_hcd_nxp_match), 451 }, 452 .probe = usb_hcd_nxp_probe, 453 .remove = usb_hcd_nxp_remove, 454 }; 455 456