1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * 13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 14 * interfaces (though some non-x86 Intel chips use it). It supports 15 * smarter hardware than UHCI. A download link for the spec available 16 * through the http://www.usb.org website. 17 * 18 * This file is licenced under the GPL. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 #include <linux/delay.h> 26 #include <linux/ioport.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/timer.h> 32 #include <linux/list.h> 33 #include <linux/usb.h> 34 #include <linux/usb/otg.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/dmapool.h> 37 #include <linux/workqueue.h> 38 #include <linux/debugfs.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <asm/system.h> 43 #include <asm/unaligned.h> 44 #include <asm/byteorder.h> 45 46 #include "../core/hcd.h" 47 48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 50 51 /*-------------------------------------------------------------------------*/ 52 53 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 54 55 /* For initializing controller (mask in an HCFS mode too) */ 56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 57 #define OHCI_INTR_INIT \ 58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 59 | OHCI_INTR_RD | OHCI_INTR_WDH) 60 61 #ifdef __hppa__ 62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 63 #define IR_DISABLE 64 #endif 65 66 #ifdef CONFIG_ARCH_OMAP 67 /* OMAP doesn't support IR (no SMM; not needed) */ 68 #define IR_DISABLE 69 #endif 70 71 /*-------------------------------------------------------------------------*/ 72 73 static const char hcd_name [] = "ohci_hcd"; 74 75 #define STATECHANGE_DELAY msecs_to_jiffies(300) 76 77 #include "ohci.h" 78 79 static void ohci_dump (struct ohci_hcd *ohci, int verbose); 80 static int ohci_init (struct ohci_hcd *ohci); 81 static void ohci_stop (struct usb_hcd *hcd); 82 83 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 84 static int ohci_restart (struct ohci_hcd *ohci); 85 #endif 86 87 #ifdef CONFIG_PCI 88 static void quirk_amd_pll(int state); 89 static void amd_iso_dev_put(void); 90 #else 91 static inline void quirk_amd_pll(int state) 92 { 93 return; 94 } 95 static inline void amd_iso_dev_put(void) 96 { 97 return; 98 } 99 #endif 100 101 102 #include "ohci-hub.c" 103 #include "ohci-dbg.c" 104 #include "ohci-mem.c" 105 #include "ohci-q.c" 106 107 108 /* 109 * On architectures with edge-triggered interrupts we must never return 110 * IRQ_NONE. 111 */ 112 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 113 #define IRQ_NOTMINE IRQ_HANDLED 114 #else 115 #define IRQ_NOTMINE IRQ_NONE 116 #endif 117 118 119 /* Some boards misreport power switching/overcurrent */ 120 static int distrust_firmware = 1; 121 module_param (distrust_firmware, bool, 0); 122 MODULE_PARM_DESC (distrust_firmware, 123 "true to distrust firmware power/overcurrent setup"); 124 125 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 126 static int no_handshake = 0; 127 module_param (no_handshake, bool, 0); 128 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 129 130 /*-------------------------------------------------------------------------*/ 131 132 /* 133 * queue up an urb for anything except the root hub 134 */ 135 static int ohci_urb_enqueue ( 136 struct usb_hcd *hcd, 137 struct urb *urb, 138 gfp_t mem_flags 139 ) { 140 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 141 struct ed *ed; 142 urb_priv_t *urb_priv; 143 unsigned int pipe = urb->pipe; 144 int i, size = 0; 145 unsigned long flags; 146 int retval = 0; 147 148 #ifdef OHCI_VERBOSE_DEBUG 149 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 150 #endif 151 152 /* every endpoint has a ed, locate and maybe (re)initialize it */ 153 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 154 return -ENOMEM; 155 156 /* for the private part of the URB we need the number of TDs (size) */ 157 switch (ed->type) { 158 case PIPE_CONTROL: 159 /* td_submit_urb() doesn't yet handle these */ 160 if (urb->transfer_buffer_length > 4096) 161 return -EMSGSIZE; 162 163 /* 1 TD for setup, 1 for ACK, plus ... */ 164 size = 2; 165 /* FALLTHROUGH */ 166 // case PIPE_INTERRUPT: 167 // case PIPE_BULK: 168 default: 169 /* one TD for every 4096 Bytes (can be upto 8K) */ 170 size += urb->transfer_buffer_length / 4096; 171 /* ... and for any remaining bytes ... */ 172 if ((urb->transfer_buffer_length % 4096) != 0) 173 size++; 174 /* ... and maybe a zero length packet to wrap it up */ 175 if (size == 0) 176 size++; 177 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 178 && (urb->transfer_buffer_length 179 % usb_maxpacket (urb->dev, pipe, 180 usb_pipeout (pipe))) == 0) 181 size++; 182 break; 183 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 184 size = urb->number_of_packets; 185 break; 186 } 187 188 /* allocate the private part of the URB */ 189 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 190 mem_flags); 191 if (!urb_priv) 192 return -ENOMEM; 193 INIT_LIST_HEAD (&urb_priv->pending); 194 urb_priv->length = size; 195 urb_priv->ed = ed; 196 197 /* allocate the TDs (deferring hash chain updates) */ 198 for (i = 0; i < size; i++) { 199 urb_priv->td [i] = td_alloc (ohci, mem_flags); 200 if (!urb_priv->td [i]) { 201 urb_priv->length = i; 202 urb_free_priv (ohci, urb_priv); 203 return -ENOMEM; 204 } 205 } 206 207 spin_lock_irqsave (&ohci->lock, flags); 208 209 /* don't submit to a dead HC */ 210 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 211 retval = -ENODEV; 212 goto fail; 213 } 214 if (!HC_IS_RUNNING(hcd->state)) { 215 retval = -ENODEV; 216 goto fail; 217 } 218 retval = usb_hcd_link_urb_to_ep(hcd, urb); 219 if (retval) 220 goto fail; 221 222 /* schedule the ed if needed */ 223 if (ed->state == ED_IDLE) { 224 retval = ed_schedule (ohci, ed); 225 if (retval < 0) { 226 usb_hcd_unlink_urb_from_ep(hcd, urb); 227 goto fail; 228 } 229 if (ed->type == PIPE_ISOCHRONOUS) { 230 u16 frame = ohci_frame_no(ohci); 231 232 /* delay a few frames before the first TD */ 233 frame += max_t (u16, 8, ed->interval); 234 frame &= ~(ed->interval - 1); 235 frame |= ed->branch; 236 urb->start_frame = frame; 237 238 /* yes, only URB_ISO_ASAP is supported, and 239 * urb->start_frame is never used as input. 240 */ 241 } 242 } else if (ed->type == PIPE_ISOCHRONOUS) 243 urb->start_frame = ed->last_iso + ed->interval; 244 245 /* fill the TDs and link them to the ed; and 246 * enable that part of the schedule, if needed 247 * and update count of queued periodic urbs 248 */ 249 urb->hcpriv = urb_priv; 250 td_submit_urb (ohci, urb); 251 252 fail: 253 if (retval) 254 urb_free_priv (ohci, urb_priv); 255 spin_unlock_irqrestore (&ohci->lock, flags); 256 return retval; 257 } 258 259 /* 260 * decouple the URB from the HC queues (TDs, urb_priv). 261 * reporting is always done 262 * asynchronously, and we might be dealing with an urb that's 263 * partially transferred, or an ED with other urbs being unlinked. 264 */ 265 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 266 { 267 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 268 unsigned long flags; 269 int rc; 270 271 #ifdef OHCI_VERBOSE_DEBUG 272 urb_print(urb, "UNLINK", 1, status); 273 #endif 274 275 spin_lock_irqsave (&ohci->lock, flags); 276 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 277 if (rc) { 278 ; /* Do nothing */ 279 } else if (HC_IS_RUNNING(hcd->state)) { 280 urb_priv_t *urb_priv; 281 282 /* Unless an IRQ completed the unlink while it was being 283 * handed to us, flag it for unlink and giveback, and force 284 * some upcoming INTR_SF to call finish_unlinks() 285 */ 286 urb_priv = urb->hcpriv; 287 if (urb_priv) { 288 if (urb_priv->ed->state == ED_OPER) 289 start_ed_unlink (ohci, urb_priv->ed); 290 } 291 } else { 292 /* 293 * with HC dead, we won't respect hc queue pointers 294 * any more ... just clean up every urb's memory. 295 */ 296 if (urb->hcpriv) 297 finish_urb(ohci, urb, status); 298 } 299 spin_unlock_irqrestore (&ohci->lock, flags); 300 return rc; 301 } 302 303 /*-------------------------------------------------------------------------*/ 304 305 /* frees config/altsetting state for endpoints, 306 * including ED memory, dummy TD, and bulk/intr data toggle 307 */ 308 309 static void 310 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 311 { 312 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 313 unsigned long flags; 314 struct ed *ed = ep->hcpriv; 315 unsigned limit = 1000; 316 317 /* ASSERT: any requests/urbs are being unlinked */ 318 /* ASSERT: nobody can be submitting urbs for this any more */ 319 320 if (!ed) 321 return; 322 323 rescan: 324 spin_lock_irqsave (&ohci->lock, flags); 325 326 if (!HC_IS_RUNNING (hcd->state)) { 327 sanitize: 328 ed->state = ED_IDLE; 329 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 330 ohci->eds_scheduled--; 331 finish_unlinks (ohci, 0); 332 } 333 334 switch (ed->state) { 335 case ED_UNLINK: /* wait for hw to finish? */ 336 /* major IRQ delivery trouble loses INTR_SF too... */ 337 if (limit-- == 0) { 338 ohci_warn(ohci, "ED unlink timeout\n"); 339 if (quirk_zfmicro(ohci)) { 340 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 341 ohci->ed_to_check = ed; 342 ohci->zf_delay = 2; 343 } 344 goto sanitize; 345 } 346 spin_unlock_irqrestore (&ohci->lock, flags); 347 schedule_timeout_uninterruptible(1); 348 goto rescan; 349 case ED_IDLE: /* fully unlinked */ 350 if (list_empty (&ed->td_list)) { 351 td_free (ohci, ed->dummy); 352 ed_free (ohci, ed); 353 break; 354 } 355 /* else FALL THROUGH */ 356 default: 357 /* caller was supposed to have unlinked any requests; 358 * that's not our job. can't recover; must leak ed. 359 */ 360 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 361 ed, ep->desc.bEndpointAddress, ed->state, 362 list_empty (&ed->td_list) ? "" : " (has tds)"); 363 td_free (ohci, ed->dummy); 364 break; 365 } 366 ep->hcpriv = NULL; 367 spin_unlock_irqrestore (&ohci->lock, flags); 368 return; 369 } 370 371 static int ohci_get_frame (struct usb_hcd *hcd) 372 { 373 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 374 375 return ohci_frame_no(ohci); 376 } 377 378 static void ohci_usb_reset (struct ohci_hcd *ohci) 379 { 380 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 381 ohci->hc_control &= OHCI_CTRL_RWC; 382 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 383 } 384 385 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 386 * other cases where the next software may expect clean state from the 387 * "firmware". this is bus-neutral, unlike shutdown() methods. 388 */ 389 static void 390 ohci_shutdown (struct usb_hcd *hcd) 391 { 392 struct ohci_hcd *ohci; 393 394 ohci = hcd_to_ohci (hcd); 395 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 396 ohci_usb_reset (ohci); 397 /* flush the writes */ 398 (void) ohci_readl (ohci, &ohci->regs->control); 399 } 400 401 static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 402 { 403 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 404 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 405 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 406 && !list_empty(&ed->td_list); 407 } 408 409 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 410 * an interrupt TD but neglects to add it to the donelist. On systems with 411 * this chipset, we need to periodically check the state of the queues to look 412 * for such "lost" TDs. 413 */ 414 static void unlink_watchdog_func(unsigned long _ohci) 415 { 416 unsigned long flags; 417 unsigned max; 418 unsigned seen_count = 0; 419 unsigned i; 420 struct ed **seen = NULL; 421 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 422 423 spin_lock_irqsave(&ohci->lock, flags); 424 max = ohci->eds_scheduled; 425 if (!max) 426 goto done; 427 428 if (ohci->ed_to_check) 429 goto out; 430 431 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 432 if (!seen) 433 goto out; 434 435 for (i = 0; i < NUM_INTS; i++) { 436 struct ed *ed = ohci->periodic[i]; 437 438 while (ed) { 439 unsigned temp; 440 441 /* scan this branch of the periodic schedule tree */ 442 for (temp = 0; temp < seen_count; temp++) { 443 if (seen[temp] == ed) { 444 /* we've checked it and what's after */ 445 ed = NULL; 446 break; 447 } 448 } 449 if (!ed) 450 break; 451 seen[seen_count++] = ed; 452 if (!check_ed(ohci, ed)) { 453 ed = ed->ed_next; 454 continue; 455 } 456 457 /* HC's TD list is empty, but HCD sees at least one 458 * TD that's not been sent through the donelist. 459 */ 460 ohci->ed_to_check = ed; 461 ohci->zf_delay = 2; 462 463 /* The HC may wait until the next frame to report the 464 * TD as done through the donelist and INTR_WDH. (We 465 * just *assume* it's not a multi-TD interrupt URB; 466 * those could defer the IRQ more than one frame, using 467 * DI...) Check again after the next INTR_SF. 468 */ 469 ohci_writel(ohci, OHCI_INTR_SF, 470 &ohci->regs->intrstatus); 471 ohci_writel(ohci, OHCI_INTR_SF, 472 &ohci->regs->intrenable); 473 474 /* flush those writes */ 475 (void) ohci_readl(ohci, &ohci->regs->control); 476 477 goto out; 478 } 479 } 480 out: 481 kfree(seen); 482 if (ohci->eds_scheduled) 483 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 484 done: 485 spin_unlock_irqrestore(&ohci->lock, flags); 486 } 487 488 /*-------------------------------------------------------------------------* 489 * HC functions 490 *-------------------------------------------------------------------------*/ 491 492 /* init memory, and kick BIOS/SMM off */ 493 494 static int ohci_init (struct ohci_hcd *ohci) 495 { 496 int ret; 497 struct usb_hcd *hcd = ohci_to_hcd(ohci); 498 499 if (distrust_firmware) 500 ohci->flags |= OHCI_QUIRK_HUB_POWER; 501 502 disable (ohci); 503 ohci->regs = hcd->regs; 504 505 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 506 * was never needed for most non-PCI systems ... remove the code? 507 */ 508 509 #ifndef IR_DISABLE 510 /* SMM owns the HC? not for long! */ 511 if (!no_handshake && ohci_readl (ohci, 512 &ohci->regs->control) & OHCI_CTRL_IR) { 513 u32 temp; 514 515 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 516 517 /* this timeout is arbitrary. we make it long, so systems 518 * depending on usb keyboards may be usable even if the 519 * BIOS/SMM code seems pretty broken. 520 */ 521 temp = 500; /* arbitrary: five seconds */ 522 523 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 524 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 525 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 526 msleep (10); 527 if (--temp == 0) { 528 ohci_err (ohci, "USB HC takeover failed!" 529 " (BIOS/SMM bug)\n"); 530 return -EBUSY; 531 } 532 } 533 ohci_usb_reset (ohci); 534 } 535 #endif 536 537 /* Disable HC interrupts */ 538 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 539 540 /* flush the writes, and save key bits like RWC */ 541 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 542 ohci->hc_control |= OHCI_CTRL_RWC; 543 544 /* Read the number of ports unless overridden */ 545 if (ohci->num_ports == 0) 546 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 547 548 if (ohci->hcca) 549 return 0; 550 551 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 552 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 553 if (!ohci->hcca) 554 return -ENOMEM; 555 556 if ((ret = ohci_mem_init (ohci)) < 0) 557 ohci_stop (hcd); 558 else { 559 create_debug_files (ohci); 560 } 561 562 return ret; 563 } 564 565 /*-------------------------------------------------------------------------*/ 566 567 /* Start an OHCI controller, set the BUS operational 568 * resets USB and controller 569 * enable interrupts 570 */ 571 static int ohci_run (struct ohci_hcd *ohci) 572 { 573 u32 mask, val; 574 int first = ohci->fminterval == 0; 575 struct usb_hcd *hcd = ohci_to_hcd(ohci); 576 577 disable (ohci); 578 579 /* boot firmware should have set this up (5.1.1.3.1) */ 580 if (first) { 581 582 val = ohci_readl (ohci, &ohci->regs->fminterval); 583 ohci->fminterval = val & 0x3fff; 584 if (ohci->fminterval != FI) 585 ohci_dbg (ohci, "fminterval delta %d\n", 586 ohci->fminterval - FI); 587 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 588 /* also: power/overcurrent flags in roothub.a */ 589 } 590 591 /* Reset USB nearly "by the book". RemoteWakeupConnected has 592 * to be checked in case boot firmware (BIOS/SMM/...) has set up 593 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 594 * If the bus glue detected wakeup capability then it should 595 * already be enabled; if so we'll just enable it again. 596 */ 597 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) 598 device_set_wakeup_capable(hcd->self.controller, 1); 599 600 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 601 case OHCI_USB_OPER: 602 val = 0; 603 break; 604 case OHCI_USB_SUSPEND: 605 case OHCI_USB_RESUME: 606 ohci->hc_control &= OHCI_CTRL_RWC; 607 ohci->hc_control |= OHCI_USB_RESUME; 608 val = 10 /* msec wait */; 609 break; 610 // case OHCI_USB_RESET: 611 default: 612 ohci->hc_control &= OHCI_CTRL_RWC; 613 ohci->hc_control |= OHCI_USB_RESET; 614 val = 50 /* msec wait */; 615 break; 616 } 617 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 618 // flush the writes 619 (void) ohci_readl (ohci, &ohci->regs->control); 620 msleep(val); 621 622 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 623 624 /* 2msec timelimit here means no irqs/preempt */ 625 spin_lock_irq (&ohci->lock); 626 627 retry: 628 /* HC Reset requires max 10 us delay */ 629 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 630 val = 30; /* ... allow extra time */ 631 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 632 if (--val == 0) { 633 spin_unlock_irq (&ohci->lock); 634 ohci_err (ohci, "USB HC reset timed out!\n"); 635 return -1; 636 } 637 udelay (1); 638 } 639 640 /* now we're in the SUSPEND state ... must go OPERATIONAL 641 * within 2msec else HC enters RESUME 642 * 643 * ... but some hardware won't init fmInterval "by the book" 644 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 645 * this if we write fmInterval after we're OPERATIONAL. 646 * Unclear about ALi, ServerWorks, and others ... this could 647 * easily be a longstanding bug in chip init on Linux. 648 */ 649 if (ohci->flags & OHCI_QUIRK_INITRESET) { 650 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 651 // flush those writes 652 (void) ohci_readl (ohci, &ohci->regs->control); 653 } 654 655 /* Tell the controller where the control and bulk lists are 656 * The lists are empty now. */ 657 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 658 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 659 660 /* a reset clears this */ 661 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 662 663 periodic_reinit (ohci); 664 665 /* some OHCI implementations are finicky about how they init. 666 * bogus values here mean not even enumeration could work. 667 */ 668 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 669 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 670 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 671 ohci->flags |= OHCI_QUIRK_INITRESET; 672 ohci_dbg (ohci, "enabling initreset quirk\n"); 673 goto retry; 674 } 675 spin_unlock_irq (&ohci->lock); 676 ohci_err (ohci, "init err (%08x %04x)\n", 677 ohci_readl (ohci, &ohci->regs->fminterval), 678 ohci_readl (ohci, &ohci->regs->periodicstart)); 679 return -EOVERFLOW; 680 } 681 682 /* use rhsc irqs after khubd is fully initialized */ 683 hcd->poll_rh = 1; 684 hcd->uses_new_polling = 1; 685 686 /* start controller operations */ 687 ohci->hc_control &= OHCI_CTRL_RWC; 688 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 689 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 690 hcd->state = HC_STATE_RUNNING; 691 692 /* wake on ConnectStatusChange, matching external hubs */ 693 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 694 695 /* Choose the interrupts we care about now, others later on demand */ 696 mask = OHCI_INTR_INIT; 697 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 698 ohci_writel (ohci, mask, &ohci->regs->intrenable); 699 700 /* handle root hub init quirks ... */ 701 val = roothub_a (ohci); 702 val &= ~(RH_A_PSM | RH_A_OCPM); 703 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 704 /* NSC 87560 and maybe others */ 705 val |= RH_A_NOCP; 706 val &= ~(RH_A_POTPGT | RH_A_NPS); 707 ohci_writel (ohci, val, &ohci->regs->roothub.a); 708 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 709 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 710 /* hub power always on; required for AMD-756 and some 711 * Mac platforms. ganged overcurrent reporting, if any. 712 */ 713 val |= RH_A_NPS; 714 ohci_writel (ohci, val, &ohci->regs->roothub.a); 715 } 716 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 717 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, 718 &ohci->regs->roothub.b); 719 // flush those writes 720 (void) ohci_readl (ohci, &ohci->regs->control); 721 722 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 723 spin_unlock_irq (&ohci->lock); 724 725 // POTPGT delay is bits 24-31, in 2 ms units. 726 mdelay ((val >> 23) & 0x1fe); 727 hcd->state = HC_STATE_RUNNING; 728 729 if (quirk_zfmicro(ohci)) { 730 /* Create timer to watch for bad queue state on ZF Micro */ 731 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 732 (unsigned long) ohci); 733 734 ohci->eds_scheduled = 0; 735 ohci->ed_to_check = NULL; 736 } 737 738 ohci_dump (ohci, 1); 739 740 return 0; 741 } 742 743 /*-------------------------------------------------------------------------*/ 744 745 /* an interrupt happens */ 746 747 static irqreturn_t ohci_irq (struct usb_hcd *hcd) 748 { 749 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 750 struct ohci_regs __iomem *regs = ohci->regs; 751 int ints; 752 753 /* Read interrupt status (and flush pending writes). We ignore the 754 * optimization of checking the LSB of hcca->done_head; it doesn't 755 * work on all systems (edge triggering for OHCI can be a factor). 756 */ 757 ints = ohci_readl(ohci, ®s->intrstatus); 758 759 /* Check for an all 1's result which is a typical consequence 760 * of dead, unclocked, or unplugged (CardBus...) devices 761 */ 762 if (ints == ~(u32)0) { 763 disable (ohci); 764 ohci_dbg (ohci, "device removed!\n"); 765 return IRQ_HANDLED; 766 } 767 768 /* We only care about interrupts that are enabled */ 769 ints &= ohci_readl(ohci, ®s->intrenable); 770 771 /* interrupt for some other device? */ 772 if (ints == 0) 773 return IRQ_NOTMINE; 774 775 if (ints & OHCI_INTR_UE) { 776 // e.g. due to PCI Master/Target Abort 777 if (quirk_nec(ohci)) { 778 /* Workaround for a silicon bug in some NEC chips used 779 * in Apple's PowerBooks. Adapted from Darwin code. 780 */ 781 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 782 783 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 784 785 schedule_work (&ohci->nec_work); 786 } else { 787 disable (ohci); 788 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 789 } 790 791 ohci_dump (ohci, 1); 792 ohci_usb_reset (ohci); 793 } 794 795 if (ints & OHCI_INTR_RHSC) { 796 ohci_vdbg(ohci, "rhsc\n"); 797 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 798 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 799 ®s->intrstatus); 800 801 /* NOTE: Vendors didn't always make the same implementation 802 * choices for RHSC. Many followed the spec; RHSC triggers 803 * on an edge, like setting and maybe clearing a port status 804 * change bit. With others it's level-triggered, active 805 * until khubd clears all the port status change bits. We'll 806 * always disable it here and rely on polling until khubd 807 * re-enables it. 808 */ 809 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 810 usb_hcd_poll_rh_status(hcd); 811 } 812 813 /* For connect and disconnect events, we expect the controller 814 * to turn on RHSC along with RD. But for remote wakeup events 815 * this might not happen. 816 */ 817 else if (ints & OHCI_INTR_RD) { 818 ohci_vdbg(ohci, "resume detect\n"); 819 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 820 hcd->poll_rh = 1; 821 if (ohci->autostop) { 822 spin_lock (&ohci->lock); 823 ohci_rh_resume (ohci); 824 spin_unlock (&ohci->lock); 825 } else 826 usb_hcd_resume_root_hub(hcd); 827 } 828 829 if (ints & OHCI_INTR_WDH) { 830 spin_lock (&ohci->lock); 831 dl_done_list (ohci); 832 spin_unlock (&ohci->lock); 833 } 834 835 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 836 spin_lock(&ohci->lock); 837 if (ohci->ed_to_check) { 838 struct ed *ed = ohci->ed_to_check; 839 840 if (check_ed(ohci, ed)) { 841 /* HC thinks the TD list is empty; HCD knows 842 * at least one TD is outstanding 843 */ 844 if (--ohci->zf_delay == 0) { 845 struct td *td = list_entry( 846 ed->td_list.next, 847 struct td, td_list); 848 ohci_warn(ohci, 849 "Reclaiming orphan TD %p\n", 850 td); 851 takeback_td(ohci, td); 852 ohci->ed_to_check = NULL; 853 } 854 } else 855 ohci->ed_to_check = NULL; 856 } 857 spin_unlock(&ohci->lock); 858 } 859 860 /* could track INTR_SO to reduce available PCI/... bandwidth */ 861 862 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 863 * when there's still unlinking to be done (next frame). 864 */ 865 spin_lock (&ohci->lock); 866 if (ohci->ed_rm_list) 867 finish_unlinks (ohci, ohci_frame_no(ohci)); 868 if ((ints & OHCI_INTR_SF) != 0 869 && !ohci->ed_rm_list 870 && !ohci->ed_to_check 871 && HC_IS_RUNNING(hcd->state)) 872 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 873 spin_unlock (&ohci->lock); 874 875 if (HC_IS_RUNNING(hcd->state)) { 876 ohci_writel (ohci, ints, ®s->intrstatus); 877 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 878 // flush those writes 879 (void) ohci_readl (ohci, &ohci->regs->control); 880 } 881 882 return IRQ_HANDLED; 883 } 884 885 /*-------------------------------------------------------------------------*/ 886 887 static void ohci_stop (struct usb_hcd *hcd) 888 { 889 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 890 891 ohci_dump (ohci, 1); 892 893 flush_scheduled_work(); 894 895 ohci_usb_reset (ohci); 896 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 897 free_irq(hcd->irq, hcd); 898 hcd->irq = -1; 899 900 if (quirk_zfmicro(ohci)) 901 del_timer(&ohci->unlink_watchdog); 902 if (quirk_amdiso(ohci)) 903 amd_iso_dev_put(); 904 905 remove_debug_files (ohci); 906 ohci_mem_cleanup (ohci); 907 if (ohci->hcca) { 908 dma_free_coherent (hcd->self.controller, 909 sizeof *ohci->hcca, 910 ohci->hcca, ohci->hcca_dma); 911 ohci->hcca = NULL; 912 ohci->hcca_dma = 0; 913 } 914 } 915 916 /*-------------------------------------------------------------------------*/ 917 918 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 919 920 /* must not be called from interrupt context */ 921 static int ohci_restart (struct ohci_hcd *ohci) 922 { 923 int temp; 924 int i; 925 struct urb_priv *priv; 926 927 spin_lock_irq(&ohci->lock); 928 disable (ohci); 929 930 /* Recycle any "live" eds/tds (and urbs). */ 931 if (!list_empty (&ohci->pending)) 932 ohci_dbg(ohci, "abort schedule...\n"); 933 list_for_each_entry (priv, &ohci->pending, pending) { 934 struct urb *urb = priv->td[0]->urb; 935 struct ed *ed = priv->ed; 936 937 switch (ed->state) { 938 case ED_OPER: 939 ed->state = ED_UNLINK; 940 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 941 ed_deschedule (ohci, ed); 942 943 ed->ed_next = ohci->ed_rm_list; 944 ed->ed_prev = NULL; 945 ohci->ed_rm_list = ed; 946 /* FALLTHROUGH */ 947 case ED_UNLINK: 948 break; 949 default: 950 ohci_dbg(ohci, "bogus ed %p state %d\n", 951 ed, ed->state); 952 } 953 954 if (!urb->unlinked) 955 urb->unlinked = -ESHUTDOWN; 956 } 957 finish_unlinks (ohci, 0); 958 spin_unlock_irq(&ohci->lock); 959 960 /* paranoia, in case that didn't work: */ 961 962 /* empty the interrupt branches */ 963 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 964 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 965 966 /* no EDs to remove */ 967 ohci->ed_rm_list = NULL; 968 969 /* empty control and bulk lists */ 970 ohci->ed_controltail = NULL; 971 ohci->ed_bulktail = NULL; 972 973 if ((temp = ohci_run (ohci)) < 0) { 974 ohci_err (ohci, "can't restart, %d\n", temp); 975 return temp; 976 } 977 ohci_dbg(ohci, "restart complete\n"); 978 return 0; 979 } 980 981 #endif 982 983 /*-------------------------------------------------------------------------*/ 984 985 MODULE_AUTHOR (DRIVER_AUTHOR); 986 MODULE_DESCRIPTION(DRIVER_DESC); 987 MODULE_LICENSE ("GPL"); 988 989 #ifdef CONFIG_PCI 990 #include "ohci-pci.c" 991 #define PCI_DRIVER ohci_pci_driver 992 #endif 993 994 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 995 #include "ohci-sa1111.c" 996 #define SA1111_DRIVER ohci_hcd_sa1111_driver 997 #endif 998 999 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1000 #include "ohci-s3c2410.c" 1001 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1002 #endif 1003 1004 #ifdef CONFIG_ARCH_OMAP 1005 #include "ohci-omap.c" 1006 #define PLATFORM_DRIVER ohci_hcd_omap_driver 1007 #endif 1008 1009 #ifdef CONFIG_ARCH_LH7A404 1010 #include "ohci-lh7a404.c" 1011 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver 1012 #endif 1013 1014 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1015 #include "ohci-pxa27x.c" 1016 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1017 #endif 1018 1019 #ifdef CONFIG_ARCH_EP93XX 1020 #include "ohci-ep93xx.c" 1021 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1022 #endif 1023 1024 #ifdef CONFIG_SOC_AU1X00 1025 #include "ohci-au1xxx.c" 1026 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1027 #endif 1028 1029 #ifdef CONFIG_PNX8550 1030 #include "ohci-pnx8550.c" 1031 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1032 #endif 1033 1034 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1035 #include "ohci-ppc-soc.c" 1036 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1037 #endif 1038 1039 #ifdef CONFIG_ARCH_AT91 1040 #include "ohci-at91.c" 1041 #define PLATFORM_DRIVER ohci_hcd_at91_driver 1042 #endif 1043 1044 #ifdef CONFIG_ARCH_PNX4008 1045 #include "ohci-pnx4008.c" 1046 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1047 #endif 1048 1049 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 1050 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 1051 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 1052 defined(CONFIG_CPU_SUBTYPE_SH7786) 1053 #include "ohci-sh.c" 1054 #define PLATFORM_DRIVER ohci_hcd_sh_driver 1055 #endif 1056 1057 1058 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1059 #include "ohci-ppc-of.c" 1060 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1061 #endif 1062 1063 #ifdef CONFIG_PPC_PS3 1064 #include "ohci-ps3.c" 1065 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1066 #endif 1067 1068 #ifdef CONFIG_USB_OHCI_HCD_SSB 1069 #include "ohci-ssb.c" 1070 #define SSB_OHCI_DRIVER ssb_ohci_driver 1071 #endif 1072 1073 #ifdef CONFIG_MFD_SM501 1074 #include "ohci-sm501.c" 1075 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1076 #endif 1077 1078 #ifdef CONFIG_MFD_TC6393XB 1079 #include "ohci-tmio.c" 1080 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver 1081 #endif 1082 1083 #if !defined(PCI_DRIVER) && \ 1084 !defined(PLATFORM_DRIVER) && \ 1085 !defined(OF_PLATFORM_DRIVER) && \ 1086 !defined(SA1111_DRIVER) && \ 1087 !defined(PS3_SYSTEM_BUS_DRIVER) && \ 1088 !defined(SM501_OHCI_DRIVER) && \ 1089 !defined(TMIO_OHCI_DRIVER) && \ 1090 !defined(SSB_OHCI_DRIVER) 1091 #error "missing bus glue for ohci-hcd" 1092 #endif 1093 1094 static int __init ohci_hcd_mod_init(void) 1095 { 1096 int retval = 0; 1097 1098 if (usb_disabled()) 1099 return -ENODEV; 1100 1101 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1102 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1103 sizeof (struct ed), sizeof (struct td)); 1104 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1105 1106 #ifdef DEBUG 1107 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); 1108 if (!ohci_debug_root) { 1109 retval = -ENOENT; 1110 goto error_debug; 1111 } 1112 #endif 1113 1114 #ifdef PS3_SYSTEM_BUS_DRIVER 1115 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1116 if (retval < 0) 1117 goto error_ps3; 1118 #endif 1119 1120 #ifdef PLATFORM_DRIVER 1121 retval = platform_driver_register(&PLATFORM_DRIVER); 1122 if (retval < 0) 1123 goto error_platform; 1124 #endif 1125 1126 #ifdef OF_PLATFORM_DRIVER 1127 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1128 if (retval < 0) 1129 goto error_of_platform; 1130 #endif 1131 1132 #ifdef SA1111_DRIVER 1133 retval = sa1111_driver_register(&SA1111_DRIVER); 1134 if (retval < 0) 1135 goto error_sa1111; 1136 #endif 1137 1138 #ifdef PCI_DRIVER 1139 retval = pci_register_driver(&PCI_DRIVER); 1140 if (retval < 0) 1141 goto error_pci; 1142 #endif 1143 1144 #ifdef SSB_OHCI_DRIVER 1145 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1146 if (retval) 1147 goto error_ssb; 1148 #endif 1149 1150 #ifdef SM501_OHCI_DRIVER 1151 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1152 if (retval < 0) 1153 goto error_sm501; 1154 #endif 1155 1156 #ifdef TMIO_OHCI_DRIVER 1157 retval = platform_driver_register(&TMIO_OHCI_DRIVER); 1158 if (retval < 0) 1159 goto error_tmio; 1160 #endif 1161 1162 return retval; 1163 1164 /* Error path */ 1165 #ifdef TMIO_OHCI_DRIVER 1166 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1167 error_tmio: 1168 #endif 1169 #ifdef SM501_OHCI_DRIVER 1170 platform_driver_unregister(&SM501_OHCI_DRIVER); 1171 error_sm501: 1172 #endif 1173 #ifdef SSB_OHCI_DRIVER 1174 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1175 error_ssb: 1176 #endif 1177 #ifdef PCI_DRIVER 1178 pci_unregister_driver(&PCI_DRIVER); 1179 error_pci: 1180 #endif 1181 #ifdef SA1111_DRIVER 1182 sa1111_driver_unregister(&SA1111_DRIVER); 1183 error_sa1111: 1184 #endif 1185 #ifdef OF_PLATFORM_DRIVER 1186 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1187 error_of_platform: 1188 #endif 1189 #ifdef PLATFORM_DRIVER 1190 platform_driver_unregister(&PLATFORM_DRIVER); 1191 error_platform: 1192 #endif 1193 #ifdef PS3_SYSTEM_BUS_DRIVER 1194 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1195 error_ps3: 1196 #endif 1197 #ifdef DEBUG 1198 debugfs_remove(ohci_debug_root); 1199 ohci_debug_root = NULL; 1200 error_debug: 1201 #endif 1202 1203 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1204 return retval; 1205 } 1206 module_init(ohci_hcd_mod_init); 1207 1208 static void __exit ohci_hcd_mod_exit(void) 1209 { 1210 #ifdef TMIO_OHCI_DRIVER 1211 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1212 #endif 1213 #ifdef SM501_OHCI_DRIVER 1214 platform_driver_unregister(&SM501_OHCI_DRIVER); 1215 #endif 1216 #ifdef SSB_OHCI_DRIVER 1217 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1218 #endif 1219 #ifdef PCI_DRIVER 1220 pci_unregister_driver(&PCI_DRIVER); 1221 #endif 1222 #ifdef SA1111_DRIVER 1223 sa1111_driver_unregister(&SA1111_DRIVER); 1224 #endif 1225 #ifdef OF_PLATFORM_DRIVER 1226 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1227 #endif 1228 #ifdef PLATFORM_DRIVER 1229 platform_driver_unregister(&PLATFORM_DRIVER); 1230 #endif 1231 #ifdef PS3_SYSTEM_BUS_DRIVER 1232 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1233 #endif 1234 #ifdef DEBUG 1235 debugfs_remove(ohci_debug_root); 1236 #endif 1237 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1238 } 1239 module_exit(ohci_hcd_mod_exit); 1240 1241