1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * 13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 14 * interfaces (though some non-x86 Intel chips use it). It supports 15 * smarter hardware than UHCI. A download link for the spec available 16 * through the http://www.usb.org website. 17 * 18 * This file is licenced under the GPL. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 #include <linux/delay.h> 26 #include <linux/ioport.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/timer.h> 32 #include <linux/list.h> 33 #include <linux/usb.h> 34 #include <linux/usb/otg.h> 35 #include <linux/usb/hcd.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/dmapool.h> 38 #include <linux/workqueue.h> 39 #include <linux/debugfs.h> 40 41 #include <asm/io.h> 42 #include <asm/irq.h> 43 #include <asm/system.h> 44 #include <asm/unaligned.h> 45 #include <asm/byteorder.h> 46 47 48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 50 51 /*-------------------------------------------------------------------------*/ 52 53 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 54 55 /* For initializing controller (mask in an HCFS mode too) */ 56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 57 #define OHCI_INTR_INIT \ 58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 59 | OHCI_INTR_RD | OHCI_INTR_WDH) 60 61 #ifdef __hppa__ 62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 63 #define IR_DISABLE 64 #endif 65 66 #ifdef CONFIG_ARCH_OMAP 67 /* OMAP doesn't support IR (no SMM; not needed) */ 68 #define IR_DISABLE 69 #endif 70 71 /*-------------------------------------------------------------------------*/ 72 73 static const char hcd_name [] = "ohci_hcd"; 74 75 #define STATECHANGE_DELAY msecs_to_jiffies(300) 76 77 #include "ohci.h" 78 #include "pci-quirks.h" 79 80 static void ohci_dump (struct ohci_hcd *ohci, int verbose); 81 static int ohci_init (struct ohci_hcd *ohci); 82 static void ohci_stop (struct usb_hcd *hcd); 83 84 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 85 static int ohci_restart (struct ohci_hcd *ohci); 86 #endif 87 88 #ifdef CONFIG_PCI 89 static void sb800_prefetch(struct ohci_hcd *ohci, int on); 90 #else 91 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) 92 { 93 return; 94 } 95 #endif 96 97 98 #include "ohci-hub.c" 99 #include "ohci-dbg.c" 100 #include "ohci-mem.c" 101 #include "ohci-q.c" 102 103 104 /* 105 * On architectures with edge-triggered interrupts we must never return 106 * IRQ_NONE. 107 */ 108 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 109 #define IRQ_NOTMINE IRQ_HANDLED 110 #else 111 #define IRQ_NOTMINE IRQ_NONE 112 #endif 113 114 115 /* Some boards misreport power switching/overcurrent */ 116 static int distrust_firmware = 1; 117 module_param (distrust_firmware, bool, 0); 118 MODULE_PARM_DESC (distrust_firmware, 119 "true to distrust firmware power/overcurrent setup"); 120 121 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 122 static int no_handshake = 0; 123 module_param (no_handshake, bool, 0); 124 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 125 126 /*-------------------------------------------------------------------------*/ 127 128 /* 129 * queue up an urb for anything except the root hub 130 */ 131 static int ohci_urb_enqueue ( 132 struct usb_hcd *hcd, 133 struct urb *urb, 134 gfp_t mem_flags 135 ) { 136 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 137 struct ed *ed; 138 urb_priv_t *urb_priv; 139 unsigned int pipe = urb->pipe; 140 int i, size = 0; 141 unsigned long flags; 142 int retval = 0; 143 144 #ifdef OHCI_VERBOSE_DEBUG 145 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 146 #endif 147 148 /* every endpoint has a ed, locate and maybe (re)initialize it */ 149 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 150 return -ENOMEM; 151 152 /* for the private part of the URB we need the number of TDs (size) */ 153 switch (ed->type) { 154 case PIPE_CONTROL: 155 /* td_submit_urb() doesn't yet handle these */ 156 if (urb->transfer_buffer_length > 4096) 157 return -EMSGSIZE; 158 159 /* 1 TD for setup, 1 for ACK, plus ... */ 160 size = 2; 161 /* FALLTHROUGH */ 162 // case PIPE_INTERRUPT: 163 // case PIPE_BULK: 164 default: 165 /* one TD for every 4096 Bytes (can be up to 8K) */ 166 size += urb->transfer_buffer_length / 4096; 167 /* ... and for any remaining bytes ... */ 168 if ((urb->transfer_buffer_length % 4096) != 0) 169 size++; 170 /* ... and maybe a zero length packet to wrap it up */ 171 if (size == 0) 172 size++; 173 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 174 && (urb->transfer_buffer_length 175 % usb_maxpacket (urb->dev, pipe, 176 usb_pipeout (pipe))) == 0) 177 size++; 178 break; 179 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 180 size = urb->number_of_packets; 181 break; 182 } 183 184 /* allocate the private part of the URB */ 185 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 186 mem_flags); 187 if (!urb_priv) 188 return -ENOMEM; 189 INIT_LIST_HEAD (&urb_priv->pending); 190 urb_priv->length = size; 191 urb_priv->ed = ed; 192 193 /* allocate the TDs (deferring hash chain updates) */ 194 for (i = 0; i < size; i++) { 195 urb_priv->td [i] = td_alloc (ohci, mem_flags); 196 if (!urb_priv->td [i]) { 197 urb_priv->length = i; 198 urb_free_priv (ohci, urb_priv); 199 return -ENOMEM; 200 } 201 } 202 203 spin_lock_irqsave (&ohci->lock, flags); 204 205 /* don't submit to a dead HC */ 206 if (!HCD_HW_ACCESSIBLE(hcd)) { 207 retval = -ENODEV; 208 goto fail; 209 } 210 if (!HC_IS_RUNNING(hcd->state)) { 211 retval = -ENODEV; 212 goto fail; 213 } 214 retval = usb_hcd_link_urb_to_ep(hcd, urb); 215 if (retval) 216 goto fail; 217 218 /* schedule the ed if needed */ 219 if (ed->state == ED_IDLE) { 220 retval = ed_schedule (ohci, ed); 221 if (retval < 0) { 222 usb_hcd_unlink_urb_from_ep(hcd, urb); 223 goto fail; 224 } 225 if (ed->type == PIPE_ISOCHRONOUS) { 226 u16 frame = ohci_frame_no(ohci); 227 228 /* delay a few frames before the first TD */ 229 frame += max_t (u16, 8, ed->interval); 230 frame &= ~(ed->interval - 1); 231 frame |= ed->branch; 232 urb->start_frame = frame; 233 234 /* yes, only URB_ISO_ASAP is supported, and 235 * urb->start_frame is never used as input. 236 */ 237 } 238 } else if (ed->type == PIPE_ISOCHRONOUS) 239 urb->start_frame = ed->last_iso + ed->interval; 240 241 /* fill the TDs and link them to the ed; and 242 * enable that part of the schedule, if needed 243 * and update count of queued periodic urbs 244 */ 245 urb->hcpriv = urb_priv; 246 td_submit_urb (ohci, urb); 247 248 fail: 249 if (retval) 250 urb_free_priv (ohci, urb_priv); 251 spin_unlock_irqrestore (&ohci->lock, flags); 252 return retval; 253 } 254 255 /* 256 * decouple the URB from the HC queues (TDs, urb_priv). 257 * reporting is always done 258 * asynchronously, and we might be dealing with an urb that's 259 * partially transferred, or an ED with other urbs being unlinked. 260 */ 261 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 262 { 263 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 264 unsigned long flags; 265 int rc; 266 267 #ifdef OHCI_VERBOSE_DEBUG 268 urb_print(urb, "UNLINK", 1, status); 269 #endif 270 271 spin_lock_irqsave (&ohci->lock, flags); 272 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 273 if (rc) { 274 ; /* Do nothing */ 275 } else if (HC_IS_RUNNING(hcd->state)) { 276 urb_priv_t *urb_priv; 277 278 /* Unless an IRQ completed the unlink while it was being 279 * handed to us, flag it for unlink and giveback, and force 280 * some upcoming INTR_SF to call finish_unlinks() 281 */ 282 urb_priv = urb->hcpriv; 283 if (urb_priv) { 284 if (urb_priv->ed->state == ED_OPER) 285 start_ed_unlink (ohci, urb_priv->ed); 286 } 287 } else { 288 /* 289 * with HC dead, we won't respect hc queue pointers 290 * any more ... just clean up every urb's memory. 291 */ 292 if (urb->hcpriv) 293 finish_urb(ohci, urb, status); 294 } 295 spin_unlock_irqrestore (&ohci->lock, flags); 296 return rc; 297 } 298 299 /*-------------------------------------------------------------------------*/ 300 301 /* frees config/altsetting state for endpoints, 302 * including ED memory, dummy TD, and bulk/intr data toggle 303 */ 304 305 static void 306 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 307 { 308 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 309 unsigned long flags; 310 struct ed *ed = ep->hcpriv; 311 unsigned limit = 1000; 312 313 /* ASSERT: any requests/urbs are being unlinked */ 314 /* ASSERT: nobody can be submitting urbs for this any more */ 315 316 if (!ed) 317 return; 318 319 rescan: 320 spin_lock_irqsave (&ohci->lock, flags); 321 322 if (!HC_IS_RUNNING (hcd->state)) { 323 sanitize: 324 ed->state = ED_IDLE; 325 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 326 ohci->eds_scheduled--; 327 finish_unlinks (ohci, 0); 328 } 329 330 switch (ed->state) { 331 case ED_UNLINK: /* wait for hw to finish? */ 332 /* major IRQ delivery trouble loses INTR_SF too... */ 333 if (limit-- == 0) { 334 ohci_warn(ohci, "ED unlink timeout\n"); 335 if (quirk_zfmicro(ohci)) { 336 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 337 ohci->ed_to_check = ed; 338 ohci->zf_delay = 2; 339 } 340 goto sanitize; 341 } 342 spin_unlock_irqrestore (&ohci->lock, flags); 343 schedule_timeout_uninterruptible(1); 344 goto rescan; 345 case ED_IDLE: /* fully unlinked */ 346 if (list_empty (&ed->td_list)) { 347 td_free (ohci, ed->dummy); 348 ed_free (ohci, ed); 349 break; 350 } 351 /* else FALL THROUGH */ 352 default: 353 /* caller was supposed to have unlinked any requests; 354 * that's not our job. can't recover; must leak ed. 355 */ 356 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 357 ed, ep->desc.bEndpointAddress, ed->state, 358 list_empty (&ed->td_list) ? "" : " (has tds)"); 359 td_free (ohci, ed->dummy); 360 break; 361 } 362 ep->hcpriv = NULL; 363 spin_unlock_irqrestore (&ohci->lock, flags); 364 } 365 366 static int ohci_get_frame (struct usb_hcd *hcd) 367 { 368 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 369 370 return ohci_frame_no(ohci); 371 } 372 373 static void ohci_usb_reset (struct ohci_hcd *ohci) 374 { 375 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 376 ohci->hc_control &= OHCI_CTRL_RWC; 377 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 378 } 379 380 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 381 * other cases where the next software may expect clean state from the 382 * "firmware". this is bus-neutral, unlike shutdown() methods. 383 */ 384 static void 385 ohci_shutdown (struct usb_hcd *hcd) 386 { 387 struct ohci_hcd *ohci; 388 389 ohci = hcd_to_ohci (hcd); 390 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 391 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); 392 393 /* If the SHUTDOWN quirk is set, don't put the controller in RESET */ 394 ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ? 395 OHCI_CTRL_RWC | OHCI_CTRL_HCFS : 396 OHCI_CTRL_RWC); 397 ohci_writel(ohci, ohci->hc_control, &ohci->regs->control); 398 399 /* flush the writes */ 400 (void) ohci_readl (ohci, &ohci->regs->control); 401 } 402 403 static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 404 { 405 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 406 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 407 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 408 && !list_empty(&ed->td_list); 409 } 410 411 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 412 * an interrupt TD but neglects to add it to the donelist. On systems with 413 * this chipset, we need to periodically check the state of the queues to look 414 * for such "lost" TDs. 415 */ 416 static void unlink_watchdog_func(unsigned long _ohci) 417 { 418 unsigned long flags; 419 unsigned max; 420 unsigned seen_count = 0; 421 unsigned i; 422 struct ed **seen = NULL; 423 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 424 425 spin_lock_irqsave(&ohci->lock, flags); 426 max = ohci->eds_scheduled; 427 if (!max) 428 goto done; 429 430 if (ohci->ed_to_check) 431 goto out; 432 433 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 434 if (!seen) 435 goto out; 436 437 for (i = 0; i < NUM_INTS; i++) { 438 struct ed *ed = ohci->periodic[i]; 439 440 while (ed) { 441 unsigned temp; 442 443 /* scan this branch of the periodic schedule tree */ 444 for (temp = 0; temp < seen_count; temp++) { 445 if (seen[temp] == ed) { 446 /* we've checked it and what's after */ 447 ed = NULL; 448 break; 449 } 450 } 451 if (!ed) 452 break; 453 seen[seen_count++] = ed; 454 if (!check_ed(ohci, ed)) { 455 ed = ed->ed_next; 456 continue; 457 } 458 459 /* HC's TD list is empty, but HCD sees at least one 460 * TD that's not been sent through the donelist. 461 */ 462 ohci->ed_to_check = ed; 463 ohci->zf_delay = 2; 464 465 /* The HC may wait until the next frame to report the 466 * TD as done through the donelist and INTR_WDH. (We 467 * just *assume* it's not a multi-TD interrupt URB; 468 * those could defer the IRQ more than one frame, using 469 * DI...) Check again after the next INTR_SF. 470 */ 471 ohci_writel(ohci, OHCI_INTR_SF, 472 &ohci->regs->intrstatus); 473 ohci_writel(ohci, OHCI_INTR_SF, 474 &ohci->regs->intrenable); 475 476 /* flush those writes */ 477 (void) ohci_readl(ohci, &ohci->regs->control); 478 479 goto out; 480 } 481 } 482 out: 483 kfree(seen); 484 if (ohci->eds_scheduled) 485 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 486 done: 487 spin_unlock_irqrestore(&ohci->lock, flags); 488 } 489 490 /*-------------------------------------------------------------------------* 491 * HC functions 492 *-------------------------------------------------------------------------*/ 493 494 /* init memory, and kick BIOS/SMM off */ 495 496 static int ohci_init (struct ohci_hcd *ohci) 497 { 498 int ret; 499 struct usb_hcd *hcd = ohci_to_hcd(ohci); 500 501 if (distrust_firmware) 502 ohci->flags |= OHCI_QUIRK_HUB_POWER; 503 504 disable (ohci); 505 ohci->regs = hcd->regs; 506 507 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 508 * was never needed for most non-PCI systems ... remove the code? 509 */ 510 511 #ifndef IR_DISABLE 512 /* SMM owns the HC? not for long! */ 513 if (!no_handshake && ohci_readl (ohci, 514 &ohci->regs->control) & OHCI_CTRL_IR) { 515 u32 temp; 516 517 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 518 519 /* this timeout is arbitrary. we make it long, so systems 520 * depending on usb keyboards may be usable even if the 521 * BIOS/SMM code seems pretty broken. 522 */ 523 temp = 500; /* arbitrary: five seconds */ 524 525 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 526 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 527 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 528 msleep (10); 529 if (--temp == 0) { 530 ohci_err (ohci, "USB HC takeover failed!" 531 " (BIOS/SMM bug)\n"); 532 return -EBUSY; 533 } 534 } 535 ohci_usb_reset (ohci); 536 } 537 #endif 538 539 /* Disable HC interrupts */ 540 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 541 542 /* flush the writes, and save key bits like RWC */ 543 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 544 ohci->hc_control |= OHCI_CTRL_RWC; 545 546 /* Read the number of ports unless overridden */ 547 if (ohci->num_ports == 0) 548 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 549 550 if (ohci->hcca) 551 return 0; 552 553 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 554 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 555 if (!ohci->hcca) 556 return -ENOMEM; 557 558 if ((ret = ohci_mem_init (ohci)) < 0) 559 ohci_stop (hcd); 560 else { 561 create_debug_files (ohci); 562 } 563 564 return ret; 565 } 566 567 /*-------------------------------------------------------------------------*/ 568 569 /* Start an OHCI controller, set the BUS operational 570 * resets USB and controller 571 * enable interrupts 572 */ 573 static int ohci_run (struct ohci_hcd *ohci) 574 { 575 u32 mask, val; 576 int first = ohci->fminterval == 0; 577 struct usb_hcd *hcd = ohci_to_hcd(ohci); 578 579 disable (ohci); 580 581 /* boot firmware should have set this up (5.1.1.3.1) */ 582 if (first) { 583 584 val = ohci_readl (ohci, &ohci->regs->fminterval); 585 ohci->fminterval = val & 0x3fff; 586 if (ohci->fminterval != FI) 587 ohci_dbg (ohci, "fminterval delta %d\n", 588 ohci->fminterval - FI); 589 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 590 /* also: power/overcurrent flags in roothub.a */ 591 } 592 593 /* Reset USB nearly "by the book". RemoteWakeupConnected has 594 * to be checked in case boot firmware (BIOS/SMM/...) has set up 595 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). 596 * If the bus glue detected wakeup capability then it should 597 * already be enabled; if so we'll just enable it again. 598 */ 599 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) 600 device_set_wakeup_capable(hcd->self.controller, 1); 601 602 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 603 case OHCI_USB_OPER: 604 val = 0; 605 break; 606 case OHCI_USB_SUSPEND: 607 case OHCI_USB_RESUME: 608 ohci->hc_control &= OHCI_CTRL_RWC; 609 ohci->hc_control |= OHCI_USB_RESUME; 610 val = 10 /* msec wait */; 611 break; 612 // case OHCI_USB_RESET: 613 default: 614 ohci->hc_control &= OHCI_CTRL_RWC; 615 ohci->hc_control |= OHCI_USB_RESET; 616 val = 50 /* msec wait */; 617 break; 618 } 619 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 620 // flush the writes 621 (void) ohci_readl (ohci, &ohci->regs->control); 622 msleep(val); 623 624 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 625 626 /* 2msec timelimit here means no irqs/preempt */ 627 spin_lock_irq (&ohci->lock); 628 629 retry: 630 /* HC Reset requires max 10 us delay */ 631 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 632 val = 30; /* ... allow extra time */ 633 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 634 if (--val == 0) { 635 spin_unlock_irq (&ohci->lock); 636 ohci_err (ohci, "USB HC reset timed out!\n"); 637 return -1; 638 } 639 udelay (1); 640 } 641 642 /* now we're in the SUSPEND state ... must go OPERATIONAL 643 * within 2msec else HC enters RESUME 644 * 645 * ... but some hardware won't init fmInterval "by the book" 646 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 647 * this if we write fmInterval after we're OPERATIONAL. 648 * Unclear about ALi, ServerWorks, and others ... this could 649 * easily be a longstanding bug in chip init on Linux. 650 */ 651 if (ohci->flags & OHCI_QUIRK_INITRESET) { 652 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 653 // flush those writes 654 (void) ohci_readl (ohci, &ohci->regs->control); 655 } 656 657 /* Tell the controller where the control and bulk lists are 658 * The lists are empty now. */ 659 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 660 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 661 662 /* a reset clears this */ 663 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 664 665 periodic_reinit (ohci); 666 667 /* some OHCI implementations are finicky about how they init. 668 * bogus values here mean not even enumeration could work. 669 */ 670 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 671 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 672 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 673 ohci->flags |= OHCI_QUIRK_INITRESET; 674 ohci_dbg (ohci, "enabling initreset quirk\n"); 675 goto retry; 676 } 677 spin_unlock_irq (&ohci->lock); 678 ohci_err (ohci, "init err (%08x %04x)\n", 679 ohci_readl (ohci, &ohci->regs->fminterval), 680 ohci_readl (ohci, &ohci->regs->periodicstart)); 681 return -EOVERFLOW; 682 } 683 684 /* use rhsc irqs after khubd is fully initialized */ 685 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 686 hcd->uses_new_polling = 1; 687 688 /* start controller operations */ 689 ohci->hc_control &= OHCI_CTRL_RWC; 690 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 691 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 692 hcd->state = HC_STATE_RUNNING; 693 694 /* wake on ConnectStatusChange, matching external hubs */ 695 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 696 697 /* Choose the interrupts we care about now, others later on demand */ 698 mask = OHCI_INTR_INIT; 699 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 700 ohci_writel (ohci, mask, &ohci->regs->intrenable); 701 702 /* handle root hub init quirks ... */ 703 val = roothub_a (ohci); 704 val &= ~(RH_A_PSM | RH_A_OCPM); 705 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 706 /* NSC 87560 and maybe others */ 707 val |= RH_A_NOCP; 708 val &= ~(RH_A_POTPGT | RH_A_NPS); 709 ohci_writel (ohci, val, &ohci->regs->roothub.a); 710 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 711 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 712 /* hub power always on; required for AMD-756 and some 713 * Mac platforms. ganged overcurrent reporting, if any. 714 */ 715 val |= RH_A_NPS; 716 ohci_writel (ohci, val, &ohci->regs->roothub.a); 717 } 718 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 719 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, 720 &ohci->regs->roothub.b); 721 // flush those writes 722 (void) ohci_readl (ohci, &ohci->regs->control); 723 724 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 725 spin_unlock_irq (&ohci->lock); 726 727 // POTPGT delay is bits 24-31, in 2 ms units. 728 mdelay ((val >> 23) & 0x1fe); 729 hcd->state = HC_STATE_RUNNING; 730 731 if (quirk_zfmicro(ohci)) { 732 /* Create timer to watch for bad queue state on ZF Micro */ 733 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 734 (unsigned long) ohci); 735 736 ohci->eds_scheduled = 0; 737 ohci->ed_to_check = NULL; 738 } 739 740 ohci_dump (ohci, 1); 741 742 return 0; 743 } 744 745 /*-------------------------------------------------------------------------*/ 746 747 /* an interrupt happens */ 748 749 static irqreturn_t ohci_irq (struct usb_hcd *hcd) 750 { 751 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 752 struct ohci_regs __iomem *regs = ohci->regs; 753 int ints; 754 755 /* Read interrupt status (and flush pending writes). We ignore the 756 * optimization of checking the LSB of hcca->done_head; it doesn't 757 * work on all systems (edge triggering for OHCI can be a factor). 758 */ 759 ints = ohci_readl(ohci, ®s->intrstatus); 760 761 /* Check for an all 1's result which is a typical consequence 762 * of dead, unclocked, or unplugged (CardBus...) devices 763 */ 764 if (ints == ~(u32)0) { 765 disable (ohci); 766 ohci_dbg (ohci, "device removed!\n"); 767 usb_hc_died(hcd); 768 return IRQ_HANDLED; 769 } 770 771 /* We only care about interrupts that are enabled */ 772 ints &= ohci_readl(ohci, ®s->intrenable); 773 774 /* interrupt for some other device? */ 775 if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT)) 776 return IRQ_NOTMINE; 777 778 if (ints & OHCI_INTR_UE) { 779 // e.g. due to PCI Master/Target Abort 780 if (quirk_nec(ohci)) { 781 /* Workaround for a silicon bug in some NEC chips used 782 * in Apple's PowerBooks. Adapted from Darwin code. 783 */ 784 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 785 786 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 787 788 schedule_work (&ohci->nec_work); 789 } else { 790 disable (ohci); 791 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 792 usb_hc_died(hcd); 793 } 794 795 ohci_dump (ohci, 1); 796 ohci_usb_reset (ohci); 797 } 798 799 if (ints & OHCI_INTR_RHSC) { 800 ohci_vdbg(ohci, "rhsc\n"); 801 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 802 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 803 ®s->intrstatus); 804 805 /* NOTE: Vendors didn't always make the same implementation 806 * choices for RHSC. Many followed the spec; RHSC triggers 807 * on an edge, like setting and maybe clearing a port status 808 * change bit. With others it's level-triggered, active 809 * until khubd clears all the port status change bits. We'll 810 * always disable it here and rely on polling until khubd 811 * re-enables it. 812 */ 813 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 814 usb_hcd_poll_rh_status(hcd); 815 } 816 817 /* For connect and disconnect events, we expect the controller 818 * to turn on RHSC along with RD. But for remote wakeup events 819 * this might not happen. 820 */ 821 else if (ints & OHCI_INTR_RD) { 822 ohci_vdbg(ohci, "resume detect\n"); 823 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 824 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 825 if (ohci->autostop) { 826 spin_lock (&ohci->lock); 827 ohci_rh_resume (ohci); 828 spin_unlock (&ohci->lock); 829 } else 830 usb_hcd_resume_root_hub(hcd); 831 } 832 833 if (ints & OHCI_INTR_WDH) { 834 spin_lock (&ohci->lock); 835 dl_done_list (ohci); 836 spin_unlock (&ohci->lock); 837 } 838 839 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 840 spin_lock(&ohci->lock); 841 if (ohci->ed_to_check) { 842 struct ed *ed = ohci->ed_to_check; 843 844 if (check_ed(ohci, ed)) { 845 /* HC thinks the TD list is empty; HCD knows 846 * at least one TD is outstanding 847 */ 848 if (--ohci->zf_delay == 0) { 849 struct td *td = list_entry( 850 ed->td_list.next, 851 struct td, td_list); 852 ohci_warn(ohci, 853 "Reclaiming orphan TD %p\n", 854 td); 855 takeback_td(ohci, td); 856 ohci->ed_to_check = NULL; 857 } 858 } else 859 ohci->ed_to_check = NULL; 860 } 861 spin_unlock(&ohci->lock); 862 } 863 864 /* could track INTR_SO to reduce available PCI/... bandwidth */ 865 866 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 867 * when there's still unlinking to be done (next frame). 868 */ 869 spin_lock (&ohci->lock); 870 if (ohci->ed_rm_list) 871 finish_unlinks (ohci, ohci_frame_no(ohci)); 872 if ((ints & OHCI_INTR_SF) != 0 873 && !ohci->ed_rm_list 874 && !ohci->ed_to_check 875 && HC_IS_RUNNING(hcd->state)) 876 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 877 spin_unlock (&ohci->lock); 878 879 if (HC_IS_RUNNING(hcd->state)) { 880 ohci_writel (ohci, ints, ®s->intrstatus); 881 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 882 // flush those writes 883 (void) ohci_readl (ohci, &ohci->regs->control); 884 } 885 886 return IRQ_HANDLED; 887 } 888 889 /*-------------------------------------------------------------------------*/ 890 891 static void ohci_stop (struct usb_hcd *hcd) 892 { 893 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 894 895 ohci_dump (ohci, 1); 896 897 if (quirk_nec(ohci)) 898 flush_work_sync(&ohci->nec_work); 899 900 ohci_usb_reset (ohci); 901 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 902 free_irq(hcd->irq, hcd); 903 hcd->irq = -1; 904 905 if (quirk_zfmicro(ohci)) 906 del_timer(&ohci->unlink_watchdog); 907 if (quirk_amdiso(ohci)) 908 usb_amd_dev_put(); 909 910 remove_debug_files (ohci); 911 ohci_mem_cleanup (ohci); 912 if (ohci->hcca) { 913 dma_free_coherent (hcd->self.controller, 914 sizeof *ohci->hcca, 915 ohci->hcca, ohci->hcca_dma); 916 ohci->hcca = NULL; 917 ohci->hcca_dma = 0; 918 } 919 } 920 921 /*-------------------------------------------------------------------------*/ 922 923 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 924 925 /* must not be called from interrupt context */ 926 static int ohci_restart (struct ohci_hcd *ohci) 927 { 928 int temp; 929 int i; 930 struct urb_priv *priv; 931 932 spin_lock_irq(&ohci->lock); 933 disable (ohci); 934 935 /* Recycle any "live" eds/tds (and urbs). */ 936 if (!list_empty (&ohci->pending)) 937 ohci_dbg(ohci, "abort schedule...\n"); 938 list_for_each_entry (priv, &ohci->pending, pending) { 939 struct urb *urb = priv->td[0]->urb; 940 struct ed *ed = priv->ed; 941 942 switch (ed->state) { 943 case ED_OPER: 944 ed->state = ED_UNLINK; 945 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 946 ed_deschedule (ohci, ed); 947 948 ed->ed_next = ohci->ed_rm_list; 949 ed->ed_prev = NULL; 950 ohci->ed_rm_list = ed; 951 /* FALLTHROUGH */ 952 case ED_UNLINK: 953 break; 954 default: 955 ohci_dbg(ohci, "bogus ed %p state %d\n", 956 ed, ed->state); 957 } 958 959 if (!urb->unlinked) 960 urb->unlinked = -ESHUTDOWN; 961 } 962 finish_unlinks (ohci, 0); 963 spin_unlock_irq(&ohci->lock); 964 965 /* paranoia, in case that didn't work: */ 966 967 /* empty the interrupt branches */ 968 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 969 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 970 971 /* no EDs to remove */ 972 ohci->ed_rm_list = NULL; 973 974 /* empty control and bulk lists */ 975 ohci->ed_controltail = NULL; 976 ohci->ed_bulktail = NULL; 977 978 if ((temp = ohci_run (ohci)) < 0) { 979 ohci_err (ohci, "can't restart, %d\n", temp); 980 return temp; 981 } 982 ohci_dbg(ohci, "restart complete\n"); 983 return 0; 984 } 985 986 #endif 987 988 /*-------------------------------------------------------------------------*/ 989 990 MODULE_AUTHOR (DRIVER_AUTHOR); 991 MODULE_DESCRIPTION(DRIVER_DESC); 992 MODULE_LICENSE ("GPL"); 993 994 #ifdef CONFIG_PCI 995 #include "ohci-pci.c" 996 #define PCI_DRIVER ohci_pci_driver 997 #endif 998 999 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 1000 #include "ohci-sa1111.c" 1001 #define SA1111_DRIVER ohci_hcd_sa1111_driver 1002 #endif 1003 1004 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1005 #include "ohci-s3c2410.c" 1006 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1007 #endif 1008 1009 #ifdef CONFIG_USB_OHCI_HCD_OMAP1 1010 #include "ohci-omap.c" 1011 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver 1012 #endif 1013 1014 #ifdef CONFIG_USB_OHCI_HCD_OMAP3 1015 #include "ohci-omap3.c" 1016 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver 1017 #endif 1018 1019 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1020 #include "ohci-pxa27x.c" 1021 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1022 #endif 1023 1024 #ifdef CONFIG_ARCH_EP93XX 1025 #include "ohci-ep93xx.c" 1026 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1027 #endif 1028 1029 #ifdef CONFIG_MIPS_ALCHEMY 1030 #include "ohci-au1xxx.c" 1031 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1032 #endif 1033 1034 #ifdef CONFIG_PNX8550 1035 #include "ohci-pnx8550.c" 1036 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1037 #endif 1038 1039 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1040 #include "ohci-ppc-soc.c" 1041 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1042 #endif 1043 1044 #ifdef CONFIG_ARCH_AT91 1045 #include "ohci-at91.c" 1046 #define PLATFORM_DRIVER ohci_hcd_at91_driver 1047 #endif 1048 1049 #ifdef CONFIG_ARCH_PNX4008 1050 #include "ohci-pnx4008.c" 1051 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1052 #endif 1053 1054 #ifdef CONFIG_ARCH_DAVINCI_DA8XX 1055 #include "ohci-da8xx.c" 1056 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver 1057 #endif 1058 1059 #ifdef CONFIG_USB_OHCI_SH 1060 #include "ohci-sh.c" 1061 #define PLATFORM_DRIVER ohci_hcd_sh_driver 1062 #endif 1063 1064 1065 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1066 #include "ohci-ppc-of.c" 1067 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1068 #endif 1069 1070 #ifdef CONFIG_PLAT_SPEAR 1071 #include "ohci-spear.c" 1072 #define PLATFORM_DRIVER spear_ohci_hcd_driver 1073 #endif 1074 1075 #ifdef CONFIG_PPC_PS3 1076 #include "ohci-ps3.c" 1077 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1078 #endif 1079 1080 #ifdef CONFIG_USB_OHCI_HCD_SSB 1081 #include "ohci-ssb.c" 1082 #define SSB_OHCI_DRIVER ssb_ohci_driver 1083 #endif 1084 1085 #ifdef CONFIG_MFD_SM501 1086 #include "ohci-sm501.c" 1087 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1088 #endif 1089 1090 #ifdef CONFIG_MFD_TC6393XB 1091 #include "ohci-tmio.c" 1092 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver 1093 #endif 1094 1095 #ifdef CONFIG_MACH_JZ4740 1096 #include "ohci-jz4740.c" 1097 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver 1098 #endif 1099 1100 #ifdef CONFIG_USB_OCTEON_OHCI 1101 #include "ohci-octeon.c" 1102 #define PLATFORM_DRIVER ohci_octeon_driver 1103 #endif 1104 1105 #ifdef CONFIG_USB_CNS3XXX_OHCI 1106 #include "ohci-cns3xxx.c" 1107 #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver 1108 #endif 1109 1110 #ifdef CONFIG_USB_OHCI_ATH79 1111 #include "ohci-ath79.c" 1112 #define PLATFORM_DRIVER ohci_hcd_ath79_driver 1113 #endif 1114 1115 #if !defined(PCI_DRIVER) && \ 1116 !defined(PLATFORM_DRIVER) && \ 1117 !defined(OMAP1_PLATFORM_DRIVER) && \ 1118 !defined(OMAP3_PLATFORM_DRIVER) && \ 1119 !defined(OF_PLATFORM_DRIVER) && \ 1120 !defined(SA1111_DRIVER) && \ 1121 !defined(PS3_SYSTEM_BUS_DRIVER) && \ 1122 !defined(SM501_OHCI_DRIVER) && \ 1123 !defined(TMIO_OHCI_DRIVER) && \ 1124 !defined(SSB_OHCI_DRIVER) 1125 #error "missing bus glue for ohci-hcd" 1126 #endif 1127 1128 static int __init ohci_hcd_mod_init(void) 1129 { 1130 int retval = 0; 1131 1132 if (usb_disabled()) 1133 return -ENODEV; 1134 1135 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1136 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1137 sizeof (struct ed), sizeof (struct td)); 1138 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1139 1140 #ifdef DEBUG 1141 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); 1142 if (!ohci_debug_root) { 1143 retval = -ENOENT; 1144 goto error_debug; 1145 } 1146 #endif 1147 1148 #ifdef PS3_SYSTEM_BUS_DRIVER 1149 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1150 if (retval < 0) 1151 goto error_ps3; 1152 #endif 1153 1154 #ifdef PLATFORM_DRIVER 1155 retval = platform_driver_register(&PLATFORM_DRIVER); 1156 if (retval < 0) 1157 goto error_platform; 1158 #endif 1159 1160 #ifdef OMAP1_PLATFORM_DRIVER 1161 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); 1162 if (retval < 0) 1163 goto error_omap1_platform; 1164 #endif 1165 1166 #ifdef OMAP3_PLATFORM_DRIVER 1167 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); 1168 if (retval < 0) 1169 goto error_omap3_platform; 1170 #endif 1171 1172 #ifdef OF_PLATFORM_DRIVER 1173 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1174 if (retval < 0) 1175 goto error_of_platform; 1176 #endif 1177 1178 #ifdef SA1111_DRIVER 1179 retval = sa1111_driver_register(&SA1111_DRIVER); 1180 if (retval < 0) 1181 goto error_sa1111; 1182 #endif 1183 1184 #ifdef PCI_DRIVER 1185 retval = pci_register_driver(&PCI_DRIVER); 1186 if (retval < 0) 1187 goto error_pci; 1188 #endif 1189 1190 #ifdef SSB_OHCI_DRIVER 1191 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1192 if (retval) 1193 goto error_ssb; 1194 #endif 1195 1196 #ifdef SM501_OHCI_DRIVER 1197 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1198 if (retval < 0) 1199 goto error_sm501; 1200 #endif 1201 1202 #ifdef TMIO_OHCI_DRIVER 1203 retval = platform_driver_register(&TMIO_OHCI_DRIVER); 1204 if (retval < 0) 1205 goto error_tmio; 1206 #endif 1207 1208 return retval; 1209 1210 /* Error path */ 1211 #ifdef TMIO_OHCI_DRIVER 1212 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1213 error_tmio: 1214 #endif 1215 #ifdef SM501_OHCI_DRIVER 1216 platform_driver_unregister(&SM501_OHCI_DRIVER); 1217 error_sm501: 1218 #endif 1219 #ifdef SSB_OHCI_DRIVER 1220 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1221 error_ssb: 1222 #endif 1223 #ifdef PCI_DRIVER 1224 pci_unregister_driver(&PCI_DRIVER); 1225 error_pci: 1226 #endif 1227 #ifdef SA1111_DRIVER 1228 sa1111_driver_unregister(&SA1111_DRIVER); 1229 error_sa1111: 1230 #endif 1231 #ifdef OF_PLATFORM_DRIVER 1232 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1233 error_of_platform: 1234 #endif 1235 #ifdef PLATFORM_DRIVER 1236 platform_driver_unregister(&PLATFORM_DRIVER); 1237 error_platform: 1238 #endif 1239 #ifdef OMAP1_PLATFORM_DRIVER 1240 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); 1241 error_omap1_platform: 1242 #endif 1243 #ifdef OMAP3_PLATFORM_DRIVER 1244 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); 1245 error_omap3_platform: 1246 #endif 1247 #ifdef PS3_SYSTEM_BUS_DRIVER 1248 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1249 error_ps3: 1250 #endif 1251 #ifdef DEBUG 1252 debugfs_remove(ohci_debug_root); 1253 ohci_debug_root = NULL; 1254 error_debug: 1255 #endif 1256 1257 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1258 return retval; 1259 } 1260 module_init(ohci_hcd_mod_init); 1261 1262 static void __exit ohci_hcd_mod_exit(void) 1263 { 1264 #ifdef TMIO_OHCI_DRIVER 1265 platform_driver_unregister(&TMIO_OHCI_DRIVER); 1266 #endif 1267 #ifdef SM501_OHCI_DRIVER 1268 platform_driver_unregister(&SM501_OHCI_DRIVER); 1269 #endif 1270 #ifdef SSB_OHCI_DRIVER 1271 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1272 #endif 1273 #ifdef PCI_DRIVER 1274 pci_unregister_driver(&PCI_DRIVER); 1275 #endif 1276 #ifdef SA1111_DRIVER 1277 sa1111_driver_unregister(&SA1111_DRIVER); 1278 #endif 1279 #ifdef OF_PLATFORM_DRIVER 1280 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1281 #endif 1282 #ifdef PLATFORM_DRIVER 1283 platform_driver_unregister(&PLATFORM_DRIVER); 1284 #endif 1285 #ifdef OMAP3_PLATFORM_DRIVER 1286 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); 1287 #endif 1288 #ifdef PS3_SYSTEM_BUS_DRIVER 1289 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1290 #endif 1291 #ifdef DEBUG 1292 debugfs_remove(ohci_debug_root); 1293 #endif 1294 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); 1295 } 1296 module_exit(ohci_hcd_mod_exit); 1297 1298