1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* statistics can be kept for for tuning/monitoring */ 25 struct ehci_stats { 26 /* irq usage */ 27 unsigned long normal; 28 unsigned long error; 29 unsigned long reclaim; 30 unsigned long lost_iaa; 31 32 /* termination of urbs from core */ 33 unsigned long complete; 34 unsigned long unlink; 35 }; 36 37 /* ehci_hcd->lock guards shared data against other CPUs: 38 * ehci_hcd: async, reclaim, periodic (and shadow), ... 39 * usb_host_endpoint: hcpriv 40 * ehci_qh: qh_next, qtd_list 41 * ehci_qtd: qtd_list 42 * 43 * Also, hold this lock when talking to HC registers or 44 * when updating hw_* fields in shared qh/qtd/... structures. 45 */ 46 47 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 48 49 struct ehci_hcd { /* one per controller */ 50 /* glue to PCI and HCD framework */ 51 struct ehci_caps __iomem *caps; 52 struct ehci_regs __iomem *regs; 53 struct ehci_dbg_port __iomem *debug; 54 55 __u32 hcs_params; /* cached register copy */ 56 spinlock_t lock; 57 58 /* async schedule support */ 59 struct ehci_qh *async; 60 struct ehci_qh *reclaim; 61 unsigned reclaim_ready : 1; 62 unsigned scanning : 1; 63 64 /* periodic schedule support */ 65 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 66 unsigned periodic_size; 67 __le32 *periodic; /* hw periodic table */ 68 dma_addr_t periodic_dma; 69 unsigned i_thresh; /* uframes HC might cache */ 70 71 union ehci_shadow *pshadow; /* mirror hw periodic table */ 72 int next_uframe; /* scan periodic, start here */ 73 unsigned periodic_sched; /* periodic activity count */ 74 75 /* per root hub port */ 76 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 77 78 /* per-HC memory pools (could be per-bus, but ...) */ 79 struct dma_pool *qh_pool; /* qh per active urb */ 80 struct dma_pool *qtd_pool; /* one or more per qh */ 81 struct dma_pool *itd_pool; /* itd per iso urb */ 82 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 83 84 struct timer_list watchdog; 85 struct notifier_block reboot_notifier; 86 unsigned long actions; 87 unsigned stamp; 88 unsigned long next_statechange; 89 u32 command; 90 91 /* SILICON QUIRKS */ 92 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ 93 unsigned no_selective_suspend:1; 94 unsigned has_fsl_port_bug:1; /* FreeScale */ 95 96 u8 sbrn; /* packed release number */ 97 98 /* irq statistics */ 99 #ifdef EHCI_STATS 100 struct ehci_stats stats; 101 # define COUNT(x) do { (x)++; } while (0) 102 #else 103 # define COUNT(x) do {} while (0) 104 #endif 105 }; 106 107 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 108 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 109 { 110 return (struct ehci_hcd *) (hcd->hcd_priv); 111 } 112 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 113 { 114 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 115 } 116 117 118 enum ehci_timer_action { 119 TIMER_IO_WATCHDOG, 120 TIMER_IAA_WATCHDOG, 121 TIMER_ASYNC_SHRINK, 122 TIMER_ASYNC_OFF, 123 }; 124 125 static inline void 126 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 127 { 128 clear_bit (action, &ehci->actions); 129 } 130 131 static inline void 132 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 133 { 134 if (!test_and_set_bit (action, &ehci->actions)) { 135 unsigned long t; 136 137 switch (action) { 138 case TIMER_IAA_WATCHDOG: 139 t = EHCI_IAA_JIFFIES; 140 break; 141 case TIMER_IO_WATCHDOG: 142 t = EHCI_IO_JIFFIES; 143 break; 144 case TIMER_ASYNC_OFF: 145 t = EHCI_ASYNC_JIFFIES; 146 break; 147 // case TIMER_ASYNC_SHRINK: 148 default: 149 t = EHCI_SHRINK_JIFFIES; 150 break; 151 } 152 t += jiffies; 153 // all timings except IAA watchdog can be overridden. 154 // async queue SHRINK often precedes IAA. while it's ready 155 // to go OFF neither can matter, and afterwards the IO 156 // watchdog stops unless there's still periodic traffic. 157 if (action != TIMER_IAA_WATCHDOG 158 && t > ehci->watchdog.expires 159 && timer_pending (&ehci->watchdog)) 160 return; 161 mod_timer (&ehci->watchdog, t); 162 } 163 } 164 165 /*-------------------------------------------------------------------------*/ 166 167 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 168 169 /* Section 2.2 Host Controller Capability Registers */ 170 struct ehci_caps { 171 /* these fields are specified as 8 and 16 bit registers, 172 * but some hosts can't perform 8 or 16 bit PCI accesses. 173 */ 174 u32 hc_capbase; 175 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 176 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 177 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 178 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 179 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 180 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 181 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 182 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 183 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 184 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 185 186 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 187 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 188 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 189 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 190 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 191 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 192 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 193 u8 portroute [8]; /* nibbles for routing - offset 0xC */ 194 } __attribute__ ((packed)); 195 196 197 /* Section 2.3 Host Controller Operational Registers */ 198 struct ehci_regs { 199 200 /* USBCMD: offset 0x00 */ 201 u32 command; 202 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 203 #define CMD_PARK (1<<11) /* enable "park" on async qh */ 204 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 205 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 206 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 207 #define CMD_ASE (1<<5) /* async schedule enable */ 208 #define CMD_PSE (1<<4) /* periodic schedule enable */ 209 /* 3:2 is periodic frame list size */ 210 #define CMD_RESET (1<<1) /* reset HC not bus */ 211 #define CMD_RUN (1<<0) /* start/stop HC */ 212 213 /* USBSTS: offset 0x04 */ 214 u32 status; 215 #define STS_ASS (1<<15) /* Async Schedule Status */ 216 #define STS_PSS (1<<14) /* Periodic Schedule Status */ 217 #define STS_RECL (1<<13) /* Reclamation */ 218 #define STS_HALT (1<<12) /* Not running (any reason) */ 219 /* some bits reserved */ 220 /* these STS_* flags are also intr_enable bits (USBINTR) */ 221 #define STS_IAA (1<<5) /* Interrupted on async advance */ 222 #define STS_FATAL (1<<4) /* such as some PCI access errors */ 223 #define STS_FLR (1<<3) /* frame list rolled over */ 224 #define STS_PCD (1<<2) /* port change detect */ 225 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 226 #define STS_INT (1<<0) /* "normal" completion (short, ...) */ 227 228 /* USBINTR: offset 0x08 */ 229 u32 intr_enable; 230 231 /* FRINDEX: offset 0x0C */ 232 u32 frame_index; /* current microframe number */ 233 /* CTRLDSSEGMENT: offset 0x10 */ 234 u32 segment; /* address bits 63:32 if needed */ 235 /* PERIODICLISTBASE: offset 0x14 */ 236 u32 frame_list; /* points to periodic list */ 237 /* ASYNCLISTADDR: offset 0x18 */ 238 u32 async_next; /* address of next async queue head */ 239 240 u32 reserved [9]; 241 242 /* CONFIGFLAG: offset 0x40 */ 243 u32 configured_flag; 244 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 245 246 /* PORTSC: offset 0x44 */ 247 u32 port_status [0]; /* up to N_PORTS */ 248 /* 31:23 reserved */ 249 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 250 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 251 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 252 /* 19:16 for port testing */ 253 #define PORT_LED_OFF (0<<14) 254 #define PORT_LED_AMBER (1<<14) 255 #define PORT_LED_GREEN (2<<14) 256 #define PORT_LED_MASK (3<<14) 257 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 258 #define PORT_POWER (1<<12) /* true: has power (see PPC) */ 259 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ 260 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 261 /* 9 reserved */ 262 #define PORT_RESET (1<<8) /* reset port */ 263 #define PORT_SUSPEND (1<<7) /* suspend port */ 264 #define PORT_RESUME (1<<6) /* resume it */ 265 #define PORT_OCC (1<<5) /* over current change */ 266 #define PORT_OC (1<<4) /* over current active */ 267 #define PORT_PEC (1<<3) /* port enable change */ 268 #define PORT_PE (1<<2) /* port enable */ 269 #define PORT_CSC (1<<1) /* connect status change */ 270 #define PORT_CONNECT (1<<0) /* device connected */ 271 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 272 } __attribute__ ((packed)); 273 274 /* Appendix C, Debug port ... intended for use with special "debug devices" 275 * that can help if there's no serial console. (nonstandard enumeration.) 276 */ 277 struct ehci_dbg_port { 278 u32 control; 279 #define DBGP_OWNER (1<<30) 280 #define DBGP_ENABLED (1<<28) 281 #define DBGP_DONE (1<<16) 282 #define DBGP_INUSE (1<<10) 283 #define DBGP_ERRCODE(x) (((x)>>7)&0x07) 284 # define DBGP_ERR_BAD 1 285 # define DBGP_ERR_SIGNAL 2 286 #define DBGP_ERROR (1<<6) 287 #define DBGP_GO (1<<5) 288 #define DBGP_OUT (1<<4) 289 #define DBGP_LEN(x) (((x)>>0)&0x0f) 290 u32 pids; 291 #define DBGP_PID_GET(x) (((x)>>16)&0xff) 292 #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) 293 u32 data03; 294 u32 data47; 295 u32 address; 296 #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) 297 } __attribute__ ((packed)); 298 299 /*-------------------------------------------------------------------------*/ 300 301 #define QTD_NEXT(dma) cpu_to_le32((u32)dma) 302 303 /* 304 * EHCI Specification 0.95 Section 3.5 305 * QTD: describe data transfer components (buffer, direction, ...) 306 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 307 * 308 * These are associated only with "QH" (Queue Head) structures, 309 * used with control, bulk, and interrupt transfers. 310 */ 311 struct ehci_qtd { 312 /* first part defined by EHCI spec */ 313 __le32 hw_next; /* see EHCI 3.5.1 */ 314 __le32 hw_alt_next; /* see EHCI 3.5.2 */ 315 __le32 hw_token; /* see EHCI 3.5.3 */ 316 #define QTD_TOGGLE (1 << 31) /* data toggle */ 317 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 318 #define QTD_IOC (1 << 15) /* interrupt on complete */ 319 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 320 #define QTD_PID(tok) (((tok)>>8) & 0x3) 321 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 322 #define QTD_STS_HALT (1 << 6) /* halted on error */ 323 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 324 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 325 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 326 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 327 #define QTD_STS_STS (1 << 1) /* split transaction state */ 328 #define QTD_STS_PING (1 << 0) /* issue PING? */ 329 __le32 hw_buf [5]; /* see EHCI 3.5.4 */ 330 __le32 hw_buf_hi [5]; /* Appendix B */ 331 332 /* the rest is HCD-private */ 333 dma_addr_t qtd_dma; /* qtd address */ 334 struct list_head qtd_list; /* sw qtd list */ 335 struct urb *urb; /* qtd's urb */ 336 size_t length; /* length of buffer */ 337 } __attribute__ ((aligned (32))); 338 339 /* mask NakCnt+T in qh->hw_alt_next */ 340 #define QTD_MASK __constant_cpu_to_le32 (~0x1f) 341 342 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 343 344 /*-------------------------------------------------------------------------*/ 345 346 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 347 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1)) 348 349 /* values for that type tag */ 350 #define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1) 351 #define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1) 352 #define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1) 353 #define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1) 354 355 /* next async queue entry, or pointer to interrupt/periodic QH */ 356 #define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) 357 358 /* for periodic/async schedules and qtd lists, mark end of list */ 359 #define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */ 360 361 /* 362 * Entries in periodic shadow table are pointers to one of four kinds 363 * of data structure. That's dictated by the hardware; a type tag is 364 * encoded in the low bits of the hardware's periodic schedule. Use 365 * Q_NEXT_TYPE to get the tag. 366 * 367 * For entries in the async schedule, the type tag always says "qh". 368 */ 369 union ehci_shadow { 370 struct ehci_qh *qh; /* Q_TYPE_QH */ 371 struct ehci_itd *itd; /* Q_TYPE_ITD */ 372 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 373 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 374 __le32 *hw_next; /* (all types) */ 375 void *ptr; 376 }; 377 378 /*-------------------------------------------------------------------------*/ 379 380 /* 381 * EHCI Specification 0.95 Section 3.6 382 * QH: describes control/bulk/interrupt endpoints 383 * See Fig 3-7 "Queue Head Structure Layout". 384 * 385 * These appear in both the async and (for interrupt) periodic schedules. 386 */ 387 388 struct ehci_qh { 389 /* first part defined by EHCI spec */ 390 __le32 hw_next; /* see EHCI 3.6.1 */ 391 __le32 hw_info1; /* see EHCI 3.6.2 */ 392 #define QH_HEAD 0x00008000 393 __le32 hw_info2; /* see EHCI 3.6.2 */ 394 #define QH_SMASK 0x000000ff 395 #define QH_CMASK 0x0000ff00 396 #define QH_HUBADDR 0x007f0000 397 #define QH_HUBPORT 0x3f800000 398 #define QH_MULT 0xc0000000 399 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ 400 401 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 402 __le32 hw_qtd_next; 403 __le32 hw_alt_next; 404 __le32 hw_token; 405 __le32 hw_buf [5]; 406 __le32 hw_buf_hi [5]; 407 408 /* the rest is HCD-private */ 409 dma_addr_t qh_dma; /* address of qh */ 410 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 411 struct list_head qtd_list; /* sw qtd list */ 412 struct ehci_qtd *dummy; 413 struct ehci_qh *reclaim; /* next to reclaim */ 414 415 struct ehci_hcd *ehci; 416 struct kref kref; 417 unsigned stamp; 418 419 u8 qh_state; 420 #define QH_STATE_LINKED 1 /* HC sees this */ 421 #define QH_STATE_UNLINK 2 /* HC may still see this */ 422 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 423 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 424 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 425 426 /* periodic schedule info */ 427 u8 usecs; /* intr bandwidth */ 428 u8 gap_uf; /* uframes split/csplit gap */ 429 u8 c_usecs; /* ... split completion bw */ 430 u16 tt_usecs; /* tt downstream bandwidth */ 431 unsigned short period; /* polling interval */ 432 unsigned short start; /* where polling starts */ 433 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 434 struct usb_device *dev; /* access to TT */ 435 } __attribute__ ((aligned (32))); 436 437 /*-------------------------------------------------------------------------*/ 438 439 /* description of one iso transaction (up to 3 KB data if highspeed) */ 440 struct ehci_iso_packet { 441 /* These will be copied to iTD when scheduling */ 442 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 443 __le32 transaction; /* itd->hw_transaction[i] |= */ 444 u8 cross; /* buf crosses pages */ 445 /* for full speed OUT splits */ 446 u32 buf1; 447 }; 448 449 /* temporary schedule data for packets from iso urbs (both speeds) 450 * each packet is one logical usb transaction to the device (not TT), 451 * beginning at stream->next_uframe 452 */ 453 struct ehci_iso_sched { 454 struct list_head td_list; 455 unsigned span; 456 struct ehci_iso_packet packet [0]; 457 }; 458 459 /* 460 * ehci_iso_stream - groups all (s)itds for this endpoint. 461 * acts like a qh would, if EHCI had them for ISO. 462 */ 463 struct ehci_iso_stream { 464 /* first two fields match QH, but info1 == 0 */ 465 __le32 hw_next; 466 __le32 hw_info1; 467 468 u32 refcount; 469 u8 bEndpointAddress; 470 u8 highspeed; 471 u16 depth; /* depth in uframes */ 472 struct list_head td_list; /* queued itds/sitds */ 473 struct list_head free_list; /* list of unused itds/sitds */ 474 struct usb_device *udev; 475 struct usb_host_endpoint *ep; 476 477 /* output of (re)scheduling */ 478 unsigned long start; /* jiffies */ 479 unsigned long rescheduled; 480 int next_uframe; 481 __le32 splits; 482 483 /* the rest is derived from the endpoint descriptor, 484 * trusting urb->interval == f(epdesc->bInterval) and 485 * including the extra info for hw_bufp[0..2] 486 */ 487 u8 interval; 488 u8 usecs, c_usecs; 489 u16 tt_usecs; 490 u16 maxp; 491 u16 raw_mask; 492 unsigned bandwidth; 493 494 /* This is used to initialize iTD's hw_bufp fields */ 495 __le32 buf0; 496 __le32 buf1; 497 __le32 buf2; 498 499 /* this is used to initialize sITD's tt info */ 500 __le32 address; 501 }; 502 503 /*-------------------------------------------------------------------------*/ 504 505 /* 506 * EHCI Specification 0.95 Section 3.3 507 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 508 * 509 * Schedule records for high speed iso xfers 510 */ 511 struct ehci_itd { 512 /* first part defined by EHCI spec */ 513 __le32 hw_next; /* see EHCI 3.3.1 */ 514 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */ 515 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 516 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 517 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 518 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 519 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 520 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 521 522 #define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE) 523 524 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */ 525 __le32 hw_bufp_hi [7]; /* Appendix B */ 526 527 /* the rest is HCD-private */ 528 dma_addr_t itd_dma; /* for this itd */ 529 union ehci_shadow itd_next; /* ptr to periodic q entry */ 530 531 struct urb *urb; 532 struct ehci_iso_stream *stream; /* endpoint's queue */ 533 struct list_head itd_list; /* list of stream's itds */ 534 535 /* any/all hw_transactions here may be used by that urb */ 536 unsigned frame; /* where scheduled */ 537 unsigned pg; 538 unsigned index[8]; /* in urb->iso_frame_desc */ 539 u8 usecs[8]; 540 } __attribute__ ((aligned (32))); 541 542 /*-------------------------------------------------------------------------*/ 543 544 /* 545 * EHCI Specification 0.95 Section 3.4 546 * siTD, aka split-transaction isochronous Transfer Descriptor 547 * ... describe full speed iso xfers through TT in hubs 548 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 549 */ 550 struct ehci_sitd { 551 /* first part defined by EHCI spec */ 552 __le32 hw_next; 553 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 554 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */ 555 __le32 hw_uframe; /* EHCI table 3-10 */ 556 __le32 hw_results; /* EHCI table 3-11 */ 557 #define SITD_IOC (1 << 31) /* interrupt on completion */ 558 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 559 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 560 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 561 #define SITD_STS_ERR (1 << 6) /* error from TT */ 562 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 563 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 564 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 565 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 566 #define SITD_STS_STS (1 << 1) /* split transaction state */ 567 568 #define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE) 569 570 __le32 hw_buf [2]; /* EHCI table 3-12 */ 571 __le32 hw_backpointer; /* EHCI table 3-13 */ 572 __le32 hw_buf_hi [2]; /* Appendix B */ 573 574 /* the rest is HCD-private */ 575 dma_addr_t sitd_dma; 576 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 577 578 struct urb *urb; 579 struct ehci_iso_stream *stream; /* endpoint's queue */ 580 struct list_head sitd_list; /* list of stream's sitds */ 581 unsigned frame; 582 unsigned index; 583 } __attribute__ ((aligned (32))); 584 585 /*-------------------------------------------------------------------------*/ 586 587 /* 588 * EHCI Specification 0.96 Section 3.7 589 * Periodic Frame Span Traversal Node (FSTN) 590 * 591 * Manages split interrupt transactions (using TT) that span frame boundaries 592 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 593 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 594 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 595 */ 596 struct ehci_fstn { 597 __le32 hw_next; /* any periodic q entry */ 598 __le32 hw_prev; /* qh or EHCI_LIST_END */ 599 600 /* the rest is HCD-private */ 601 dma_addr_t fstn_dma; 602 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 603 } __attribute__ ((aligned (32))); 604 605 /*-------------------------------------------------------------------------*/ 606 607 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 608 609 /* 610 * Some EHCI controllers have a Transaction Translator built into the 611 * root hub. This is a non-standard feature. Each controller will need 612 * to add code to the following inline functions, and call them as 613 * needed (mostly in root hub code). 614 */ 615 616 #define ehci_is_TDI(e) ((e)->is_tdi_rh_tt) 617 618 /* Returns the speed of a device attached to a port on the root hub. */ 619 static inline unsigned int 620 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 621 { 622 if (ehci_is_TDI(ehci)) { 623 switch ((portsc>>26)&3) { 624 case 0: 625 return 0; 626 case 1: 627 return (1<<USB_PORT_FEAT_LOWSPEED); 628 case 2: 629 default: 630 return (1<<USB_PORT_FEAT_HIGHSPEED); 631 } 632 } 633 return (1<<USB_PORT_FEAT_HIGHSPEED); 634 } 635 636 #else 637 638 #define ehci_is_TDI(e) (0) 639 640 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 641 #endif 642 643 /*-------------------------------------------------------------------------*/ 644 645 #ifdef CONFIG_PPC_83xx 646 /* Some Freescale processors have an erratum in which the TT 647 * port number in the queue head was 0..N-1 instead of 1..N. 648 */ 649 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 650 #else 651 #define ehci_has_fsl_portno_bug(e) (0) 652 #endif 653 654 655 /*-------------------------------------------------------------------------*/ 656 657 #ifndef DEBUG 658 #define STUB_DEBUG_FILES 659 #endif /* DEBUG */ 660 661 /*-------------------------------------------------------------------------*/ 662 663 #endif /* __LINUX_EHCI_HCD_H */ 664