1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 enum ehci_rh_state { 66 EHCI_RH_HALTED, 67 EHCI_RH_SUSPENDED, 68 EHCI_RH_RUNNING 69 }; 70 71 struct ehci_hcd { /* one per controller */ 72 /* glue to PCI and HCD framework */ 73 struct ehci_caps __iomem *caps; 74 struct ehci_regs __iomem *regs; 75 struct ehci_dbg_port __iomem *debug; 76 77 __u32 hcs_params; /* cached register copy */ 78 spinlock_t lock; 79 enum ehci_rh_state rh_state; 80 81 /* async schedule support */ 82 struct ehci_qh *async; 83 struct ehci_qh *dummy; /* For AMD quirk use */ 84 struct ehci_qh *reclaim; 85 struct ehci_qh *qh_scan_next; 86 unsigned scanning : 1; 87 88 /* periodic schedule support */ 89 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 90 unsigned periodic_size; 91 __hc32 *periodic; /* hw periodic table */ 92 dma_addr_t periodic_dma; 93 unsigned i_thresh; /* uframes HC might cache */ 94 95 union ehci_shadow *pshadow; /* mirror hw periodic table */ 96 int next_uframe; /* scan periodic, start here */ 97 unsigned periodic_sched; /* periodic activity count */ 98 unsigned uframe_periodic_max; /* max periodic time per uframe */ 99 100 101 /* list of itds & sitds completed while clock_frame was still active */ 102 struct list_head cached_itd_list; 103 struct list_head cached_sitd_list; 104 unsigned clock_frame; 105 106 /* per root hub port */ 107 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 108 109 /* bit vectors (one bit per port) */ 110 unsigned long bus_suspended; /* which ports were 111 already suspended at the start of a bus suspend */ 112 unsigned long companion_ports; /* which ports are 113 dedicated to the companion controller */ 114 unsigned long owned_ports; /* which ports are 115 owned by the companion during a bus suspend */ 116 unsigned long port_c_suspend; /* which ports have 117 the change-suspend feature turned on */ 118 unsigned long suspended_ports; /* which ports are 119 suspended */ 120 121 /* per-HC memory pools (could be per-bus, but ...) */ 122 struct dma_pool *qh_pool; /* qh per active urb */ 123 struct dma_pool *qtd_pool; /* one or more per qh */ 124 struct dma_pool *itd_pool; /* itd per iso urb */ 125 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 126 127 struct timer_list iaa_watchdog; 128 struct timer_list watchdog; 129 unsigned long actions; 130 unsigned periodic_stamp; 131 unsigned random_frame; 132 unsigned long next_statechange; 133 ktime_t last_periodic_enable; 134 u32 command; 135 136 /* SILICON QUIRKS */ 137 unsigned no_selective_suspend:1; 138 unsigned has_fsl_port_bug:1; /* FreeScale */ 139 unsigned big_endian_mmio:1; 140 unsigned big_endian_desc:1; 141 unsigned big_endian_capbase:1; 142 unsigned has_amcc_usb23:1; 143 unsigned need_io_watchdog:1; 144 unsigned broken_periodic:1; 145 unsigned amd_pll_fix:1; 146 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 147 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 148 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 149 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 150 151 /* required for usb32 quirk */ 152 #define OHCI_CTRL_HCFS (3 << 6) 153 #define OHCI_USB_OPER (2 << 6) 154 #define OHCI_USB_SUSPEND (3 << 6) 155 156 #define OHCI_HCCTRL_OFFSET 0x4 157 #define OHCI_HCCTRL_LEN 0x4 158 __hc32 *ohci_hcctrl_reg; 159 unsigned has_hostpc:1; 160 unsigned has_lpm:1; /* support link power management */ 161 unsigned has_ppcd:1; /* support per-port change bits */ 162 u8 sbrn; /* packed release number */ 163 164 /* irq statistics */ 165 #ifdef EHCI_STATS 166 struct ehci_stats stats; 167 # define COUNT(x) do { (x)++; } while (0) 168 #else 169 # define COUNT(x) do {} while (0) 170 #endif 171 172 /* debug files */ 173 #ifdef DEBUG 174 struct dentry *debug_dir; 175 #endif 176 /* 177 * OTG controllers and transceivers need software interaction 178 */ 179 struct otg_transceiver *transceiver; 180 }; 181 182 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 183 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 184 { 185 return (struct ehci_hcd *) (hcd->hcd_priv); 186 } 187 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 188 { 189 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 190 } 191 192 193 static inline void 194 iaa_watchdog_start(struct ehci_hcd *ehci) 195 { 196 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 197 mod_timer(&ehci->iaa_watchdog, 198 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 199 } 200 201 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 202 { 203 del_timer(&ehci->iaa_watchdog); 204 } 205 206 enum ehci_timer_action { 207 TIMER_IO_WATCHDOG, 208 TIMER_ASYNC_SHRINK, 209 TIMER_ASYNC_OFF, 210 }; 211 212 static inline void 213 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 214 { 215 clear_bit (action, &ehci->actions); 216 } 217 218 static void free_cached_lists(struct ehci_hcd *ehci); 219 220 /*-------------------------------------------------------------------------*/ 221 222 #include <linux/usb/ehci_def.h> 223 224 /*-------------------------------------------------------------------------*/ 225 226 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 227 228 /* 229 * EHCI Specification 0.95 Section 3.5 230 * QTD: describe data transfer components (buffer, direction, ...) 231 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 232 * 233 * These are associated only with "QH" (Queue Head) structures, 234 * used with control, bulk, and interrupt transfers. 235 */ 236 struct ehci_qtd { 237 /* first part defined by EHCI spec */ 238 __hc32 hw_next; /* see EHCI 3.5.1 */ 239 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 240 __hc32 hw_token; /* see EHCI 3.5.3 */ 241 #define QTD_TOGGLE (1 << 31) /* data toggle */ 242 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 243 #define QTD_IOC (1 << 15) /* interrupt on complete */ 244 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 245 #define QTD_PID(tok) (((tok)>>8) & 0x3) 246 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 247 #define QTD_STS_HALT (1 << 6) /* halted on error */ 248 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 249 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 250 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 251 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 252 #define QTD_STS_STS (1 << 1) /* split transaction state */ 253 #define QTD_STS_PING (1 << 0) /* issue PING? */ 254 255 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 256 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 257 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 258 259 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 260 __hc32 hw_buf_hi [5]; /* Appendix B */ 261 262 /* the rest is HCD-private */ 263 dma_addr_t qtd_dma; /* qtd address */ 264 struct list_head qtd_list; /* sw qtd list */ 265 struct urb *urb; /* qtd's urb */ 266 size_t length; /* length of buffer */ 267 } __attribute__ ((aligned (32))); 268 269 /* mask NakCnt+T in qh->hw_alt_next */ 270 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 271 272 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 273 274 /*-------------------------------------------------------------------------*/ 275 276 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 277 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 278 279 /* 280 * Now the following defines are not converted using the 281 * cpu_to_le32() macro anymore, since we have to support 282 * "dynamic" switching between be and le support, so that the driver 283 * can be used on one system with SoC EHCI controller using big-endian 284 * descriptors as well as a normal little-endian PCI EHCI controller. 285 */ 286 /* values for that type tag */ 287 #define Q_TYPE_ITD (0 << 1) 288 #define Q_TYPE_QH (1 << 1) 289 #define Q_TYPE_SITD (2 << 1) 290 #define Q_TYPE_FSTN (3 << 1) 291 292 /* next async queue entry, or pointer to interrupt/periodic QH */ 293 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 294 295 /* for periodic/async schedules and qtd lists, mark end of list */ 296 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 297 298 /* 299 * Entries in periodic shadow table are pointers to one of four kinds 300 * of data structure. That's dictated by the hardware; a type tag is 301 * encoded in the low bits of the hardware's periodic schedule. Use 302 * Q_NEXT_TYPE to get the tag. 303 * 304 * For entries in the async schedule, the type tag always says "qh". 305 */ 306 union ehci_shadow { 307 struct ehci_qh *qh; /* Q_TYPE_QH */ 308 struct ehci_itd *itd; /* Q_TYPE_ITD */ 309 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 310 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 311 __hc32 *hw_next; /* (all types) */ 312 void *ptr; 313 }; 314 315 /*-------------------------------------------------------------------------*/ 316 317 /* 318 * EHCI Specification 0.95 Section 3.6 319 * QH: describes control/bulk/interrupt endpoints 320 * See Fig 3-7 "Queue Head Structure Layout". 321 * 322 * These appear in both the async and (for interrupt) periodic schedules. 323 */ 324 325 /* first part defined by EHCI spec */ 326 struct ehci_qh_hw { 327 __hc32 hw_next; /* see EHCI 3.6.1 */ 328 __hc32 hw_info1; /* see EHCI 3.6.2 */ 329 #define QH_HEAD 0x00008000 330 __hc32 hw_info2; /* see EHCI 3.6.2 */ 331 #define QH_SMASK 0x000000ff 332 #define QH_CMASK 0x0000ff00 333 #define QH_HUBADDR 0x007f0000 334 #define QH_HUBPORT 0x3f800000 335 #define QH_MULT 0xc0000000 336 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 337 338 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 339 __hc32 hw_qtd_next; 340 __hc32 hw_alt_next; 341 __hc32 hw_token; 342 __hc32 hw_buf [5]; 343 __hc32 hw_buf_hi [5]; 344 } __attribute__ ((aligned(32))); 345 346 struct ehci_qh { 347 struct ehci_qh_hw *hw; 348 /* the rest is HCD-private */ 349 dma_addr_t qh_dma; /* address of qh */ 350 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 351 struct list_head qtd_list; /* sw qtd list */ 352 struct ehci_qtd *dummy; 353 struct ehci_qh *reclaim; /* next to reclaim */ 354 355 struct ehci_hcd *ehci; 356 unsigned long unlink_time; 357 358 /* 359 * Do NOT use atomic operations for QH refcounting. On some CPUs 360 * (PPC7448 for example), atomic operations cannot be performed on 361 * memory that is cache-inhibited (i.e. being used for DMA). 362 * Spinlocks are used to protect all QH fields. 363 */ 364 u32 refcount; 365 unsigned stamp; 366 367 u8 needs_rescan; /* Dequeue during giveback */ 368 u8 qh_state; 369 #define QH_STATE_LINKED 1 /* HC sees this */ 370 #define QH_STATE_UNLINK 2 /* HC may still see this */ 371 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 372 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 373 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 374 375 u8 xacterrs; /* XactErr retry counter */ 376 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 377 378 /* periodic schedule info */ 379 u8 usecs; /* intr bandwidth */ 380 u8 gap_uf; /* uframes split/csplit gap */ 381 u8 c_usecs; /* ... split completion bw */ 382 u16 tt_usecs; /* tt downstream bandwidth */ 383 unsigned short period; /* polling interval */ 384 unsigned short start; /* where polling starts */ 385 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 386 387 struct usb_device *dev; /* access to TT */ 388 unsigned is_out:1; /* bulk or intr OUT */ 389 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 390 }; 391 392 /*-------------------------------------------------------------------------*/ 393 394 /* description of one iso transaction (up to 3 KB data if highspeed) */ 395 struct ehci_iso_packet { 396 /* These will be copied to iTD when scheduling */ 397 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 398 __hc32 transaction; /* itd->hw_transaction[i] |= */ 399 u8 cross; /* buf crosses pages */ 400 /* for full speed OUT splits */ 401 u32 buf1; 402 }; 403 404 /* temporary schedule data for packets from iso urbs (both speeds) 405 * each packet is one logical usb transaction to the device (not TT), 406 * beginning at stream->next_uframe 407 */ 408 struct ehci_iso_sched { 409 struct list_head td_list; 410 unsigned span; 411 struct ehci_iso_packet packet [0]; 412 }; 413 414 /* 415 * ehci_iso_stream - groups all (s)itds for this endpoint. 416 * acts like a qh would, if EHCI had them for ISO. 417 */ 418 struct ehci_iso_stream { 419 /* first field matches ehci_hq, but is NULL */ 420 struct ehci_qh_hw *hw; 421 422 u32 refcount; 423 u8 bEndpointAddress; 424 u8 highspeed; 425 struct list_head td_list; /* queued itds/sitds */ 426 struct list_head free_list; /* list of unused itds/sitds */ 427 struct usb_device *udev; 428 struct usb_host_endpoint *ep; 429 430 /* output of (re)scheduling */ 431 int next_uframe; 432 __hc32 splits; 433 434 /* the rest is derived from the endpoint descriptor, 435 * trusting urb->interval == f(epdesc->bInterval) and 436 * including the extra info for hw_bufp[0..2] 437 */ 438 u8 usecs, c_usecs; 439 u16 interval; 440 u16 tt_usecs; 441 u16 maxp; 442 u16 raw_mask; 443 unsigned bandwidth; 444 445 /* This is used to initialize iTD's hw_bufp fields */ 446 __hc32 buf0; 447 __hc32 buf1; 448 __hc32 buf2; 449 450 /* this is used to initialize sITD's tt info */ 451 __hc32 address; 452 }; 453 454 /*-------------------------------------------------------------------------*/ 455 456 /* 457 * EHCI Specification 0.95 Section 3.3 458 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 459 * 460 * Schedule records for high speed iso xfers 461 */ 462 struct ehci_itd { 463 /* first part defined by EHCI spec */ 464 __hc32 hw_next; /* see EHCI 3.3.1 */ 465 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 466 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 467 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 468 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 469 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 470 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 471 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 472 473 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 474 475 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 476 __hc32 hw_bufp_hi [7]; /* Appendix B */ 477 478 /* the rest is HCD-private */ 479 dma_addr_t itd_dma; /* for this itd */ 480 union ehci_shadow itd_next; /* ptr to periodic q entry */ 481 482 struct urb *urb; 483 struct ehci_iso_stream *stream; /* endpoint's queue */ 484 struct list_head itd_list; /* list of stream's itds */ 485 486 /* any/all hw_transactions here may be used by that urb */ 487 unsigned frame; /* where scheduled */ 488 unsigned pg; 489 unsigned index[8]; /* in urb->iso_frame_desc */ 490 } __attribute__ ((aligned (32))); 491 492 /*-------------------------------------------------------------------------*/ 493 494 /* 495 * EHCI Specification 0.95 Section 3.4 496 * siTD, aka split-transaction isochronous Transfer Descriptor 497 * ... describe full speed iso xfers through TT in hubs 498 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 499 */ 500 struct ehci_sitd { 501 /* first part defined by EHCI spec */ 502 __hc32 hw_next; 503 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 504 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 505 __hc32 hw_uframe; /* EHCI table 3-10 */ 506 __hc32 hw_results; /* EHCI table 3-11 */ 507 #define SITD_IOC (1 << 31) /* interrupt on completion */ 508 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 509 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 510 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 511 #define SITD_STS_ERR (1 << 6) /* error from TT */ 512 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 513 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 514 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 515 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 516 #define SITD_STS_STS (1 << 1) /* split transaction state */ 517 518 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 519 520 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 521 __hc32 hw_backpointer; /* EHCI table 3-13 */ 522 __hc32 hw_buf_hi [2]; /* Appendix B */ 523 524 /* the rest is HCD-private */ 525 dma_addr_t sitd_dma; 526 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 527 528 struct urb *urb; 529 struct ehci_iso_stream *stream; /* endpoint's queue */ 530 struct list_head sitd_list; /* list of stream's sitds */ 531 unsigned frame; 532 unsigned index; 533 } __attribute__ ((aligned (32))); 534 535 /*-------------------------------------------------------------------------*/ 536 537 /* 538 * EHCI Specification 0.96 Section 3.7 539 * Periodic Frame Span Traversal Node (FSTN) 540 * 541 * Manages split interrupt transactions (using TT) that span frame boundaries 542 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 543 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 544 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 545 */ 546 struct ehci_fstn { 547 __hc32 hw_next; /* any periodic q entry */ 548 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 549 550 /* the rest is HCD-private */ 551 dma_addr_t fstn_dma; 552 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 553 } __attribute__ ((aligned (32))); 554 555 /*-------------------------------------------------------------------------*/ 556 557 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 558 559 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 560 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 561 562 #define ehci_prepare_ports_for_controller_resume(ehci) \ 563 ehci_adjust_port_wakeup_flags(ehci, false, false); 564 565 /*-------------------------------------------------------------------------*/ 566 567 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 568 569 /* 570 * Some EHCI controllers have a Transaction Translator built into the 571 * root hub. This is a non-standard feature. Each controller will need 572 * to add code to the following inline functions, and call them as 573 * needed (mostly in root hub code). 574 */ 575 576 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 577 578 /* Returns the speed of a device attached to a port on the root hub. */ 579 static inline unsigned int 580 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 581 { 582 if (ehci_is_TDI(ehci)) { 583 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 584 case 0: 585 return 0; 586 case 1: 587 return USB_PORT_STAT_LOW_SPEED; 588 case 2: 589 default: 590 return USB_PORT_STAT_HIGH_SPEED; 591 } 592 } 593 return USB_PORT_STAT_HIGH_SPEED; 594 } 595 596 #else 597 598 #define ehci_is_TDI(e) (0) 599 600 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 601 #endif 602 603 /*-------------------------------------------------------------------------*/ 604 605 #ifdef CONFIG_PPC_83xx 606 /* Some Freescale processors have an erratum in which the TT 607 * port number in the queue head was 0..N-1 instead of 1..N. 608 */ 609 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 610 #else 611 #define ehci_has_fsl_portno_bug(e) (0) 612 #endif 613 614 /* 615 * While most USB host controllers implement their registers in 616 * little-endian format, a minority (celleb companion chip) implement 617 * them in big endian format. 618 * 619 * This attempts to support either format at compile time without a 620 * runtime penalty, or both formats with the additional overhead 621 * of checking a flag bit. 622 * 623 * ehci_big_endian_capbase is a special quirk for controllers that 624 * implement the HC capability registers as separate registers and not 625 * as fields of a 32-bit register. 626 */ 627 628 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 629 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 630 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 631 #else 632 #define ehci_big_endian_mmio(e) 0 633 #define ehci_big_endian_capbase(e) 0 634 #endif 635 636 /* 637 * Big-endian read/write functions are arch-specific. 638 * Other arches can be added if/when they're needed. 639 */ 640 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 641 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 642 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 643 #endif 644 645 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 646 __u32 __iomem * regs) 647 { 648 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 649 return ehci_big_endian_mmio(ehci) ? 650 readl_be(regs) : 651 readl(regs); 652 #else 653 return readl(regs); 654 #endif 655 } 656 657 static inline void ehci_writel(const struct ehci_hcd *ehci, 658 const unsigned int val, __u32 __iomem *regs) 659 { 660 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 661 ehci_big_endian_mmio(ehci) ? 662 writel_be(val, regs) : 663 writel(val, regs); 664 #else 665 writel(val, regs); 666 #endif 667 } 668 669 /* 670 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 671 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 672 * Other common bits are dependent on has_amcc_usb23 quirk flag. 673 */ 674 #ifdef CONFIG_44x 675 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 676 { 677 u32 hc_control; 678 679 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 680 if (operational) 681 hc_control |= OHCI_USB_OPER; 682 else 683 hc_control |= OHCI_USB_SUSPEND; 684 685 writel_be(hc_control, ehci->ohci_hcctrl_reg); 686 (void) readl_be(ehci->ohci_hcctrl_reg); 687 } 688 #else 689 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 690 { } 691 #endif 692 693 /*-------------------------------------------------------------------------*/ 694 695 /* 696 * The AMCC 440EPx not only implements its EHCI registers in big-endian 697 * format, but also its DMA data structures (descriptors). 698 * 699 * EHCI controllers accessed through PCI work normally (little-endian 700 * everywhere), so we won't bother supporting a BE-only mode for now. 701 */ 702 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 703 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 704 705 /* cpu to ehci */ 706 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 707 { 708 return ehci_big_endian_desc(ehci) 709 ? (__force __hc32)cpu_to_be32(x) 710 : (__force __hc32)cpu_to_le32(x); 711 } 712 713 /* ehci to cpu */ 714 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 715 { 716 return ehci_big_endian_desc(ehci) 717 ? be32_to_cpu((__force __be32)x) 718 : le32_to_cpu((__force __le32)x); 719 } 720 721 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 722 { 723 return ehci_big_endian_desc(ehci) 724 ? be32_to_cpup((__force __be32 *)x) 725 : le32_to_cpup((__force __le32 *)x); 726 } 727 728 #else 729 730 /* cpu to ehci */ 731 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 732 { 733 return cpu_to_le32(x); 734 } 735 736 /* ehci to cpu */ 737 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 738 { 739 return le32_to_cpu(x); 740 } 741 742 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 743 { 744 return le32_to_cpup(x); 745 } 746 747 #endif 748 749 /*-------------------------------------------------------------------------*/ 750 751 #ifdef CONFIG_PCI 752 753 /* For working around the MosChip frame-index-register bug */ 754 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci); 755 756 #else 757 758 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) 759 { 760 return ehci_readl(ehci, &ehci->regs->frame_index); 761 } 762 763 #endif 764 765 /*-------------------------------------------------------------------------*/ 766 767 #ifndef DEBUG 768 #define STUB_DEBUG_FILES 769 #endif /* DEBUG */ 770 771 /*-------------------------------------------------------------------------*/ 772 773 #endif /* __LINUX_EHCI_HCD_H */ 774