1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* list of itds & sitds completed while clock_frame was still active */ 91 struct list_head cached_itd_list; 92 struct list_head cached_sitd_list; 93 unsigned clock_frame; 94 95 /* per root hub port */ 96 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 97 98 /* bit vectors (one bit per port) */ 99 unsigned long bus_suspended; /* which ports were 100 already suspended at the start of a bus suspend */ 101 unsigned long companion_ports; /* which ports are 102 dedicated to the companion controller */ 103 unsigned long owned_ports; /* which ports are 104 owned by the companion during a bus suspend */ 105 unsigned long port_c_suspend; /* which ports have 106 the change-suspend feature turned on */ 107 unsigned long suspended_ports; /* which ports are 108 suspended */ 109 110 /* per-HC memory pools (could be per-bus, but ...) */ 111 struct dma_pool *qh_pool; /* qh per active urb */ 112 struct dma_pool *qtd_pool; /* one or more per qh */ 113 struct dma_pool *itd_pool; /* itd per iso urb */ 114 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 115 116 struct timer_list iaa_watchdog; 117 struct timer_list watchdog; 118 unsigned long actions; 119 unsigned stamp; 120 unsigned random_frame; 121 unsigned long next_statechange; 122 ktime_t last_periodic_enable; 123 u32 command; 124 125 /* SILICON QUIRKS */ 126 unsigned no_selective_suspend:1; 127 unsigned has_fsl_port_bug:1; /* FreeScale */ 128 unsigned big_endian_mmio:1; 129 unsigned big_endian_desc:1; 130 unsigned has_amcc_usb23:1; 131 unsigned need_io_watchdog:1; 132 unsigned broken_periodic:1; 133 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 134 135 /* required for usb32 quirk */ 136 #define OHCI_CTRL_HCFS (3 << 6) 137 #define OHCI_USB_OPER (2 << 6) 138 #define OHCI_USB_SUSPEND (3 << 6) 139 140 #define OHCI_HCCTRL_OFFSET 0x4 141 #define OHCI_HCCTRL_LEN 0x4 142 __hc32 *ohci_hcctrl_reg; 143 unsigned has_hostpc:1; 144 unsigned has_lpm:1; /* support link power management */ 145 unsigned has_ppcd:1; /* support per-port change bits */ 146 u8 sbrn; /* packed release number */ 147 148 /* irq statistics */ 149 #ifdef EHCI_STATS 150 struct ehci_stats stats; 151 # define COUNT(x) do { (x)++; } while (0) 152 #else 153 # define COUNT(x) do {} while (0) 154 #endif 155 156 /* debug files */ 157 #ifdef DEBUG 158 struct dentry *debug_dir; 159 #endif 160 }; 161 162 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 163 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 164 { 165 return (struct ehci_hcd *) (hcd->hcd_priv); 166 } 167 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 168 { 169 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 170 } 171 172 173 static inline void 174 iaa_watchdog_start(struct ehci_hcd *ehci) 175 { 176 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 177 mod_timer(&ehci->iaa_watchdog, 178 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 179 } 180 181 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 182 { 183 del_timer(&ehci->iaa_watchdog); 184 } 185 186 enum ehci_timer_action { 187 TIMER_IO_WATCHDOG, 188 TIMER_ASYNC_SHRINK, 189 TIMER_ASYNC_OFF, 190 }; 191 192 static inline void 193 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 194 { 195 clear_bit (action, &ehci->actions); 196 } 197 198 static void free_cached_lists(struct ehci_hcd *ehci); 199 200 /*-------------------------------------------------------------------------*/ 201 202 #include <linux/usb/ehci_def.h> 203 204 /*-------------------------------------------------------------------------*/ 205 206 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 207 208 /* 209 * EHCI Specification 0.95 Section 3.5 210 * QTD: describe data transfer components (buffer, direction, ...) 211 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 212 * 213 * These are associated only with "QH" (Queue Head) structures, 214 * used with control, bulk, and interrupt transfers. 215 */ 216 struct ehci_qtd { 217 /* first part defined by EHCI spec */ 218 __hc32 hw_next; /* see EHCI 3.5.1 */ 219 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 220 __hc32 hw_token; /* see EHCI 3.5.3 */ 221 #define QTD_TOGGLE (1 << 31) /* data toggle */ 222 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 223 #define QTD_IOC (1 << 15) /* interrupt on complete */ 224 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 225 #define QTD_PID(tok) (((tok)>>8) & 0x3) 226 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 227 #define QTD_STS_HALT (1 << 6) /* halted on error */ 228 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 229 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 230 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 231 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 232 #define QTD_STS_STS (1 << 1) /* split transaction state */ 233 #define QTD_STS_PING (1 << 0) /* issue PING? */ 234 235 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 236 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 237 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 238 239 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 240 __hc32 hw_buf_hi [5]; /* Appendix B */ 241 242 /* the rest is HCD-private */ 243 dma_addr_t qtd_dma; /* qtd address */ 244 struct list_head qtd_list; /* sw qtd list */ 245 struct urb *urb; /* qtd's urb */ 246 size_t length; /* length of buffer */ 247 } __attribute__ ((aligned (32))); 248 249 /* mask NakCnt+T in qh->hw_alt_next */ 250 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 251 252 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 253 254 /*-------------------------------------------------------------------------*/ 255 256 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 257 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 258 259 /* 260 * Now the following defines are not converted using the 261 * cpu_to_le32() macro anymore, since we have to support 262 * "dynamic" switching between be and le support, so that the driver 263 * can be used on one system with SoC EHCI controller using big-endian 264 * descriptors as well as a normal little-endian PCI EHCI controller. 265 */ 266 /* values for that type tag */ 267 #define Q_TYPE_ITD (0 << 1) 268 #define Q_TYPE_QH (1 << 1) 269 #define Q_TYPE_SITD (2 << 1) 270 #define Q_TYPE_FSTN (3 << 1) 271 272 /* next async queue entry, or pointer to interrupt/periodic QH */ 273 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 274 275 /* for periodic/async schedules and qtd lists, mark end of list */ 276 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 277 278 /* 279 * Entries in periodic shadow table are pointers to one of four kinds 280 * of data structure. That's dictated by the hardware; a type tag is 281 * encoded in the low bits of the hardware's periodic schedule. Use 282 * Q_NEXT_TYPE to get the tag. 283 * 284 * For entries in the async schedule, the type tag always says "qh". 285 */ 286 union ehci_shadow { 287 struct ehci_qh *qh; /* Q_TYPE_QH */ 288 struct ehci_itd *itd; /* Q_TYPE_ITD */ 289 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 290 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 291 __hc32 *hw_next; /* (all types) */ 292 void *ptr; 293 }; 294 295 /*-------------------------------------------------------------------------*/ 296 297 /* 298 * EHCI Specification 0.95 Section 3.6 299 * QH: describes control/bulk/interrupt endpoints 300 * See Fig 3-7 "Queue Head Structure Layout". 301 * 302 * These appear in both the async and (for interrupt) periodic schedules. 303 */ 304 305 /* first part defined by EHCI spec */ 306 struct ehci_qh_hw { 307 __hc32 hw_next; /* see EHCI 3.6.1 */ 308 __hc32 hw_info1; /* see EHCI 3.6.2 */ 309 #define QH_HEAD 0x00008000 310 __hc32 hw_info2; /* see EHCI 3.6.2 */ 311 #define QH_SMASK 0x000000ff 312 #define QH_CMASK 0x0000ff00 313 #define QH_HUBADDR 0x007f0000 314 #define QH_HUBPORT 0x3f800000 315 #define QH_MULT 0xc0000000 316 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 317 318 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 319 __hc32 hw_qtd_next; 320 __hc32 hw_alt_next; 321 __hc32 hw_token; 322 __hc32 hw_buf [5]; 323 __hc32 hw_buf_hi [5]; 324 } __attribute__ ((aligned(32))); 325 326 struct ehci_qh { 327 struct ehci_qh_hw *hw; 328 /* the rest is HCD-private */ 329 dma_addr_t qh_dma; /* address of qh */ 330 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 331 struct list_head qtd_list; /* sw qtd list */ 332 struct ehci_qtd *dummy; 333 struct ehci_qh *reclaim; /* next to reclaim */ 334 335 struct ehci_hcd *ehci; 336 337 /* 338 * Do NOT use atomic operations for QH refcounting. On some CPUs 339 * (PPC7448 for example), atomic operations cannot be performed on 340 * memory that is cache-inhibited (i.e. being used for DMA). 341 * Spinlocks are used to protect all QH fields. 342 */ 343 u32 refcount; 344 unsigned stamp; 345 346 u8 needs_rescan; /* Dequeue during giveback */ 347 u8 qh_state; 348 #define QH_STATE_LINKED 1 /* HC sees this */ 349 #define QH_STATE_UNLINK 2 /* HC may still see this */ 350 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 351 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 352 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 353 354 u8 xacterrs; /* XactErr retry counter */ 355 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 356 357 /* periodic schedule info */ 358 u8 usecs; /* intr bandwidth */ 359 u8 gap_uf; /* uframes split/csplit gap */ 360 u8 c_usecs; /* ... split completion bw */ 361 u16 tt_usecs; /* tt downstream bandwidth */ 362 unsigned short period; /* polling interval */ 363 unsigned short start; /* where polling starts */ 364 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 365 366 struct usb_device *dev; /* access to TT */ 367 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 368 }; 369 370 /*-------------------------------------------------------------------------*/ 371 372 /* description of one iso transaction (up to 3 KB data if highspeed) */ 373 struct ehci_iso_packet { 374 /* These will be copied to iTD when scheduling */ 375 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 376 __hc32 transaction; /* itd->hw_transaction[i] |= */ 377 u8 cross; /* buf crosses pages */ 378 /* for full speed OUT splits */ 379 u32 buf1; 380 }; 381 382 /* temporary schedule data for packets from iso urbs (both speeds) 383 * each packet is one logical usb transaction to the device (not TT), 384 * beginning at stream->next_uframe 385 */ 386 struct ehci_iso_sched { 387 struct list_head td_list; 388 unsigned span; 389 struct ehci_iso_packet packet [0]; 390 }; 391 392 /* 393 * ehci_iso_stream - groups all (s)itds for this endpoint. 394 * acts like a qh would, if EHCI had them for ISO. 395 */ 396 struct ehci_iso_stream { 397 /* first field matches ehci_hq, but is NULL */ 398 struct ehci_qh_hw *hw; 399 400 u32 refcount; 401 u8 bEndpointAddress; 402 u8 highspeed; 403 struct list_head td_list; /* queued itds/sitds */ 404 struct list_head free_list; /* list of unused itds/sitds */ 405 struct usb_device *udev; 406 struct usb_host_endpoint *ep; 407 408 /* output of (re)scheduling */ 409 int next_uframe; 410 __hc32 splits; 411 412 /* the rest is derived from the endpoint descriptor, 413 * trusting urb->interval == f(epdesc->bInterval) and 414 * including the extra info for hw_bufp[0..2] 415 */ 416 u8 usecs, c_usecs; 417 u16 interval; 418 u16 tt_usecs; 419 u16 maxp; 420 u16 raw_mask; 421 unsigned bandwidth; 422 423 /* This is used to initialize iTD's hw_bufp fields */ 424 __hc32 buf0; 425 __hc32 buf1; 426 __hc32 buf2; 427 428 /* this is used to initialize sITD's tt info */ 429 __hc32 address; 430 }; 431 432 /*-------------------------------------------------------------------------*/ 433 434 /* 435 * EHCI Specification 0.95 Section 3.3 436 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 437 * 438 * Schedule records for high speed iso xfers 439 */ 440 struct ehci_itd { 441 /* first part defined by EHCI spec */ 442 __hc32 hw_next; /* see EHCI 3.3.1 */ 443 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 444 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 445 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 446 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 447 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 448 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 449 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 450 451 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 452 453 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 454 __hc32 hw_bufp_hi [7]; /* Appendix B */ 455 456 /* the rest is HCD-private */ 457 dma_addr_t itd_dma; /* for this itd */ 458 union ehci_shadow itd_next; /* ptr to periodic q entry */ 459 460 struct urb *urb; 461 struct ehci_iso_stream *stream; /* endpoint's queue */ 462 struct list_head itd_list; /* list of stream's itds */ 463 464 /* any/all hw_transactions here may be used by that urb */ 465 unsigned frame; /* where scheduled */ 466 unsigned pg; 467 unsigned index[8]; /* in urb->iso_frame_desc */ 468 } __attribute__ ((aligned (32))); 469 470 /*-------------------------------------------------------------------------*/ 471 472 /* 473 * EHCI Specification 0.95 Section 3.4 474 * siTD, aka split-transaction isochronous Transfer Descriptor 475 * ... describe full speed iso xfers through TT in hubs 476 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 477 */ 478 struct ehci_sitd { 479 /* first part defined by EHCI spec */ 480 __hc32 hw_next; 481 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 482 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 483 __hc32 hw_uframe; /* EHCI table 3-10 */ 484 __hc32 hw_results; /* EHCI table 3-11 */ 485 #define SITD_IOC (1 << 31) /* interrupt on completion */ 486 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 487 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 488 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 489 #define SITD_STS_ERR (1 << 6) /* error from TT */ 490 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 491 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 492 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 493 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 494 #define SITD_STS_STS (1 << 1) /* split transaction state */ 495 496 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 497 498 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 499 __hc32 hw_backpointer; /* EHCI table 3-13 */ 500 __hc32 hw_buf_hi [2]; /* Appendix B */ 501 502 /* the rest is HCD-private */ 503 dma_addr_t sitd_dma; 504 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 505 506 struct urb *urb; 507 struct ehci_iso_stream *stream; /* endpoint's queue */ 508 struct list_head sitd_list; /* list of stream's sitds */ 509 unsigned frame; 510 unsigned index; 511 } __attribute__ ((aligned (32))); 512 513 /*-------------------------------------------------------------------------*/ 514 515 /* 516 * EHCI Specification 0.96 Section 3.7 517 * Periodic Frame Span Traversal Node (FSTN) 518 * 519 * Manages split interrupt transactions (using TT) that span frame boundaries 520 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 521 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 522 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 523 */ 524 struct ehci_fstn { 525 __hc32 hw_next; /* any periodic q entry */ 526 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 527 528 /* the rest is HCD-private */ 529 dma_addr_t fstn_dma; 530 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 531 } __attribute__ ((aligned (32))); 532 533 /*-------------------------------------------------------------------------*/ 534 535 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 536 537 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 538 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 539 540 #define ehci_prepare_ports_for_controller_resume(ehci) \ 541 ehci_adjust_port_wakeup_flags(ehci, false, false); 542 543 /*-------------------------------------------------------------------------*/ 544 545 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 546 547 /* 548 * Some EHCI controllers have a Transaction Translator built into the 549 * root hub. This is a non-standard feature. Each controller will need 550 * to add code to the following inline functions, and call them as 551 * needed (mostly in root hub code). 552 */ 553 554 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 555 556 /* Returns the speed of a device attached to a port on the root hub. */ 557 static inline unsigned int 558 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 559 { 560 if (ehci_is_TDI(ehci)) { 561 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 562 case 0: 563 return 0; 564 case 1: 565 return USB_PORT_STAT_LOW_SPEED; 566 case 2: 567 default: 568 return USB_PORT_STAT_HIGH_SPEED; 569 } 570 } 571 return USB_PORT_STAT_HIGH_SPEED; 572 } 573 574 #else 575 576 #define ehci_is_TDI(e) (0) 577 578 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 579 #endif 580 581 /*-------------------------------------------------------------------------*/ 582 583 #ifdef CONFIG_PPC_83xx 584 /* Some Freescale processors have an erratum in which the TT 585 * port number in the queue head was 0..N-1 instead of 1..N. 586 */ 587 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 588 #else 589 #define ehci_has_fsl_portno_bug(e) (0) 590 #endif 591 592 /* 593 * While most USB host controllers implement their registers in 594 * little-endian format, a minority (celleb companion chip) implement 595 * them in big endian format. 596 * 597 * This attempts to support either format at compile time without a 598 * runtime penalty, or both formats with the additional overhead 599 * of checking a flag bit. 600 */ 601 602 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 603 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 604 #else 605 #define ehci_big_endian_mmio(e) 0 606 #endif 607 608 /* 609 * Big-endian read/write functions are arch-specific. 610 * Other arches can be added if/when they're needed. 611 */ 612 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 613 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 614 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 615 #endif 616 617 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 618 __u32 __iomem * regs) 619 { 620 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 621 return ehci_big_endian_mmio(ehci) ? 622 readl_be(regs) : 623 readl(regs); 624 #else 625 return readl(regs); 626 #endif 627 } 628 629 static inline void ehci_writel(const struct ehci_hcd *ehci, 630 const unsigned int val, __u32 __iomem *regs) 631 { 632 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 633 ehci_big_endian_mmio(ehci) ? 634 writel_be(val, regs) : 635 writel(val, regs); 636 #else 637 writel(val, regs); 638 #endif 639 } 640 641 /* 642 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 643 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 644 * Other common bits are dependant on has_amcc_usb23 quirk flag. 645 */ 646 #ifdef CONFIG_44x 647 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 648 { 649 u32 hc_control; 650 651 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 652 if (operational) 653 hc_control |= OHCI_USB_OPER; 654 else 655 hc_control |= OHCI_USB_SUSPEND; 656 657 writel_be(hc_control, ehci->ohci_hcctrl_reg); 658 (void) readl_be(ehci->ohci_hcctrl_reg); 659 } 660 #else 661 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 662 { } 663 #endif 664 665 /*-------------------------------------------------------------------------*/ 666 667 /* 668 * The AMCC 440EPx not only implements its EHCI registers in big-endian 669 * format, but also its DMA data structures (descriptors). 670 * 671 * EHCI controllers accessed through PCI work normally (little-endian 672 * everywhere), so we won't bother supporting a BE-only mode for now. 673 */ 674 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 675 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 676 677 /* cpu to ehci */ 678 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 679 { 680 return ehci_big_endian_desc(ehci) 681 ? (__force __hc32)cpu_to_be32(x) 682 : (__force __hc32)cpu_to_le32(x); 683 } 684 685 /* ehci to cpu */ 686 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 687 { 688 return ehci_big_endian_desc(ehci) 689 ? be32_to_cpu((__force __be32)x) 690 : le32_to_cpu((__force __le32)x); 691 } 692 693 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 694 { 695 return ehci_big_endian_desc(ehci) 696 ? be32_to_cpup((__force __be32 *)x) 697 : le32_to_cpup((__force __le32 *)x); 698 } 699 700 #else 701 702 /* cpu to ehci */ 703 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 704 { 705 return cpu_to_le32(x); 706 } 707 708 /* ehci to cpu */ 709 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 710 { 711 return le32_to_cpu(x); 712 } 713 714 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 715 { 716 return le32_to_cpup(x); 717 } 718 719 #endif 720 721 /*-------------------------------------------------------------------------*/ 722 723 #ifndef DEBUG 724 #define STUB_DEBUG_FILES 725 #endif /* DEBUG */ 726 727 /*-------------------------------------------------------------------------*/ 728 729 #endif /* __LINUX_EHCI_HCD_H */ 730