1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 #ifdef CONFIG_DYNAMIC_DEBUG 42 #define EHCI_STATS 43 #endif 44 45 struct ehci_stats { 46 /* irq usage */ 47 unsigned long normal; 48 unsigned long error; 49 unsigned long iaa; 50 unsigned long lost_iaa; 51 52 /* termination of urbs from core */ 53 unsigned long complete; 54 unsigned long unlink; 55 }; 56 57 /* 58 * Scheduling and budgeting information for periodic transfers, for both 59 * high-speed devices and full/low-speed devices lying behind a TT. 60 */ 61 struct ehci_per_sched { 62 struct usb_device *udev; /* access to the TT */ 63 struct usb_host_endpoint *ep; 64 struct list_head ps_list; /* node on ehci_tt's ps_list */ 65 u16 tt_usecs; /* time on the FS/LS bus */ 66 u16 cs_mask; /* C-mask and S-mask bytes */ 67 u16 period; /* actual period in frames */ 68 u16 phase; /* actual phase, frame part */ 69 u8 bw_phase; /* same, for bandwidth 70 reservation */ 71 u8 phase_uf; /* uframe part of the phase */ 72 u8 usecs, c_usecs; /* times on the HS bus */ 73 u8 bw_uperiod; /* period in microframes, for 74 bandwidth reservation */ 75 u8 bw_period; /* same, in frames */ 76 }; 77 #define NO_FRAME 29999 /* frame not assigned yet */ 78 79 /* ehci_hcd->lock guards shared data against other CPUs: 80 * ehci_hcd: async, unlink, periodic (and shadow), ... 81 * usb_host_endpoint: hcpriv 82 * ehci_qh: qh_next, qtd_list 83 * ehci_qtd: qtd_list 84 * 85 * Also, hold this lock when talking to HC registers or 86 * when updating hw_* fields in shared qh/qtd/... structures. 87 */ 88 89 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 90 91 /* 92 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 93 * controller may be doing DMA. Lower values mean there's no DMA. 94 */ 95 enum ehci_rh_state { 96 EHCI_RH_HALTED, 97 EHCI_RH_SUSPENDED, 98 EHCI_RH_RUNNING, 99 EHCI_RH_STOPPING 100 }; 101 102 /* 103 * Timer events, ordered by increasing delay length. 104 * Always update event_delays_ns[] and event_handlers[] (defined in 105 * ehci-timer.c) in parallel with this list. 106 */ 107 enum ehci_hrtimer_event { 108 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 109 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 110 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 111 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 112 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 113 EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ 114 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ 115 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 116 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 117 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 118 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 119 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 120 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 121 }; 122 #define EHCI_HRTIMER_NO_EVENT 99 123 124 struct ehci_hcd { /* one per controller */ 125 /* timing support */ 126 enum ehci_hrtimer_event next_hrtimer_event; 127 unsigned enabled_hrtimer_events; 128 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 129 struct hrtimer hrtimer; 130 131 int PSS_poll_count; 132 int ASS_poll_count; 133 int died_poll_count; 134 135 /* glue to PCI and HCD framework */ 136 struct ehci_caps __iomem *caps; 137 struct ehci_regs __iomem *regs; 138 struct ehci_dbg_port __iomem *debug; 139 140 __u32 hcs_params; /* cached register copy */ 141 spinlock_t lock; 142 enum ehci_rh_state rh_state; 143 144 /* general schedule support */ 145 bool scanning:1; 146 bool need_rescan:1; 147 bool intr_unlinking:1; 148 bool iaa_in_progress:1; 149 bool async_unlinking:1; 150 bool shutdown:1; 151 struct ehci_qh *qh_scan_next; 152 153 /* async schedule support */ 154 struct ehci_qh *async; 155 struct ehci_qh *dummy; /* For AMD quirk use */ 156 struct list_head async_unlink; 157 struct list_head async_idle; 158 unsigned async_unlink_cycle; 159 unsigned async_count; /* async activity count */ 160 __hc32 old_current; /* Test for QH becoming */ 161 __hc32 old_token; /* inactive during unlink */ 162 163 /* periodic schedule support */ 164 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 165 unsigned periodic_size; 166 __hc32 *periodic; /* hw periodic table */ 167 dma_addr_t periodic_dma; 168 struct list_head intr_qh_list; 169 unsigned i_thresh; /* uframes HC might cache */ 170 171 union ehci_shadow *pshadow; /* mirror hw periodic table */ 172 struct list_head intr_unlink_wait; 173 struct list_head intr_unlink; 174 unsigned intr_unlink_wait_cycle; 175 unsigned intr_unlink_cycle; 176 unsigned now_frame; /* frame from HC hardware */ 177 unsigned last_iso_frame; /* last frame scanned for iso */ 178 unsigned intr_count; /* intr activity count */ 179 unsigned isoc_count; /* isoc activity count */ 180 unsigned periodic_count; /* periodic activity count */ 181 unsigned uframe_periodic_max; /* max periodic time per uframe */ 182 183 184 /* list of itds & sitds completed while now_frame was still active */ 185 struct list_head cached_itd_list; 186 struct ehci_itd *last_itd_to_free; 187 struct list_head cached_sitd_list; 188 struct ehci_sitd *last_sitd_to_free; 189 190 /* per root hub port */ 191 unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; 192 193 /* bit vectors (one bit per port) */ 194 unsigned long bus_suspended; /* which ports were 195 already suspended at the start of a bus suspend */ 196 unsigned long companion_ports; /* which ports are 197 dedicated to the companion controller */ 198 unsigned long owned_ports; /* which ports are 199 owned by the companion during a bus suspend */ 200 unsigned long port_c_suspend; /* which ports have 201 the change-suspend feature turned on */ 202 unsigned long suspended_ports; /* which ports are 203 suspended */ 204 unsigned long resuming_ports; /* which ports have 205 started to resume */ 206 207 /* per-HC memory pools (could be per-bus, but ...) */ 208 struct dma_pool *qh_pool; /* qh per active urb */ 209 struct dma_pool *qtd_pool; /* one or more per qh */ 210 struct dma_pool *itd_pool; /* itd per iso urb */ 211 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 212 213 unsigned random_frame; 214 unsigned long next_statechange; 215 ktime_t last_periodic_enable; 216 u32 command; 217 218 /* SILICON QUIRKS */ 219 unsigned no_selective_suspend:1; 220 unsigned has_fsl_port_bug:1; /* FreeScale */ 221 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ 222 unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ 223 unsigned big_endian_mmio:1; 224 unsigned big_endian_desc:1; 225 unsigned big_endian_capbase:1; 226 unsigned has_amcc_usb23:1; 227 unsigned need_io_watchdog:1; 228 unsigned amd_pll_fix:1; 229 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 230 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 231 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 232 unsigned need_oc_pp_cycle:1; /* MPC834X port power */ 233 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ 234 235 /* required for usb32 quirk */ 236 #define OHCI_CTRL_HCFS (3 << 6) 237 #define OHCI_USB_OPER (2 << 6) 238 #define OHCI_USB_SUSPEND (3 << 6) 239 240 #define OHCI_HCCTRL_OFFSET 0x4 241 #define OHCI_HCCTRL_LEN 0x4 242 __hc32 *ohci_hcctrl_reg; 243 unsigned has_hostpc:1; 244 unsigned has_tdi_phy_lpm:1; 245 unsigned has_ppcd:1; /* support per-port change bits */ 246 u8 sbrn; /* packed release number */ 247 248 /* irq statistics */ 249 #ifdef EHCI_STATS 250 struct ehci_stats stats; 251 # define COUNT(x) ((x)++) 252 #else 253 # define COUNT(x) 254 #endif 255 256 /* debug files */ 257 #ifdef CONFIG_DYNAMIC_DEBUG 258 struct dentry *debug_dir; 259 #endif 260 261 /* bandwidth usage */ 262 #define EHCI_BANDWIDTH_SIZE 64 263 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) 264 u8 bandwidth[EHCI_BANDWIDTH_SIZE]; 265 /* us allocated per uframe */ 266 u8 tt_budget[EHCI_BANDWIDTH_SIZE]; 267 /* us budgeted per uframe */ 268 struct list_head tt_list; 269 270 /* platform-specific data -- must come last */ 271 unsigned long priv[0] __aligned(sizeof(s64)); 272 }; 273 274 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 275 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd) 276 { 277 return (struct ehci_hcd *) (hcd->hcd_priv); 278 } 279 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) 280 { 281 return container_of((void *) ehci, struct usb_hcd, hcd_priv); 282 } 283 284 /*-------------------------------------------------------------------------*/ 285 286 #include <linux/usb/ehci_def.h> 287 288 /*-------------------------------------------------------------------------*/ 289 290 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 291 292 /* 293 * EHCI Specification 0.95 Section 3.5 294 * QTD: describe data transfer components (buffer, direction, ...) 295 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 296 * 297 * These are associated only with "QH" (Queue Head) structures, 298 * used with control, bulk, and interrupt transfers. 299 */ 300 struct ehci_qtd { 301 /* first part defined by EHCI spec */ 302 __hc32 hw_next; /* see EHCI 3.5.1 */ 303 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 304 __hc32 hw_token; /* see EHCI 3.5.3 */ 305 #define QTD_TOGGLE (1 << 31) /* data toggle */ 306 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 307 #define QTD_IOC (1 << 15) /* interrupt on complete */ 308 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 309 #define QTD_PID(tok) (((tok)>>8) & 0x3) 310 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 311 #define QTD_STS_HALT (1 << 6) /* halted on error */ 312 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 313 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 314 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 315 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 316 #define QTD_STS_STS (1 << 1) /* split transaction state */ 317 #define QTD_STS_PING (1 << 0) /* issue PING? */ 318 319 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 320 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 321 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 322 323 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ 324 __hc32 hw_buf_hi[5]; /* Appendix B */ 325 326 /* the rest is HCD-private */ 327 dma_addr_t qtd_dma; /* qtd address */ 328 struct list_head qtd_list; /* sw qtd list */ 329 struct urb *urb; /* qtd's urb */ 330 size_t length; /* length of buffer */ 331 } __aligned(32); 332 333 /* mask NakCnt+T in qh->hw_alt_next */ 334 #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f) 335 336 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) 337 338 /*-------------------------------------------------------------------------*/ 339 340 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 341 #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 342 343 /* 344 * Now the following defines are not converted using the 345 * cpu_to_le32() macro anymore, since we have to support 346 * "dynamic" switching between be and le support, so that the driver 347 * can be used on one system with SoC EHCI controller using big-endian 348 * descriptors as well as a normal little-endian PCI EHCI controller. 349 */ 350 /* values for that type tag */ 351 #define Q_TYPE_ITD (0 << 1) 352 #define Q_TYPE_QH (1 << 1) 353 #define Q_TYPE_SITD (2 << 1) 354 #define Q_TYPE_FSTN (3 << 1) 355 356 /* next async queue entry, or pointer to interrupt/periodic QH */ 357 #define QH_NEXT(ehci, dma) \ 358 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH)) 359 360 /* for periodic/async schedules and qtd lists, mark end of list */ 361 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 362 363 /* 364 * Entries in periodic shadow table are pointers to one of four kinds 365 * of data structure. That's dictated by the hardware; a type tag is 366 * encoded in the low bits of the hardware's periodic schedule. Use 367 * Q_NEXT_TYPE to get the tag. 368 * 369 * For entries in the async schedule, the type tag always says "qh". 370 */ 371 union ehci_shadow { 372 struct ehci_qh *qh; /* Q_TYPE_QH */ 373 struct ehci_itd *itd; /* Q_TYPE_ITD */ 374 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 375 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 376 __hc32 *hw_next; /* (all types) */ 377 void *ptr; 378 }; 379 380 /*-------------------------------------------------------------------------*/ 381 382 /* 383 * EHCI Specification 0.95 Section 3.6 384 * QH: describes control/bulk/interrupt endpoints 385 * See Fig 3-7 "Queue Head Structure Layout". 386 * 387 * These appear in both the async and (for interrupt) periodic schedules. 388 */ 389 390 /* first part defined by EHCI spec */ 391 struct ehci_qh_hw { 392 __hc32 hw_next; /* see EHCI 3.6.1 */ 393 __hc32 hw_info1; /* see EHCI 3.6.2 */ 394 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 395 #define QH_HEAD (1 << 15) /* Head of async reclamation list */ 396 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 397 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 398 #define QH_LOW_SPEED (1 << 12) 399 #define QH_FULL_SPEED (0 << 12) 400 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 401 __hc32 hw_info2; /* see EHCI 3.6.2 */ 402 #define QH_SMASK 0x000000ff 403 #define QH_CMASK 0x0000ff00 404 #define QH_HUBADDR 0x007f0000 405 #define QH_HUBPORT 0x3f800000 406 #define QH_MULT 0xc0000000 407 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 408 409 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 410 __hc32 hw_qtd_next; 411 __hc32 hw_alt_next; 412 __hc32 hw_token; 413 __hc32 hw_buf[5]; 414 __hc32 hw_buf_hi[5]; 415 } __aligned(32); 416 417 struct ehci_qh { 418 struct ehci_qh_hw *hw; /* Must come first */ 419 /* the rest is HCD-private */ 420 dma_addr_t qh_dma; /* address of qh */ 421 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 422 struct list_head qtd_list; /* sw qtd list */ 423 struct list_head intr_node; /* list of intr QHs */ 424 struct ehci_qtd *dummy; 425 struct list_head unlink_node; 426 struct ehci_per_sched ps; /* scheduling info */ 427 428 unsigned unlink_cycle; 429 430 u8 qh_state; 431 #define QH_STATE_LINKED 1 /* HC sees this */ 432 #define QH_STATE_UNLINK 2 /* HC may still see this */ 433 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 434 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 435 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 436 437 u8 xacterrs; /* XactErr retry counter */ 438 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 439 440 u8 unlink_reason; 441 #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ 442 #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ 443 #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ 444 #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ 445 #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ 446 #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ 447 448 u8 gap_uf; /* uframes split/csplit gap */ 449 450 unsigned is_out:1; /* bulk or intr OUT */ 451 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 452 unsigned dequeue_during_giveback:1; 453 unsigned should_be_inactive:1; 454 }; 455 456 /*-------------------------------------------------------------------------*/ 457 458 /* description of one iso transaction (up to 3 KB data if highspeed) */ 459 struct ehci_iso_packet { 460 /* These will be copied to iTD when scheduling */ 461 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 462 __hc32 transaction; /* itd->hw_transaction[i] |= */ 463 u8 cross; /* buf crosses pages */ 464 /* for full speed OUT splits */ 465 u32 buf1; 466 }; 467 468 /* temporary schedule data for packets from iso urbs (both speeds) 469 * each packet is one logical usb transaction to the device (not TT), 470 * beginning at stream->next_uframe 471 */ 472 struct ehci_iso_sched { 473 struct list_head td_list; 474 unsigned span; 475 unsigned first_packet; 476 struct ehci_iso_packet packet[0]; 477 }; 478 479 /* 480 * ehci_iso_stream - groups all (s)itds for this endpoint. 481 * acts like a qh would, if EHCI had them for ISO. 482 */ 483 struct ehci_iso_stream { 484 /* first field matches ehci_hq, but is NULL */ 485 struct ehci_qh_hw *hw; 486 487 u8 bEndpointAddress; 488 u8 highspeed; 489 struct list_head td_list; /* queued itds/sitds */ 490 struct list_head free_list; /* list of unused itds/sitds */ 491 492 /* output of (re)scheduling */ 493 struct ehci_per_sched ps; /* scheduling info */ 494 unsigned next_uframe; 495 __hc32 splits; 496 497 /* the rest is derived from the endpoint descriptor, 498 * including the extra info for hw_bufp[0..2] 499 */ 500 u16 uperiod; /* period in uframes */ 501 u16 maxp; 502 unsigned bandwidth; 503 504 /* This is used to initialize iTD's hw_bufp fields */ 505 __hc32 buf0; 506 __hc32 buf1; 507 __hc32 buf2; 508 509 /* this is used to initialize sITD's tt info */ 510 __hc32 address; 511 }; 512 513 /*-------------------------------------------------------------------------*/ 514 515 /* 516 * EHCI Specification 0.95 Section 3.3 517 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 518 * 519 * Schedule records for high speed iso xfers 520 */ 521 struct ehci_itd { 522 /* first part defined by EHCI spec */ 523 __hc32 hw_next; /* see EHCI 3.3.1 */ 524 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ 525 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 526 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 527 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 528 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 529 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 530 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 531 532 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 533 534 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ 535 __hc32 hw_bufp_hi[7]; /* Appendix B */ 536 537 /* the rest is HCD-private */ 538 dma_addr_t itd_dma; /* for this itd */ 539 union ehci_shadow itd_next; /* ptr to periodic q entry */ 540 541 struct urb *urb; 542 struct ehci_iso_stream *stream; /* endpoint's queue */ 543 struct list_head itd_list; /* list of stream's itds */ 544 545 /* any/all hw_transactions here may be used by that urb */ 546 unsigned frame; /* where scheduled */ 547 unsigned pg; 548 unsigned index[8]; /* in urb->iso_frame_desc */ 549 } __aligned(32); 550 551 /*-------------------------------------------------------------------------*/ 552 553 /* 554 * EHCI Specification 0.95 Section 3.4 555 * siTD, aka split-transaction isochronous Transfer Descriptor 556 * ... describe full speed iso xfers through TT in hubs 557 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 558 */ 559 struct ehci_sitd { 560 /* first part defined by EHCI spec */ 561 __hc32 hw_next; 562 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 563 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 564 __hc32 hw_uframe; /* EHCI table 3-10 */ 565 __hc32 hw_results; /* EHCI table 3-11 */ 566 #define SITD_IOC (1 << 31) /* interrupt on completion */ 567 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 568 #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff) 569 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 570 #define SITD_STS_ERR (1 << 6) /* error from TT */ 571 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 572 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 573 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 574 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 575 #define SITD_STS_STS (1 << 1) /* split transaction state */ 576 577 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 578 579 __hc32 hw_buf[2]; /* EHCI table 3-12 */ 580 __hc32 hw_backpointer; /* EHCI table 3-13 */ 581 __hc32 hw_buf_hi[2]; /* Appendix B */ 582 583 /* the rest is HCD-private */ 584 dma_addr_t sitd_dma; 585 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 586 587 struct urb *urb; 588 struct ehci_iso_stream *stream; /* endpoint's queue */ 589 struct list_head sitd_list; /* list of stream's sitds */ 590 unsigned frame; 591 unsigned index; 592 } __aligned(32); 593 594 /*-------------------------------------------------------------------------*/ 595 596 /* 597 * EHCI Specification 0.96 Section 3.7 598 * Periodic Frame Span Traversal Node (FSTN) 599 * 600 * Manages split interrupt transactions (using TT) that span frame boundaries 601 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 602 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 603 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 604 */ 605 struct ehci_fstn { 606 __hc32 hw_next; /* any periodic q entry */ 607 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 608 609 /* the rest is HCD-private */ 610 dma_addr_t fstn_dma; 611 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 612 } __aligned(32); 613 614 /*-------------------------------------------------------------------------*/ 615 616 /* 617 * USB-2.0 Specification Sections 11.14 and 11.18 618 * Scheduling and budgeting split transactions using TTs 619 * 620 * A hub can have a single TT for all its ports, or multiple TTs (one for each 621 * port). The bandwidth and budgeting information for the full/low-speed bus 622 * below each TT is self-contained and independent of the other TTs or the 623 * high-speed bus. 624 * 625 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated 626 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to 627 * the best-case estimate of the number of full-speed bytes allocated to an 628 * endpoint for each microframe within an allocated frame. 629 * 630 * Removal of an endpoint invalidates a TT's budget. Instead of trying to 631 * keep an up-to-date record, we recompute the budget when it is needed. 632 */ 633 634 struct ehci_tt { 635 u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; 636 637 struct list_head tt_list; /* List of all ehci_tt's */ 638 struct list_head ps_list; /* Items using this TT */ 639 struct usb_tt *usb_tt; 640 int tt_port; /* TT port number */ 641 }; 642 643 /*-------------------------------------------------------------------------*/ 644 645 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 646 647 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 648 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup) 649 650 #define ehci_prepare_ports_for_controller_resume(ehci) \ 651 ehci_adjust_port_wakeup_flags(ehci, false, false) 652 653 /*-------------------------------------------------------------------------*/ 654 655 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 656 657 /* 658 * Some EHCI controllers have a Transaction Translator built into the 659 * root hub. This is a non-standard feature. Each controller will need 660 * to add code to the following inline functions, and call them as 661 * needed (mostly in root hub code). 662 */ 663 664 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 665 666 /* Returns the speed of a device attached to a port on the root hub. */ 667 static inline unsigned int 668 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 669 { 670 if (ehci_is_TDI(ehci)) { 671 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 672 case 0: 673 return 0; 674 case 1: 675 return USB_PORT_STAT_LOW_SPEED; 676 case 2: 677 default: 678 return USB_PORT_STAT_HIGH_SPEED; 679 } 680 } 681 return USB_PORT_STAT_HIGH_SPEED; 682 } 683 684 #else 685 686 #define ehci_is_TDI(e) (0) 687 688 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 689 #endif 690 691 /*-------------------------------------------------------------------------*/ 692 693 #ifdef CONFIG_PPC_83xx 694 /* Some Freescale processors have an erratum in which the TT 695 * port number in the queue head was 0..N-1 instead of 1..N. 696 */ 697 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 698 #else 699 #define ehci_has_fsl_portno_bug(e) (0) 700 #endif 701 702 #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */ 703 704 #if defined(CONFIG_PPC_85xx) 705 /* Some Freescale processors have an erratum (USB A-005275) in which 706 * incoming packets get corrupted in HS mode 707 */ 708 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata) 709 #else 710 #define ehci_has_fsl_hs_errata(e) (0) 711 #endif 712 713 /* 714 * Some Freescale/NXP processors have an erratum (USB A-005697) 715 * in which we need to wait for 10ms for bus to enter suspend mode 716 * after setting SUSP bit. 717 */ 718 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata) 719 720 /* 721 * While most USB host controllers implement their registers in 722 * little-endian format, a minority (celleb companion chip) implement 723 * them in big endian format. 724 * 725 * This attempts to support either format at compile time without a 726 * runtime penalty, or both formats with the additional overhead 727 * of checking a flag bit. 728 * 729 * ehci_big_endian_capbase is a special quirk for controllers that 730 * implement the HC capability registers as separate registers and not 731 * as fields of a 32-bit register. 732 */ 733 734 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 735 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 736 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 737 #else 738 #define ehci_big_endian_mmio(e) 0 739 #define ehci_big_endian_capbase(e) 0 740 #endif 741 742 /* 743 * Big-endian read/write functions are arch-specific. 744 * Other arches can be added if/when they're needed. 745 */ 746 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 747 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 748 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 749 #endif 750 751 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 752 __u32 __iomem *regs) 753 { 754 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 755 return ehci_big_endian_mmio(ehci) ? 756 readl_be(regs) : 757 readl(regs); 758 #else 759 return readl(regs); 760 #endif 761 } 762 763 #ifdef CONFIG_SOC_IMX28 764 static inline void imx28_ehci_writel(const unsigned int val, 765 volatile __u32 __iomem *addr) 766 { 767 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 768 } 769 #else 770 static inline void imx28_ehci_writel(const unsigned int val, 771 volatile __u32 __iomem *addr) 772 { 773 } 774 #endif 775 static inline void ehci_writel(const struct ehci_hcd *ehci, 776 const unsigned int val, __u32 __iomem *regs) 777 { 778 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 779 ehci_big_endian_mmio(ehci) ? 780 writel_be(val, regs) : 781 writel(val, regs); 782 #else 783 if (ehci->imx28_write_fix) 784 imx28_ehci_writel(val, regs); 785 else 786 writel(val, regs); 787 #endif 788 } 789 790 /* 791 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 792 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 793 * Other common bits are dependent on has_amcc_usb23 quirk flag. 794 */ 795 #ifdef CONFIG_44x 796 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 797 { 798 u32 hc_control; 799 800 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 801 if (operational) 802 hc_control |= OHCI_USB_OPER; 803 else 804 hc_control |= OHCI_USB_SUSPEND; 805 806 writel_be(hc_control, ehci->ohci_hcctrl_reg); 807 (void) readl_be(ehci->ohci_hcctrl_reg); 808 } 809 #else 810 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 811 { } 812 #endif 813 814 /*-------------------------------------------------------------------------*/ 815 816 /* 817 * The AMCC 440EPx not only implements its EHCI registers in big-endian 818 * format, but also its DMA data structures (descriptors). 819 * 820 * EHCI controllers accessed through PCI work normally (little-endian 821 * everywhere), so we won't bother supporting a BE-only mode for now. 822 */ 823 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 824 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 825 826 /* cpu to ehci */ 827 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) 828 { 829 return ehci_big_endian_desc(ehci) 830 ? (__force __hc32)cpu_to_be32(x) 831 : (__force __hc32)cpu_to_le32(x); 832 } 833 834 /* ehci to cpu */ 835 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) 836 { 837 return ehci_big_endian_desc(ehci) 838 ? be32_to_cpu((__force __be32)x) 839 : le32_to_cpu((__force __le32)x); 840 } 841 842 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) 843 { 844 return ehci_big_endian_desc(ehci) 845 ? be32_to_cpup((__force __be32 *)x) 846 : le32_to_cpup((__force __le32 *)x); 847 } 848 849 #else 850 851 /* cpu to ehci */ 852 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) 853 { 854 return cpu_to_le32(x); 855 } 856 857 /* ehci to cpu */ 858 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) 859 { 860 return le32_to_cpu(x); 861 } 862 863 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) 864 { 865 return le32_to_cpup(x); 866 } 867 868 #endif 869 870 /*-------------------------------------------------------------------------*/ 871 872 #define ehci_dbg(ehci, fmt, args...) \ 873 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 874 #define ehci_err(ehci, fmt, args...) \ 875 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 876 #define ehci_info(ehci, fmt, args...) \ 877 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 878 #define ehci_warn(ehci, fmt, args...) \ 879 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 880 881 /*-------------------------------------------------------------------------*/ 882 883 /* Declarations of things exported for use by ehci platform drivers */ 884 885 struct ehci_driver_overrides { 886 size_t extra_priv_size; 887 int (*reset)(struct usb_hcd *hcd); 888 int (*port_power)(struct usb_hcd *hcd, 889 int portnum, bool enable); 890 }; 891 892 extern void ehci_init_driver(struct hc_driver *drv, 893 const struct ehci_driver_overrides *over); 894 extern int ehci_setup(struct usb_hcd *hcd); 895 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 896 u32 mask, u32 done, int usec); 897 extern int ehci_reset(struct ehci_hcd *ehci); 898 899 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 900 extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); 901 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, 902 bool suspending, bool do_wakeup); 903 904 extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 905 u16 wIndex, char *buf, u16 wLength); 906 907 #endif /* __LINUX_EHCI_HCD_H */ 908