1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2001-2002 by David Brownell 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software Foundation, 17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #ifndef __LINUX_EHCI_HCD_H 21 #define __LINUX_EHCI_HCD_H 22 23 /* definitions used for the EHCI driver */ 24 25 /* 26 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 27 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 28 * the host controller implementation. 29 * 30 * To facilitate the strongest possible byte-order checking from "sparse" 31 * and so on, we use __leXX unless that's not practical. 32 */ 33 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 34 typedef __u32 __bitwise __hc32; 35 typedef __u16 __bitwise __hc16; 36 #else 37 #define __hc32 __le32 38 #define __hc16 __le16 39 #endif 40 41 /* statistics can be kept for tuning/monitoring */ 42 #ifdef CONFIG_DYNAMIC_DEBUG 43 #define EHCI_STATS 44 #endif 45 46 struct ehci_stats { 47 /* irq usage */ 48 unsigned long normal; 49 unsigned long error; 50 unsigned long iaa; 51 unsigned long lost_iaa; 52 53 /* termination of urbs from core */ 54 unsigned long complete; 55 unsigned long unlink; 56 }; 57 58 /* 59 * Scheduling and budgeting information for periodic transfers, for both 60 * high-speed devices and full/low-speed devices lying behind a TT. 61 */ 62 struct ehci_per_sched { 63 struct usb_device *udev; /* access to the TT */ 64 struct usb_host_endpoint *ep; 65 struct list_head ps_list; /* node on ehci_tt's ps_list */ 66 u16 tt_usecs; /* time on the FS/LS bus */ 67 u16 cs_mask; /* C-mask and S-mask bytes */ 68 u16 period; /* actual period in frames */ 69 u16 phase; /* actual phase, frame part */ 70 u8 bw_phase; /* same, for bandwidth 71 reservation */ 72 u8 phase_uf; /* uframe part of the phase */ 73 u8 usecs, c_usecs; /* times on the HS bus */ 74 u8 bw_uperiod; /* period in microframes, for 75 bandwidth reservation */ 76 u8 bw_period; /* same, in frames */ 77 }; 78 #define NO_FRAME 29999 /* frame not assigned yet */ 79 80 /* ehci_hcd->lock guards shared data against other CPUs: 81 * ehci_hcd: async, unlink, periodic (and shadow), ... 82 * usb_host_endpoint: hcpriv 83 * ehci_qh: qh_next, qtd_list 84 * ehci_qtd: qtd_list 85 * 86 * Also, hold this lock when talking to HC registers or 87 * when updating hw_* fields in shared qh/qtd/... structures. 88 */ 89 90 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 91 92 /* 93 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 94 * controller may be doing DMA. Lower values mean there's no DMA. 95 */ 96 enum ehci_rh_state { 97 EHCI_RH_HALTED, 98 EHCI_RH_SUSPENDED, 99 EHCI_RH_RUNNING, 100 EHCI_RH_STOPPING 101 }; 102 103 /* 104 * Timer events, ordered by increasing delay length. 105 * Always update event_delays_ns[] and event_handlers[] (defined in 106 * ehci-timer.c) in parallel with this list. 107 */ 108 enum ehci_hrtimer_event { 109 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 110 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 111 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 112 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 113 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 114 EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ 115 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ 116 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 117 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 118 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 119 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 120 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 121 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 122 }; 123 #define EHCI_HRTIMER_NO_EVENT 99 124 125 struct ehci_hcd { /* one per controller */ 126 /* timing support */ 127 enum ehci_hrtimer_event next_hrtimer_event; 128 unsigned enabled_hrtimer_events; 129 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 130 struct hrtimer hrtimer; 131 132 int PSS_poll_count; 133 int ASS_poll_count; 134 int died_poll_count; 135 136 /* glue to PCI and HCD framework */ 137 struct ehci_caps __iomem *caps; 138 struct ehci_regs __iomem *regs; 139 struct ehci_dbg_port __iomem *debug; 140 141 __u32 hcs_params; /* cached register copy */ 142 spinlock_t lock; 143 enum ehci_rh_state rh_state; 144 145 /* general schedule support */ 146 bool scanning:1; 147 bool need_rescan:1; 148 bool intr_unlinking:1; 149 bool iaa_in_progress:1; 150 bool async_unlinking:1; 151 bool shutdown:1; 152 struct ehci_qh *qh_scan_next; 153 154 /* async schedule support */ 155 struct ehci_qh *async; 156 struct ehci_qh *dummy; /* For AMD quirk use */ 157 struct list_head async_unlink; 158 struct list_head async_idle; 159 unsigned async_unlink_cycle; 160 unsigned async_count; /* async activity count */ 161 __hc32 old_current; /* Test for QH becoming */ 162 __hc32 old_token; /* inactive during unlink */ 163 164 /* periodic schedule support */ 165 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 166 unsigned periodic_size; 167 __hc32 *periodic; /* hw periodic table */ 168 dma_addr_t periodic_dma; 169 struct list_head intr_qh_list; 170 unsigned i_thresh; /* uframes HC might cache */ 171 172 union ehci_shadow *pshadow; /* mirror hw periodic table */ 173 struct list_head intr_unlink_wait; 174 struct list_head intr_unlink; 175 unsigned intr_unlink_wait_cycle; 176 unsigned intr_unlink_cycle; 177 unsigned now_frame; /* frame from HC hardware */ 178 unsigned last_iso_frame; /* last frame scanned for iso */ 179 unsigned intr_count; /* intr activity count */ 180 unsigned isoc_count; /* isoc activity count */ 181 unsigned periodic_count; /* periodic activity count */ 182 unsigned uframe_periodic_max; /* max periodic time per uframe */ 183 184 185 /* list of itds & sitds completed while now_frame was still active */ 186 struct list_head cached_itd_list; 187 struct ehci_itd *last_itd_to_free; 188 struct list_head cached_sitd_list; 189 struct ehci_sitd *last_sitd_to_free; 190 191 /* per root hub port */ 192 unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; 193 194 /* bit vectors (one bit per port) */ 195 unsigned long bus_suspended; /* which ports were 196 already suspended at the start of a bus suspend */ 197 unsigned long companion_ports; /* which ports are 198 dedicated to the companion controller */ 199 unsigned long owned_ports; /* which ports are 200 owned by the companion during a bus suspend */ 201 unsigned long port_c_suspend; /* which ports have 202 the change-suspend feature turned on */ 203 unsigned long suspended_ports; /* which ports are 204 suspended */ 205 unsigned long resuming_ports; /* which ports have 206 started to resume */ 207 208 /* per-HC memory pools (could be per-bus, but ...) */ 209 struct dma_pool *qh_pool; /* qh per active urb */ 210 struct dma_pool *qtd_pool; /* one or more per qh */ 211 struct dma_pool *itd_pool; /* itd per iso urb */ 212 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 213 214 unsigned random_frame; 215 unsigned long next_statechange; 216 ktime_t last_periodic_enable; 217 u32 command; 218 219 /* SILICON QUIRKS */ 220 unsigned no_selective_suspend:1; 221 unsigned has_fsl_port_bug:1; /* FreeScale */ 222 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ 223 unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ 224 unsigned big_endian_mmio:1; 225 unsigned big_endian_desc:1; 226 unsigned big_endian_capbase:1; 227 unsigned has_amcc_usb23:1; 228 unsigned need_io_watchdog:1; 229 unsigned amd_pll_fix:1; 230 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 231 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 232 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 233 unsigned need_oc_pp_cycle:1; /* MPC834X port power */ 234 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ 235 236 /* required for usb32 quirk */ 237 #define OHCI_CTRL_HCFS (3 << 6) 238 #define OHCI_USB_OPER (2 << 6) 239 #define OHCI_USB_SUSPEND (3 << 6) 240 241 #define OHCI_HCCTRL_OFFSET 0x4 242 #define OHCI_HCCTRL_LEN 0x4 243 __hc32 *ohci_hcctrl_reg; 244 unsigned has_hostpc:1; 245 unsigned has_tdi_phy_lpm:1; 246 unsigned has_ppcd:1; /* support per-port change bits */ 247 u8 sbrn; /* packed release number */ 248 249 /* irq statistics */ 250 #ifdef EHCI_STATS 251 struct ehci_stats stats; 252 # define COUNT(x) ((x)++) 253 #else 254 # define COUNT(x) 255 #endif 256 257 /* debug files */ 258 #ifdef CONFIG_DYNAMIC_DEBUG 259 struct dentry *debug_dir; 260 #endif 261 262 /* bandwidth usage */ 263 #define EHCI_BANDWIDTH_SIZE 64 264 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) 265 u8 bandwidth[EHCI_BANDWIDTH_SIZE]; 266 /* us allocated per uframe */ 267 u8 tt_budget[EHCI_BANDWIDTH_SIZE]; 268 /* us budgeted per uframe */ 269 struct list_head tt_list; 270 271 /* platform-specific data -- must come last */ 272 unsigned long priv[0] __aligned(sizeof(s64)); 273 }; 274 275 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 276 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd) 277 { 278 return (struct ehci_hcd *) (hcd->hcd_priv); 279 } 280 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) 281 { 282 return container_of((void *) ehci, struct usb_hcd, hcd_priv); 283 } 284 285 /*-------------------------------------------------------------------------*/ 286 287 #include <linux/usb/ehci_def.h> 288 289 /*-------------------------------------------------------------------------*/ 290 291 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 292 293 /* 294 * EHCI Specification 0.95 Section 3.5 295 * QTD: describe data transfer components (buffer, direction, ...) 296 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 297 * 298 * These are associated only with "QH" (Queue Head) structures, 299 * used with control, bulk, and interrupt transfers. 300 */ 301 struct ehci_qtd { 302 /* first part defined by EHCI spec */ 303 __hc32 hw_next; /* see EHCI 3.5.1 */ 304 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 305 __hc32 hw_token; /* see EHCI 3.5.3 */ 306 #define QTD_TOGGLE (1 << 31) /* data toggle */ 307 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 308 #define QTD_IOC (1 << 15) /* interrupt on complete */ 309 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 310 #define QTD_PID(tok) (((tok)>>8) & 0x3) 311 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 312 #define QTD_STS_HALT (1 << 6) /* halted on error */ 313 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 314 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 315 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 316 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 317 #define QTD_STS_STS (1 << 1) /* split transaction state */ 318 #define QTD_STS_PING (1 << 0) /* issue PING? */ 319 320 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 321 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 322 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 323 324 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ 325 __hc32 hw_buf_hi[5]; /* Appendix B */ 326 327 /* the rest is HCD-private */ 328 dma_addr_t qtd_dma; /* qtd address */ 329 struct list_head qtd_list; /* sw qtd list */ 330 struct urb *urb; /* qtd's urb */ 331 size_t length; /* length of buffer */ 332 } __aligned(32); 333 334 /* mask NakCnt+T in qh->hw_alt_next */ 335 #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f) 336 337 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) 338 339 /*-------------------------------------------------------------------------*/ 340 341 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 342 #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 343 344 /* 345 * Now the following defines are not converted using the 346 * cpu_to_le32() macro anymore, since we have to support 347 * "dynamic" switching between be and le support, so that the driver 348 * can be used on one system with SoC EHCI controller using big-endian 349 * descriptors as well as a normal little-endian PCI EHCI controller. 350 */ 351 /* values for that type tag */ 352 #define Q_TYPE_ITD (0 << 1) 353 #define Q_TYPE_QH (1 << 1) 354 #define Q_TYPE_SITD (2 << 1) 355 #define Q_TYPE_FSTN (3 << 1) 356 357 /* next async queue entry, or pointer to interrupt/periodic QH */ 358 #define QH_NEXT(ehci, dma) \ 359 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH)) 360 361 /* for periodic/async schedules and qtd lists, mark end of list */ 362 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 363 364 /* 365 * Entries in periodic shadow table are pointers to one of four kinds 366 * of data structure. That's dictated by the hardware; a type tag is 367 * encoded in the low bits of the hardware's periodic schedule. Use 368 * Q_NEXT_TYPE to get the tag. 369 * 370 * For entries in the async schedule, the type tag always says "qh". 371 */ 372 union ehci_shadow { 373 struct ehci_qh *qh; /* Q_TYPE_QH */ 374 struct ehci_itd *itd; /* Q_TYPE_ITD */ 375 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 376 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 377 __hc32 *hw_next; /* (all types) */ 378 void *ptr; 379 }; 380 381 /*-------------------------------------------------------------------------*/ 382 383 /* 384 * EHCI Specification 0.95 Section 3.6 385 * QH: describes control/bulk/interrupt endpoints 386 * See Fig 3-7 "Queue Head Structure Layout". 387 * 388 * These appear in both the async and (for interrupt) periodic schedules. 389 */ 390 391 /* first part defined by EHCI spec */ 392 struct ehci_qh_hw { 393 __hc32 hw_next; /* see EHCI 3.6.1 */ 394 __hc32 hw_info1; /* see EHCI 3.6.2 */ 395 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 396 #define QH_HEAD (1 << 15) /* Head of async reclamation list */ 397 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 398 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 399 #define QH_LOW_SPEED (1 << 12) 400 #define QH_FULL_SPEED (0 << 12) 401 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 402 __hc32 hw_info2; /* see EHCI 3.6.2 */ 403 #define QH_SMASK 0x000000ff 404 #define QH_CMASK 0x0000ff00 405 #define QH_HUBADDR 0x007f0000 406 #define QH_HUBPORT 0x3f800000 407 #define QH_MULT 0xc0000000 408 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 409 410 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 411 __hc32 hw_qtd_next; 412 __hc32 hw_alt_next; 413 __hc32 hw_token; 414 __hc32 hw_buf[5]; 415 __hc32 hw_buf_hi[5]; 416 } __aligned(32); 417 418 struct ehci_qh { 419 struct ehci_qh_hw *hw; /* Must come first */ 420 /* the rest is HCD-private */ 421 dma_addr_t qh_dma; /* address of qh */ 422 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 423 struct list_head qtd_list; /* sw qtd list */ 424 struct list_head intr_node; /* list of intr QHs */ 425 struct ehci_qtd *dummy; 426 struct list_head unlink_node; 427 struct ehci_per_sched ps; /* scheduling info */ 428 429 unsigned unlink_cycle; 430 431 u8 qh_state; 432 #define QH_STATE_LINKED 1 /* HC sees this */ 433 #define QH_STATE_UNLINK 2 /* HC may still see this */ 434 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 435 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 436 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 437 438 u8 xacterrs; /* XactErr retry counter */ 439 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 440 441 u8 unlink_reason; 442 #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ 443 #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ 444 #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ 445 #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ 446 #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ 447 #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ 448 449 u8 gap_uf; /* uframes split/csplit gap */ 450 451 unsigned is_out:1; /* bulk or intr OUT */ 452 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 453 unsigned dequeue_during_giveback:1; 454 unsigned should_be_inactive:1; 455 }; 456 457 /*-------------------------------------------------------------------------*/ 458 459 /* description of one iso transaction (up to 3 KB data if highspeed) */ 460 struct ehci_iso_packet { 461 /* These will be copied to iTD when scheduling */ 462 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 463 __hc32 transaction; /* itd->hw_transaction[i] |= */ 464 u8 cross; /* buf crosses pages */ 465 /* for full speed OUT splits */ 466 u32 buf1; 467 }; 468 469 /* temporary schedule data for packets from iso urbs (both speeds) 470 * each packet is one logical usb transaction to the device (not TT), 471 * beginning at stream->next_uframe 472 */ 473 struct ehci_iso_sched { 474 struct list_head td_list; 475 unsigned span; 476 unsigned first_packet; 477 struct ehci_iso_packet packet[0]; 478 }; 479 480 /* 481 * ehci_iso_stream - groups all (s)itds for this endpoint. 482 * acts like a qh would, if EHCI had them for ISO. 483 */ 484 struct ehci_iso_stream { 485 /* first field matches ehci_hq, but is NULL */ 486 struct ehci_qh_hw *hw; 487 488 u8 bEndpointAddress; 489 u8 highspeed; 490 struct list_head td_list; /* queued itds/sitds */ 491 struct list_head free_list; /* list of unused itds/sitds */ 492 493 /* output of (re)scheduling */ 494 struct ehci_per_sched ps; /* scheduling info */ 495 unsigned next_uframe; 496 __hc32 splits; 497 498 /* the rest is derived from the endpoint descriptor, 499 * including the extra info for hw_bufp[0..2] 500 */ 501 u16 uperiod; /* period in uframes */ 502 u16 maxp; 503 unsigned bandwidth; 504 505 /* This is used to initialize iTD's hw_bufp fields */ 506 __hc32 buf0; 507 __hc32 buf1; 508 __hc32 buf2; 509 510 /* this is used to initialize sITD's tt info */ 511 __hc32 address; 512 }; 513 514 /*-------------------------------------------------------------------------*/ 515 516 /* 517 * EHCI Specification 0.95 Section 3.3 518 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 519 * 520 * Schedule records for high speed iso xfers 521 */ 522 struct ehci_itd { 523 /* first part defined by EHCI spec */ 524 __hc32 hw_next; /* see EHCI 3.3.1 */ 525 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ 526 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 527 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 528 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 529 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 530 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 531 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 532 533 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 534 535 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ 536 __hc32 hw_bufp_hi[7]; /* Appendix B */ 537 538 /* the rest is HCD-private */ 539 dma_addr_t itd_dma; /* for this itd */ 540 union ehci_shadow itd_next; /* ptr to periodic q entry */ 541 542 struct urb *urb; 543 struct ehci_iso_stream *stream; /* endpoint's queue */ 544 struct list_head itd_list; /* list of stream's itds */ 545 546 /* any/all hw_transactions here may be used by that urb */ 547 unsigned frame; /* where scheduled */ 548 unsigned pg; 549 unsigned index[8]; /* in urb->iso_frame_desc */ 550 } __aligned(32); 551 552 /*-------------------------------------------------------------------------*/ 553 554 /* 555 * EHCI Specification 0.95 Section 3.4 556 * siTD, aka split-transaction isochronous Transfer Descriptor 557 * ... describe full speed iso xfers through TT in hubs 558 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 559 */ 560 struct ehci_sitd { 561 /* first part defined by EHCI spec */ 562 __hc32 hw_next; 563 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 564 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 565 __hc32 hw_uframe; /* EHCI table 3-10 */ 566 __hc32 hw_results; /* EHCI table 3-11 */ 567 #define SITD_IOC (1 << 31) /* interrupt on completion */ 568 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 569 #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff) 570 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 571 #define SITD_STS_ERR (1 << 6) /* error from TT */ 572 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 573 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 574 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 575 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 576 #define SITD_STS_STS (1 << 1) /* split transaction state */ 577 578 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 579 580 __hc32 hw_buf[2]; /* EHCI table 3-12 */ 581 __hc32 hw_backpointer; /* EHCI table 3-13 */ 582 __hc32 hw_buf_hi[2]; /* Appendix B */ 583 584 /* the rest is HCD-private */ 585 dma_addr_t sitd_dma; 586 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 587 588 struct urb *urb; 589 struct ehci_iso_stream *stream; /* endpoint's queue */ 590 struct list_head sitd_list; /* list of stream's sitds */ 591 unsigned frame; 592 unsigned index; 593 } __aligned(32); 594 595 /*-------------------------------------------------------------------------*/ 596 597 /* 598 * EHCI Specification 0.96 Section 3.7 599 * Periodic Frame Span Traversal Node (FSTN) 600 * 601 * Manages split interrupt transactions (using TT) that span frame boundaries 602 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 603 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 604 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 605 */ 606 struct ehci_fstn { 607 __hc32 hw_next; /* any periodic q entry */ 608 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 609 610 /* the rest is HCD-private */ 611 dma_addr_t fstn_dma; 612 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 613 } __aligned(32); 614 615 /*-------------------------------------------------------------------------*/ 616 617 /* 618 * USB-2.0 Specification Sections 11.14 and 11.18 619 * Scheduling and budgeting split transactions using TTs 620 * 621 * A hub can have a single TT for all its ports, or multiple TTs (one for each 622 * port). The bandwidth and budgeting information for the full/low-speed bus 623 * below each TT is self-contained and independent of the other TTs or the 624 * high-speed bus. 625 * 626 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated 627 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to 628 * the best-case estimate of the number of full-speed bytes allocated to an 629 * endpoint for each microframe within an allocated frame. 630 * 631 * Removal of an endpoint invalidates a TT's budget. Instead of trying to 632 * keep an up-to-date record, we recompute the budget when it is needed. 633 */ 634 635 struct ehci_tt { 636 u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; 637 638 struct list_head tt_list; /* List of all ehci_tt's */ 639 struct list_head ps_list; /* Items using this TT */ 640 struct usb_tt *usb_tt; 641 int tt_port; /* TT port number */ 642 }; 643 644 /*-------------------------------------------------------------------------*/ 645 646 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 647 648 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 649 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup) 650 651 #define ehci_prepare_ports_for_controller_resume(ehci) \ 652 ehci_adjust_port_wakeup_flags(ehci, false, false) 653 654 /*-------------------------------------------------------------------------*/ 655 656 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 657 658 /* 659 * Some EHCI controllers have a Transaction Translator built into the 660 * root hub. This is a non-standard feature. Each controller will need 661 * to add code to the following inline functions, and call them as 662 * needed (mostly in root hub code). 663 */ 664 665 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 666 667 /* Returns the speed of a device attached to a port on the root hub. */ 668 static inline unsigned int 669 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 670 { 671 if (ehci_is_TDI(ehci)) { 672 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 673 case 0: 674 return 0; 675 case 1: 676 return USB_PORT_STAT_LOW_SPEED; 677 case 2: 678 default: 679 return USB_PORT_STAT_HIGH_SPEED; 680 } 681 } 682 return USB_PORT_STAT_HIGH_SPEED; 683 } 684 685 #else 686 687 #define ehci_is_TDI(e) (0) 688 689 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 690 #endif 691 692 /*-------------------------------------------------------------------------*/ 693 694 #ifdef CONFIG_PPC_83xx 695 /* Some Freescale processors have an erratum in which the TT 696 * port number in the queue head was 0..N-1 instead of 1..N. 697 */ 698 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 699 #else 700 #define ehci_has_fsl_portno_bug(e) (0) 701 #endif 702 703 #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */ 704 705 #if defined(CONFIG_PPC_85xx) 706 /* Some Freescale processors have an erratum (USB A-005275) in which 707 * incoming packets get corrupted in HS mode 708 */ 709 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata) 710 #else 711 #define ehci_has_fsl_hs_errata(e) (0) 712 #endif 713 714 /* 715 * Some Freescale/NXP processors have an erratum (USB A-005697) 716 * in which we need to wait for 10ms for bus to enter suspend mode 717 * after setting SUSP bit. 718 */ 719 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata) 720 721 /* 722 * While most USB host controllers implement their registers in 723 * little-endian format, a minority (celleb companion chip) implement 724 * them in big endian format. 725 * 726 * This attempts to support either format at compile time without a 727 * runtime penalty, or both formats with the additional overhead 728 * of checking a flag bit. 729 * 730 * ehci_big_endian_capbase is a special quirk for controllers that 731 * implement the HC capability registers as separate registers and not 732 * as fields of a 32-bit register. 733 */ 734 735 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 736 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 737 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 738 #else 739 #define ehci_big_endian_mmio(e) 0 740 #define ehci_big_endian_capbase(e) 0 741 #endif 742 743 /* 744 * Big-endian read/write functions are arch-specific. 745 * Other arches can be added if/when they're needed. 746 */ 747 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 748 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 749 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 750 #endif 751 752 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 753 __u32 __iomem *regs) 754 { 755 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 756 return ehci_big_endian_mmio(ehci) ? 757 readl_be(regs) : 758 readl(regs); 759 #else 760 return readl(regs); 761 #endif 762 } 763 764 #ifdef CONFIG_SOC_IMX28 765 static inline void imx28_ehci_writel(const unsigned int val, 766 volatile __u32 __iomem *addr) 767 { 768 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 769 } 770 #else 771 static inline void imx28_ehci_writel(const unsigned int val, 772 volatile __u32 __iomem *addr) 773 { 774 } 775 #endif 776 static inline void ehci_writel(const struct ehci_hcd *ehci, 777 const unsigned int val, __u32 __iomem *regs) 778 { 779 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 780 ehci_big_endian_mmio(ehci) ? 781 writel_be(val, regs) : 782 writel(val, regs); 783 #else 784 if (ehci->imx28_write_fix) 785 imx28_ehci_writel(val, regs); 786 else 787 writel(val, regs); 788 #endif 789 } 790 791 /* 792 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 793 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 794 * Other common bits are dependent on has_amcc_usb23 quirk flag. 795 */ 796 #ifdef CONFIG_44x 797 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 798 { 799 u32 hc_control; 800 801 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 802 if (operational) 803 hc_control |= OHCI_USB_OPER; 804 else 805 hc_control |= OHCI_USB_SUSPEND; 806 807 writel_be(hc_control, ehci->ohci_hcctrl_reg); 808 (void) readl_be(ehci->ohci_hcctrl_reg); 809 } 810 #else 811 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 812 { } 813 #endif 814 815 /*-------------------------------------------------------------------------*/ 816 817 /* 818 * The AMCC 440EPx not only implements its EHCI registers in big-endian 819 * format, but also its DMA data structures (descriptors). 820 * 821 * EHCI controllers accessed through PCI work normally (little-endian 822 * everywhere), so we won't bother supporting a BE-only mode for now. 823 */ 824 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 825 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 826 827 /* cpu to ehci */ 828 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) 829 { 830 return ehci_big_endian_desc(ehci) 831 ? (__force __hc32)cpu_to_be32(x) 832 : (__force __hc32)cpu_to_le32(x); 833 } 834 835 /* ehci to cpu */ 836 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) 837 { 838 return ehci_big_endian_desc(ehci) 839 ? be32_to_cpu((__force __be32)x) 840 : le32_to_cpu((__force __le32)x); 841 } 842 843 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) 844 { 845 return ehci_big_endian_desc(ehci) 846 ? be32_to_cpup((__force __be32 *)x) 847 : le32_to_cpup((__force __le32 *)x); 848 } 849 850 #else 851 852 /* cpu to ehci */ 853 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) 854 { 855 return cpu_to_le32(x); 856 } 857 858 /* ehci to cpu */ 859 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) 860 { 861 return le32_to_cpu(x); 862 } 863 864 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) 865 { 866 return le32_to_cpup(x); 867 } 868 869 #endif 870 871 /*-------------------------------------------------------------------------*/ 872 873 #define ehci_dbg(ehci, fmt, args...) \ 874 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 875 #define ehci_err(ehci, fmt, args...) \ 876 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 877 #define ehci_info(ehci, fmt, args...) \ 878 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 879 #define ehci_warn(ehci, fmt, args...) \ 880 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args) 881 882 /*-------------------------------------------------------------------------*/ 883 884 /* Declarations of things exported for use by ehci platform drivers */ 885 886 struct ehci_driver_overrides { 887 size_t extra_priv_size; 888 int (*reset)(struct usb_hcd *hcd); 889 int (*port_power)(struct usb_hcd *hcd, 890 int portnum, bool enable); 891 }; 892 893 extern void ehci_init_driver(struct hc_driver *drv, 894 const struct ehci_driver_overrides *over); 895 extern int ehci_setup(struct usb_hcd *hcd); 896 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 897 u32 mask, u32 done, int usec); 898 extern int ehci_reset(struct ehci_hcd *ehci); 899 900 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 901 extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); 902 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, 903 bool suspending, bool do_wakeup); 904 905 extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 906 u16 wIndex, char *buf, u16 wLength); 907 908 #endif /* __LINUX_EHCI_HCD_H */ 909