1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* per root hub port */ 91 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 92 93 /* bit vectors (one bit per port) */ 94 unsigned long bus_suspended; /* which ports were 95 already suspended at the start of a bus suspend */ 96 unsigned long companion_ports; /* which ports are 97 dedicated to the companion controller */ 98 unsigned long owned_ports; /* which ports are 99 owned by the companion during a bus suspend */ 100 unsigned long port_c_suspend; /* which ports have 101 the change-suspend feature turned on */ 102 unsigned long suspended_ports; /* which ports are 103 suspended */ 104 105 /* per-HC memory pools (could be per-bus, but ...) */ 106 struct dma_pool *qh_pool; /* qh per active urb */ 107 struct dma_pool *qtd_pool; /* one or more per qh */ 108 struct dma_pool *itd_pool; /* itd per iso urb */ 109 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 110 111 struct timer_list iaa_watchdog; 112 struct timer_list watchdog; 113 unsigned long actions; 114 unsigned stamp; 115 unsigned long next_statechange; 116 u32 command; 117 118 /* SILICON QUIRKS */ 119 unsigned no_selective_suspend:1; 120 unsigned has_fsl_port_bug:1; /* FreeScale */ 121 unsigned big_endian_mmio:1; 122 unsigned big_endian_desc:1; 123 unsigned has_amcc_usb23:1; 124 125 /* required for usb32 quirk */ 126 #define OHCI_CTRL_HCFS (3 << 6) 127 #define OHCI_USB_OPER (2 << 6) 128 #define OHCI_USB_SUSPEND (3 << 6) 129 130 #define OHCI_HCCTRL_OFFSET 0x4 131 #define OHCI_HCCTRL_LEN 0x4 132 __hc32 *ohci_hcctrl_reg; 133 134 u8 sbrn; /* packed release number */ 135 136 /* irq statistics */ 137 #ifdef EHCI_STATS 138 struct ehci_stats stats; 139 # define COUNT(x) do { (x)++; } while (0) 140 #else 141 # define COUNT(x) do {} while (0) 142 #endif 143 144 /* debug files */ 145 #ifdef DEBUG 146 struct dentry *debug_dir; 147 struct dentry *debug_async; 148 struct dentry *debug_periodic; 149 struct dentry *debug_registers; 150 #endif 151 }; 152 153 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 154 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 155 { 156 return (struct ehci_hcd *) (hcd->hcd_priv); 157 } 158 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 159 { 160 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 161 } 162 163 164 static inline void 165 iaa_watchdog_start(struct ehci_hcd *ehci) 166 { 167 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 168 mod_timer(&ehci->iaa_watchdog, 169 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 170 } 171 172 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 173 { 174 del_timer(&ehci->iaa_watchdog); 175 } 176 177 enum ehci_timer_action { 178 TIMER_IO_WATCHDOG, 179 TIMER_ASYNC_SHRINK, 180 TIMER_ASYNC_OFF, 181 }; 182 183 static inline void 184 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 185 { 186 clear_bit (action, &ehci->actions); 187 } 188 189 static inline void 190 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 191 { 192 /* Don't override timeouts which shrink or (later) disable 193 * the async ring; just the I/O watchdog. Note that if a 194 * SHRINK were pending, OFF would never be requested. 195 */ 196 if (timer_pending(&ehci->watchdog) 197 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 198 & ehci->actions)) 199 return; 200 201 if (!test_and_set_bit (action, &ehci->actions)) { 202 unsigned long t; 203 204 switch (action) { 205 case TIMER_IO_WATCHDOG: 206 t = EHCI_IO_JIFFIES; 207 break; 208 case TIMER_ASYNC_OFF: 209 t = EHCI_ASYNC_JIFFIES; 210 break; 211 // case TIMER_ASYNC_SHRINK: 212 default: 213 /* add a jiffie since we synch against the 214 * 8 KHz uframe counter. 215 */ 216 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 217 break; 218 } 219 mod_timer(&ehci->watchdog, t + jiffies); 220 } 221 } 222 223 /*-------------------------------------------------------------------------*/ 224 225 #include <linux/usb/ehci_def.h> 226 227 /*-------------------------------------------------------------------------*/ 228 229 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 230 231 /* 232 * EHCI Specification 0.95 Section 3.5 233 * QTD: describe data transfer components (buffer, direction, ...) 234 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 235 * 236 * These are associated only with "QH" (Queue Head) structures, 237 * used with control, bulk, and interrupt transfers. 238 */ 239 struct ehci_qtd { 240 /* first part defined by EHCI spec */ 241 __hc32 hw_next; /* see EHCI 3.5.1 */ 242 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 243 __hc32 hw_token; /* see EHCI 3.5.3 */ 244 #define QTD_TOGGLE (1 << 31) /* data toggle */ 245 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 246 #define QTD_IOC (1 << 15) /* interrupt on complete */ 247 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 248 #define QTD_PID(tok) (((tok)>>8) & 0x3) 249 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 250 #define QTD_STS_HALT (1 << 6) /* halted on error */ 251 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 252 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 253 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 254 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 255 #define QTD_STS_STS (1 << 1) /* split transaction state */ 256 #define QTD_STS_PING (1 << 0) /* issue PING? */ 257 258 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 259 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 260 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 261 262 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 263 __hc32 hw_buf_hi [5]; /* Appendix B */ 264 265 /* the rest is HCD-private */ 266 dma_addr_t qtd_dma; /* qtd address */ 267 struct list_head qtd_list; /* sw qtd list */ 268 struct urb *urb; /* qtd's urb */ 269 size_t length; /* length of buffer */ 270 } __attribute__ ((aligned (32))); 271 272 /* mask NakCnt+T in qh->hw_alt_next */ 273 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 274 275 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 276 277 /*-------------------------------------------------------------------------*/ 278 279 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 280 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 281 282 /* 283 * Now the following defines are not converted using the 284 * __constant_cpu_to_le32() macro anymore, since we have to support 285 * "dynamic" switching between be and le support, so that the driver 286 * can be used on one system with SoC EHCI controller using big-endian 287 * descriptors as well as a normal little-endian PCI EHCI controller. 288 */ 289 /* values for that type tag */ 290 #define Q_TYPE_ITD (0 << 1) 291 #define Q_TYPE_QH (1 << 1) 292 #define Q_TYPE_SITD (2 << 1) 293 #define Q_TYPE_FSTN (3 << 1) 294 295 /* next async queue entry, or pointer to interrupt/periodic QH */ 296 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 297 298 /* for periodic/async schedules and qtd lists, mark end of list */ 299 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 300 301 /* 302 * Entries in periodic shadow table are pointers to one of four kinds 303 * of data structure. That's dictated by the hardware; a type tag is 304 * encoded in the low bits of the hardware's periodic schedule. Use 305 * Q_NEXT_TYPE to get the tag. 306 * 307 * For entries in the async schedule, the type tag always says "qh". 308 */ 309 union ehci_shadow { 310 struct ehci_qh *qh; /* Q_TYPE_QH */ 311 struct ehci_itd *itd; /* Q_TYPE_ITD */ 312 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 313 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 314 __hc32 *hw_next; /* (all types) */ 315 void *ptr; 316 }; 317 318 /*-------------------------------------------------------------------------*/ 319 320 /* 321 * EHCI Specification 0.95 Section 3.6 322 * QH: describes control/bulk/interrupt endpoints 323 * See Fig 3-7 "Queue Head Structure Layout". 324 * 325 * These appear in both the async and (for interrupt) periodic schedules. 326 */ 327 328 struct ehci_qh { 329 /* first part defined by EHCI spec */ 330 __hc32 hw_next; /* see EHCI 3.6.1 */ 331 __hc32 hw_info1; /* see EHCI 3.6.2 */ 332 #define QH_HEAD 0x00008000 333 __hc32 hw_info2; /* see EHCI 3.6.2 */ 334 #define QH_SMASK 0x000000ff 335 #define QH_CMASK 0x0000ff00 336 #define QH_HUBADDR 0x007f0000 337 #define QH_HUBPORT 0x3f800000 338 #define QH_MULT 0xc0000000 339 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 340 341 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 342 __hc32 hw_qtd_next; 343 __hc32 hw_alt_next; 344 __hc32 hw_token; 345 __hc32 hw_buf [5]; 346 __hc32 hw_buf_hi [5]; 347 348 /* the rest is HCD-private */ 349 dma_addr_t qh_dma; /* address of qh */ 350 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 351 struct list_head qtd_list; /* sw qtd list */ 352 struct ehci_qtd *dummy; 353 struct ehci_qh *reclaim; /* next to reclaim */ 354 355 struct ehci_hcd *ehci; 356 357 /* 358 * Do NOT use atomic operations for QH refcounting. On some CPUs 359 * (PPC7448 for example), atomic operations cannot be performed on 360 * memory that is cache-inhibited (i.e. being used for DMA). 361 * Spinlocks are used to protect all QH fields. 362 */ 363 u32 refcount; 364 unsigned stamp; 365 366 u8 qh_state; 367 #define QH_STATE_LINKED 1 /* HC sees this */ 368 #define QH_STATE_UNLINK 2 /* HC may still see this */ 369 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 370 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 371 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 372 373 /* periodic schedule info */ 374 u8 usecs; /* intr bandwidth */ 375 u8 gap_uf; /* uframes split/csplit gap */ 376 u8 c_usecs; /* ... split completion bw */ 377 u16 tt_usecs; /* tt downstream bandwidth */ 378 unsigned short period; /* polling interval */ 379 unsigned short start; /* where polling starts */ 380 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 381 struct usb_device *dev; /* access to TT */ 382 } __attribute__ ((aligned (32))); 383 384 /*-------------------------------------------------------------------------*/ 385 386 /* description of one iso transaction (up to 3 KB data if highspeed) */ 387 struct ehci_iso_packet { 388 /* These will be copied to iTD when scheduling */ 389 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 390 __hc32 transaction; /* itd->hw_transaction[i] |= */ 391 u8 cross; /* buf crosses pages */ 392 /* for full speed OUT splits */ 393 u32 buf1; 394 }; 395 396 /* temporary schedule data for packets from iso urbs (both speeds) 397 * each packet is one logical usb transaction to the device (not TT), 398 * beginning at stream->next_uframe 399 */ 400 struct ehci_iso_sched { 401 struct list_head td_list; 402 unsigned span; 403 struct ehci_iso_packet packet [0]; 404 }; 405 406 /* 407 * ehci_iso_stream - groups all (s)itds for this endpoint. 408 * acts like a qh would, if EHCI had them for ISO. 409 */ 410 struct ehci_iso_stream { 411 /* first two fields match QH, but info1 == 0 */ 412 __hc32 hw_next; 413 __hc32 hw_info1; 414 415 u32 refcount; 416 u8 bEndpointAddress; 417 u8 highspeed; 418 u16 depth; /* depth in uframes */ 419 struct list_head td_list; /* queued itds/sitds */ 420 struct list_head free_list; /* list of unused itds/sitds */ 421 struct usb_device *udev; 422 struct usb_host_endpoint *ep; 423 424 /* output of (re)scheduling */ 425 unsigned long start; /* jiffies */ 426 unsigned long rescheduled; 427 int next_uframe; 428 __hc32 splits; 429 430 /* the rest is derived from the endpoint descriptor, 431 * trusting urb->interval == f(epdesc->bInterval) and 432 * including the extra info for hw_bufp[0..2] 433 */ 434 u8 usecs, c_usecs; 435 u16 interval; 436 u16 tt_usecs; 437 u16 maxp; 438 u16 raw_mask; 439 unsigned bandwidth; 440 441 /* This is used to initialize iTD's hw_bufp fields */ 442 __hc32 buf0; 443 __hc32 buf1; 444 __hc32 buf2; 445 446 /* this is used to initialize sITD's tt info */ 447 __hc32 address; 448 }; 449 450 /*-------------------------------------------------------------------------*/ 451 452 /* 453 * EHCI Specification 0.95 Section 3.3 454 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 455 * 456 * Schedule records for high speed iso xfers 457 */ 458 struct ehci_itd { 459 /* first part defined by EHCI spec */ 460 __hc32 hw_next; /* see EHCI 3.3.1 */ 461 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 462 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 463 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 464 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 465 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 466 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 467 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 468 469 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 470 471 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 472 __hc32 hw_bufp_hi [7]; /* Appendix B */ 473 474 /* the rest is HCD-private */ 475 dma_addr_t itd_dma; /* for this itd */ 476 union ehci_shadow itd_next; /* ptr to periodic q entry */ 477 478 struct urb *urb; 479 struct ehci_iso_stream *stream; /* endpoint's queue */ 480 struct list_head itd_list; /* list of stream's itds */ 481 482 /* any/all hw_transactions here may be used by that urb */ 483 unsigned frame; /* where scheduled */ 484 unsigned pg; 485 unsigned index[8]; /* in urb->iso_frame_desc */ 486 } __attribute__ ((aligned (32))); 487 488 /*-------------------------------------------------------------------------*/ 489 490 /* 491 * EHCI Specification 0.95 Section 3.4 492 * siTD, aka split-transaction isochronous Transfer Descriptor 493 * ... describe full speed iso xfers through TT in hubs 494 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 495 */ 496 struct ehci_sitd { 497 /* first part defined by EHCI spec */ 498 __hc32 hw_next; 499 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 500 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 501 __hc32 hw_uframe; /* EHCI table 3-10 */ 502 __hc32 hw_results; /* EHCI table 3-11 */ 503 #define SITD_IOC (1 << 31) /* interrupt on completion */ 504 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 505 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 506 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 507 #define SITD_STS_ERR (1 << 6) /* error from TT */ 508 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 509 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 510 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 511 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 512 #define SITD_STS_STS (1 << 1) /* split transaction state */ 513 514 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 515 516 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 517 __hc32 hw_backpointer; /* EHCI table 3-13 */ 518 __hc32 hw_buf_hi [2]; /* Appendix B */ 519 520 /* the rest is HCD-private */ 521 dma_addr_t sitd_dma; 522 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 523 524 struct urb *urb; 525 struct ehci_iso_stream *stream; /* endpoint's queue */ 526 struct list_head sitd_list; /* list of stream's sitds */ 527 unsigned frame; 528 unsigned index; 529 } __attribute__ ((aligned (32))); 530 531 /*-------------------------------------------------------------------------*/ 532 533 /* 534 * EHCI Specification 0.96 Section 3.7 535 * Periodic Frame Span Traversal Node (FSTN) 536 * 537 * Manages split interrupt transactions (using TT) that span frame boundaries 538 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 539 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 540 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 541 */ 542 struct ehci_fstn { 543 __hc32 hw_next; /* any periodic q entry */ 544 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 545 546 /* the rest is HCD-private */ 547 dma_addr_t fstn_dma; 548 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 549 } __attribute__ ((aligned (32))); 550 551 /*-------------------------------------------------------------------------*/ 552 553 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 554 555 /* 556 * Some EHCI controllers have a Transaction Translator built into the 557 * root hub. This is a non-standard feature. Each controller will need 558 * to add code to the following inline functions, and call them as 559 * needed (mostly in root hub code). 560 */ 561 562 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 563 564 /* Returns the speed of a device attached to a port on the root hub. */ 565 static inline unsigned int 566 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 567 { 568 if (ehci_is_TDI(ehci)) { 569 switch ((portsc>>26)&3) { 570 case 0: 571 return 0; 572 case 1: 573 return (1<<USB_PORT_FEAT_LOWSPEED); 574 case 2: 575 default: 576 return (1<<USB_PORT_FEAT_HIGHSPEED); 577 } 578 } 579 return (1<<USB_PORT_FEAT_HIGHSPEED); 580 } 581 582 #else 583 584 #define ehci_is_TDI(e) (0) 585 586 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 587 #endif 588 589 /*-------------------------------------------------------------------------*/ 590 591 #ifdef CONFIG_PPC_83xx 592 /* Some Freescale processors have an erratum in which the TT 593 * port number in the queue head was 0..N-1 instead of 1..N. 594 */ 595 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 596 #else 597 #define ehci_has_fsl_portno_bug(e) (0) 598 #endif 599 600 /* 601 * While most USB host controllers implement their registers in 602 * little-endian format, a minority (celleb companion chip) implement 603 * them in big endian format. 604 * 605 * This attempts to support either format at compile time without a 606 * runtime penalty, or both formats with the additional overhead 607 * of checking a flag bit. 608 */ 609 610 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 611 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 612 #else 613 #define ehci_big_endian_mmio(e) 0 614 #endif 615 616 /* 617 * Big-endian read/write functions are arch-specific. 618 * Other arches can be added if/when they're needed. 619 */ 620 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 621 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 622 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 623 #endif 624 625 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 626 __u32 __iomem * regs) 627 { 628 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 629 return ehci_big_endian_mmio(ehci) ? 630 readl_be(regs) : 631 readl(regs); 632 #else 633 return readl(regs); 634 #endif 635 } 636 637 static inline void ehci_writel(const struct ehci_hcd *ehci, 638 const unsigned int val, __u32 __iomem *regs) 639 { 640 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 641 ehci_big_endian_mmio(ehci) ? 642 writel_be(val, regs) : 643 writel(val, regs); 644 #else 645 writel(val, regs); 646 #endif 647 } 648 649 /* 650 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 651 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 652 * Other common bits are dependant on has_amcc_usb23 quirk flag. 653 */ 654 #ifdef CONFIG_44x 655 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 656 { 657 u32 hc_control; 658 659 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 660 if (operational) 661 hc_control |= OHCI_USB_OPER; 662 else 663 hc_control |= OHCI_USB_SUSPEND; 664 665 writel_be(hc_control, ehci->ohci_hcctrl_reg); 666 (void) readl_be(ehci->ohci_hcctrl_reg); 667 } 668 #else 669 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 670 { } 671 #endif 672 673 /*-------------------------------------------------------------------------*/ 674 675 /* 676 * The AMCC 440EPx not only implements its EHCI registers in big-endian 677 * format, but also its DMA data structures (descriptors). 678 * 679 * EHCI controllers accessed through PCI work normally (little-endian 680 * everywhere), so we won't bother supporting a BE-only mode for now. 681 */ 682 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 683 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 684 685 /* cpu to ehci */ 686 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 687 { 688 return ehci_big_endian_desc(ehci) 689 ? (__force __hc32)cpu_to_be32(x) 690 : (__force __hc32)cpu_to_le32(x); 691 } 692 693 /* ehci to cpu */ 694 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 695 { 696 return ehci_big_endian_desc(ehci) 697 ? be32_to_cpu((__force __be32)x) 698 : le32_to_cpu((__force __le32)x); 699 } 700 701 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 702 { 703 return ehci_big_endian_desc(ehci) 704 ? be32_to_cpup((__force __be32 *)x) 705 : le32_to_cpup((__force __le32 *)x); 706 } 707 708 #else 709 710 /* cpu to ehci */ 711 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 712 { 713 return cpu_to_le32(x); 714 } 715 716 /* ehci to cpu */ 717 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 718 { 719 return le32_to_cpu(x); 720 } 721 722 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 723 { 724 return le32_to_cpup(x); 725 } 726 727 #endif 728 729 /*-------------------------------------------------------------------------*/ 730 731 #ifndef DEBUG 732 #define STUB_DEBUG_FILES 733 #endif /* DEBUG */ 734 735 /*-------------------------------------------------------------------------*/ 736 737 #endif /* __LINUX_EHCI_HCD_H */ 738