1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long iaa; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, unlink, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 /* 66 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 67 * controller may be doing DMA. Lower values mean there's no DMA. 68 */ 69 enum ehci_rh_state { 70 EHCI_RH_HALTED, 71 EHCI_RH_SUSPENDED, 72 EHCI_RH_RUNNING, 73 EHCI_RH_STOPPING 74 }; 75 76 /* 77 * Timer events, ordered by increasing delay length. 78 * Always update event_delays_ns[] and event_handlers[] (defined in 79 * ehci-timer.c) in parallel with this list. 80 */ 81 enum ehci_hrtimer_event { 82 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 83 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 84 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 85 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 86 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 87 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 88 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 89 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 90 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 91 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 92 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 93 }; 94 #define EHCI_HRTIMER_NO_EVENT 99 95 96 struct ehci_hcd { /* one per controller */ 97 /* timing support */ 98 enum ehci_hrtimer_event next_hrtimer_event; 99 unsigned enabled_hrtimer_events; 100 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 101 struct hrtimer hrtimer; 102 103 int PSS_poll_count; 104 int ASS_poll_count; 105 int died_poll_count; 106 107 /* glue to PCI and HCD framework */ 108 struct ehci_caps __iomem *caps; 109 struct ehci_regs __iomem *regs; 110 struct ehci_dbg_port __iomem *debug; 111 112 __u32 hcs_params; /* cached register copy */ 113 spinlock_t lock; 114 enum ehci_rh_state rh_state; 115 116 /* general schedule support */ 117 bool scanning:1; 118 bool need_rescan:1; 119 bool intr_unlinking:1; 120 bool async_unlinking:1; 121 bool shutdown:1; 122 struct ehci_qh *qh_scan_next; 123 124 /* async schedule support */ 125 struct ehci_qh *async; 126 struct ehci_qh *dummy; /* For AMD quirk use */ 127 struct ehci_qh *async_unlink; 128 struct ehci_qh *async_unlink_last; 129 struct ehci_qh *async_iaa; 130 unsigned async_unlink_cycle; 131 unsigned async_count; /* async activity count */ 132 133 /* periodic schedule support */ 134 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 135 unsigned periodic_size; 136 __hc32 *periodic; /* hw periodic table */ 137 dma_addr_t periodic_dma; 138 struct list_head intr_qh_list; 139 unsigned i_thresh; /* uframes HC might cache */ 140 141 union ehci_shadow *pshadow; /* mirror hw periodic table */ 142 struct ehci_qh *intr_unlink; 143 struct ehci_qh *intr_unlink_last; 144 unsigned intr_unlink_cycle; 145 unsigned now_frame; /* frame from HC hardware */ 146 unsigned last_iso_frame; /* last frame scanned for iso */ 147 unsigned intr_count; /* intr activity count */ 148 unsigned isoc_count; /* isoc activity count */ 149 unsigned periodic_count; /* periodic activity count */ 150 unsigned uframe_periodic_max; /* max periodic time per uframe */ 151 152 153 /* list of itds & sitds completed while now_frame was still active */ 154 struct list_head cached_itd_list; 155 struct ehci_itd *last_itd_to_free; 156 struct list_head cached_sitd_list; 157 struct ehci_sitd *last_sitd_to_free; 158 159 /* per root hub port */ 160 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 161 162 /* bit vectors (one bit per port) */ 163 unsigned long bus_suspended; /* which ports were 164 already suspended at the start of a bus suspend */ 165 unsigned long companion_ports; /* which ports are 166 dedicated to the companion controller */ 167 unsigned long owned_ports; /* which ports are 168 owned by the companion during a bus suspend */ 169 unsigned long port_c_suspend; /* which ports have 170 the change-suspend feature turned on */ 171 unsigned long suspended_ports; /* which ports are 172 suspended */ 173 unsigned long resuming_ports; /* which ports have 174 started to resume */ 175 176 /* per-HC memory pools (could be per-bus, but ...) */ 177 struct dma_pool *qh_pool; /* qh per active urb */ 178 struct dma_pool *qtd_pool; /* one or more per qh */ 179 struct dma_pool *itd_pool; /* itd per iso urb */ 180 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 181 182 unsigned random_frame; 183 unsigned long next_statechange; 184 ktime_t last_periodic_enable; 185 u32 command; 186 187 /* SILICON QUIRKS */ 188 unsigned no_selective_suspend:1; 189 unsigned has_fsl_port_bug:1; /* FreeScale */ 190 unsigned big_endian_mmio:1; 191 unsigned big_endian_desc:1; 192 unsigned big_endian_capbase:1; 193 unsigned has_amcc_usb23:1; 194 unsigned need_io_watchdog:1; 195 unsigned amd_pll_fix:1; 196 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 197 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 198 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 199 200 /* required for usb32 quirk */ 201 #define OHCI_CTRL_HCFS (3 << 6) 202 #define OHCI_USB_OPER (2 << 6) 203 #define OHCI_USB_SUSPEND (3 << 6) 204 205 #define OHCI_HCCTRL_OFFSET 0x4 206 #define OHCI_HCCTRL_LEN 0x4 207 __hc32 *ohci_hcctrl_reg; 208 unsigned has_hostpc:1; 209 unsigned has_ppcd:1; /* support per-port change bits */ 210 u8 sbrn; /* packed release number */ 211 212 /* irq statistics */ 213 #ifdef EHCI_STATS 214 struct ehci_stats stats; 215 # define COUNT(x) do { (x)++; } while (0) 216 #else 217 # define COUNT(x) do {} while (0) 218 #endif 219 220 /* debug files */ 221 #ifdef DEBUG 222 struct dentry *debug_dir; 223 #endif 224 }; 225 226 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 227 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 228 { 229 return (struct ehci_hcd *) (hcd->hcd_priv); 230 } 231 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 232 { 233 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 234 } 235 236 /*-------------------------------------------------------------------------*/ 237 238 #include <linux/usb/ehci_def.h> 239 240 /*-------------------------------------------------------------------------*/ 241 242 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 243 244 /* 245 * EHCI Specification 0.95 Section 3.5 246 * QTD: describe data transfer components (buffer, direction, ...) 247 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 248 * 249 * These are associated only with "QH" (Queue Head) structures, 250 * used with control, bulk, and interrupt transfers. 251 */ 252 struct ehci_qtd { 253 /* first part defined by EHCI spec */ 254 __hc32 hw_next; /* see EHCI 3.5.1 */ 255 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 256 __hc32 hw_token; /* see EHCI 3.5.3 */ 257 #define QTD_TOGGLE (1 << 31) /* data toggle */ 258 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 259 #define QTD_IOC (1 << 15) /* interrupt on complete */ 260 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 261 #define QTD_PID(tok) (((tok)>>8) & 0x3) 262 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 263 #define QTD_STS_HALT (1 << 6) /* halted on error */ 264 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 265 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 266 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 267 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 268 #define QTD_STS_STS (1 << 1) /* split transaction state */ 269 #define QTD_STS_PING (1 << 0) /* issue PING? */ 270 271 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 272 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 273 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 274 275 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 276 __hc32 hw_buf_hi [5]; /* Appendix B */ 277 278 /* the rest is HCD-private */ 279 dma_addr_t qtd_dma; /* qtd address */ 280 struct list_head qtd_list; /* sw qtd list */ 281 struct urb *urb; /* qtd's urb */ 282 size_t length; /* length of buffer */ 283 } __attribute__ ((aligned (32))); 284 285 /* mask NakCnt+T in qh->hw_alt_next */ 286 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 287 288 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 289 290 /*-------------------------------------------------------------------------*/ 291 292 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 293 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 294 295 /* 296 * Now the following defines are not converted using the 297 * cpu_to_le32() macro anymore, since we have to support 298 * "dynamic" switching between be and le support, so that the driver 299 * can be used on one system with SoC EHCI controller using big-endian 300 * descriptors as well as a normal little-endian PCI EHCI controller. 301 */ 302 /* values for that type tag */ 303 #define Q_TYPE_ITD (0 << 1) 304 #define Q_TYPE_QH (1 << 1) 305 #define Q_TYPE_SITD (2 << 1) 306 #define Q_TYPE_FSTN (3 << 1) 307 308 /* next async queue entry, or pointer to interrupt/periodic QH */ 309 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 310 311 /* for periodic/async schedules and qtd lists, mark end of list */ 312 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 313 314 /* 315 * Entries in periodic shadow table are pointers to one of four kinds 316 * of data structure. That's dictated by the hardware; a type tag is 317 * encoded in the low bits of the hardware's periodic schedule. Use 318 * Q_NEXT_TYPE to get the tag. 319 * 320 * For entries in the async schedule, the type tag always says "qh". 321 */ 322 union ehci_shadow { 323 struct ehci_qh *qh; /* Q_TYPE_QH */ 324 struct ehci_itd *itd; /* Q_TYPE_ITD */ 325 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 326 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 327 __hc32 *hw_next; /* (all types) */ 328 void *ptr; 329 }; 330 331 /*-------------------------------------------------------------------------*/ 332 333 /* 334 * EHCI Specification 0.95 Section 3.6 335 * QH: describes control/bulk/interrupt endpoints 336 * See Fig 3-7 "Queue Head Structure Layout". 337 * 338 * These appear in both the async and (for interrupt) periodic schedules. 339 */ 340 341 /* first part defined by EHCI spec */ 342 struct ehci_qh_hw { 343 __hc32 hw_next; /* see EHCI 3.6.1 */ 344 __hc32 hw_info1; /* see EHCI 3.6.2 */ 345 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 346 #define QH_HEAD (1 << 15) /* Head of async reclamation list */ 347 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 348 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 349 #define QH_LOW_SPEED (1 << 12) 350 #define QH_FULL_SPEED (0 << 12) 351 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 352 __hc32 hw_info2; /* see EHCI 3.6.2 */ 353 #define QH_SMASK 0x000000ff 354 #define QH_CMASK 0x0000ff00 355 #define QH_HUBADDR 0x007f0000 356 #define QH_HUBPORT 0x3f800000 357 #define QH_MULT 0xc0000000 358 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 359 360 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 361 __hc32 hw_qtd_next; 362 __hc32 hw_alt_next; 363 __hc32 hw_token; 364 __hc32 hw_buf [5]; 365 __hc32 hw_buf_hi [5]; 366 } __attribute__ ((aligned(32))); 367 368 struct ehci_qh { 369 struct ehci_qh_hw *hw; /* Must come first */ 370 /* the rest is HCD-private */ 371 dma_addr_t qh_dma; /* address of qh */ 372 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 373 struct list_head qtd_list; /* sw qtd list */ 374 struct list_head intr_node; /* list of intr QHs */ 375 struct ehci_qtd *dummy; 376 struct ehci_qh *unlink_next; /* next on unlink list */ 377 378 unsigned unlink_cycle; 379 380 u8 needs_rescan; /* Dequeue during giveback */ 381 u8 qh_state; 382 #define QH_STATE_LINKED 1 /* HC sees this */ 383 #define QH_STATE_UNLINK 2 /* HC may still see this */ 384 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 385 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 386 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 387 388 u8 xacterrs; /* XactErr retry counter */ 389 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 390 391 /* periodic schedule info */ 392 u8 usecs; /* intr bandwidth */ 393 u8 gap_uf; /* uframes split/csplit gap */ 394 u8 c_usecs; /* ... split completion bw */ 395 u16 tt_usecs; /* tt downstream bandwidth */ 396 unsigned short period; /* polling interval */ 397 unsigned short start; /* where polling starts */ 398 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 399 400 struct usb_device *dev; /* access to TT */ 401 unsigned is_out:1; /* bulk or intr OUT */ 402 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 403 }; 404 405 /*-------------------------------------------------------------------------*/ 406 407 /* description of one iso transaction (up to 3 KB data if highspeed) */ 408 struct ehci_iso_packet { 409 /* These will be copied to iTD when scheduling */ 410 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 411 __hc32 transaction; /* itd->hw_transaction[i] |= */ 412 u8 cross; /* buf crosses pages */ 413 /* for full speed OUT splits */ 414 u32 buf1; 415 }; 416 417 /* temporary schedule data for packets from iso urbs (both speeds) 418 * each packet is one logical usb transaction to the device (not TT), 419 * beginning at stream->next_uframe 420 */ 421 struct ehci_iso_sched { 422 struct list_head td_list; 423 unsigned span; 424 struct ehci_iso_packet packet [0]; 425 }; 426 427 /* 428 * ehci_iso_stream - groups all (s)itds for this endpoint. 429 * acts like a qh would, if EHCI had them for ISO. 430 */ 431 struct ehci_iso_stream { 432 /* first field matches ehci_hq, but is NULL */ 433 struct ehci_qh_hw *hw; 434 435 u8 bEndpointAddress; 436 u8 highspeed; 437 struct list_head td_list; /* queued itds/sitds */ 438 struct list_head free_list; /* list of unused itds/sitds */ 439 struct usb_device *udev; 440 struct usb_host_endpoint *ep; 441 442 /* output of (re)scheduling */ 443 int next_uframe; 444 __hc32 splits; 445 446 /* the rest is derived from the endpoint descriptor, 447 * trusting urb->interval == f(epdesc->bInterval) and 448 * including the extra info for hw_bufp[0..2] 449 */ 450 u8 usecs, c_usecs; 451 u16 interval; 452 u16 tt_usecs; 453 u16 maxp; 454 u16 raw_mask; 455 unsigned bandwidth; 456 457 /* This is used to initialize iTD's hw_bufp fields */ 458 __hc32 buf0; 459 __hc32 buf1; 460 __hc32 buf2; 461 462 /* this is used to initialize sITD's tt info */ 463 __hc32 address; 464 }; 465 466 /*-------------------------------------------------------------------------*/ 467 468 /* 469 * EHCI Specification 0.95 Section 3.3 470 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 471 * 472 * Schedule records for high speed iso xfers 473 */ 474 struct ehci_itd { 475 /* first part defined by EHCI spec */ 476 __hc32 hw_next; /* see EHCI 3.3.1 */ 477 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 478 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 479 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 480 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 481 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 482 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 483 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 484 485 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 486 487 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 488 __hc32 hw_bufp_hi [7]; /* Appendix B */ 489 490 /* the rest is HCD-private */ 491 dma_addr_t itd_dma; /* for this itd */ 492 union ehci_shadow itd_next; /* ptr to periodic q entry */ 493 494 struct urb *urb; 495 struct ehci_iso_stream *stream; /* endpoint's queue */ 496 struct list_head itd_list; /* list of stream's itds */ 497 498 /* any/all hw_transactions here may be used by that urb */ 499 unsigned frame; /* where scheduled */ 500 unsigned pg; 501 unsigned index[8]; /* in urb->iso_frame_desc */ 502 } __attribute__ ((aligned (32))); 503 504 /*-------------------------------------------------------------------------*/ 505 506 /* 507 * EHCI Specification 0.95 Section 3.4 508 * siTD, aka split-transaction isochronous Transfer Descriptor 509 * ... describe full speed iso xfers through TT in hubs 510 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 511 */ 512 struct ehci_sitd { 513 /* first part defined by EHCI spec */ 514 __hc32 hw_next; 515 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 516 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 517 __hc32 hw_uframe; /* EHCI table 3-10 */ 518 __hc32 hw_results; /* EHCI table 3-11 */ 519 #define SITD_IOC (1 << 31) /* interrupt on completion */ 520 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 521 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 522 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 523 #define SITD_STS_ERR (1 << 6) /* error from TT */ 524 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 525 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 526 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 527 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 528 #define SITD_STS_STS (1 << 1) /* split transaction state */ 529 530 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 531 532 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 533 __hc32 hw_backpointer; /* EHCI table 3-13 */ 534 __hc32 hw_buf_hi [2]; /* Appendix B */ 535 536 /* the rest is HCD-private */ 537 dma_addr_t sitd_dma; 538 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 539 540 struct urb *urb; 541 struct ehci_iso_stream *stream; /* endpoint's queue */ 542 struct list_head sitd_list; /* list of stream's sitds */ 543 unsigned frame; 544 unsigned index; 545 } __attribute__ ((aligned (32))); 546 547 /*-------------------------------------------------------------------------*/ 548 549 /* 550 * EHCI Specification 0.96 Section 3.7 551 * Periodic Frame Span Traversal Node (FSTN) 552 * 553 * Manages split interrupt transactions (using TT) that span frame boundaries 554 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 555 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 556 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 557 */ 558 struct ehci_fstn { 559 __hc32 hw_next; /* any periodic q entry */ 560 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 561 562 /* the rest is HCD-private */ 563 dma_addr_t fstn_dma; 564 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 565 } __attribute__ ((aligned (32))); 566 567 /*-------------------------------------------------------------------------*/ 568 569 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 570 571 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 572 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 573 574 #define ehci_prepare_ports_for_controller_resume(ehci) \ 575 ehci_adjust_port_wakeup_flags(ehci, false, false); 576 577 /*-------------------------------------------------------------------------*/ 578 579 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 580 581 /* 582 * Some EHCI controllers have a Transaction Translator built into the 583 * root hub. This is a non-standard feature. Each controller will need 584 * to add code to the following inline functions, and call them as 585 * needed (mostly in root hub code). 586 */ 587 588 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 589 590 /* Returns the speed of a device attached to a port on the root hub. */ 591 static inline unsigned int 592 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 593 { 594 if (ehci_is_TDI(ehci)) { 595 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 596 case 0: 597 return 0; 598 case 1: 599 return USB_PORT_STAT_LOW_SPEED; 600 case 2: 601 default: 602 return USB_PORT_STAT_HIGH_SPEED; 603 } 604 } 605 return USB_PORT_STAT_HIGH_SPEED; 606 } 607 608 #else 609 610 #define ehci_is_TDI(e) (0) 611 612 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 613 #endif 614 615 /*-------------------------------------------------------------------------*/ 616 617 #ifdef CONFIG_PPC_83xx 618 /* Some Freescale processors have an erratum in which the TT 619 * port number in the queue head was 0..N-1 instead of 1..N. 620 */ 621 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 622 #else 623 #define ehci_has_fsl_portno_bug(e) (0) 624 #endif 625 626 /* 627 * While most USB host controllers implement their registers in 628 * little-endian format, a minority (celleb companion chip) implement 629 * them in big endian format. 630 * 631 * This attempts to support either format at compile time without a 632 * runtime penalty, or both formats with the additional overhead 633 * of checking a flag bit. 634 * 635 * ehci_big_endian_capbase is a special quirk for controllers that 636 * implement the HC capability registers as separate registers and not 637 * as fields of a 32-bit register. 638 */ 639 640 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 641 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 642 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 643 #else 644 #define ehci_big_endian_mmio(e) 0 645 #define ehci_big_endian_capbase(e) 0 646 #endif 647 648 /* 649 * Big-endian read/write functions are arch-specific. 650 * Other arches can be added if/when they're needed. 651 */ 652 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 653 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 654 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 655 #endif 656 657 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 658 __u32 __iomem * regs) 659 { 660 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 661 return ehci_big_endian_mmio(ehci) ? 662 readl_be(regs) : 663 readl(regs); 664 #else 665 return readl(regs); 666 #endif 667 } 668 669 static inline void ehci_writel(const struct ehci_hcd *ehci, 670 const unsigned int val, __u32 __iomem *regs) 671 { 672 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 673 ehci_big_endian_mmio(ehci) ? 674 writel_be(val, regs) : 675 writel(val, regs); 676 #else 677 writel(val, regs); 678 #endif 679 } 680 681 /* 682 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 683 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 684 * Other common bits are dependent on has_amcc_usb23 quirk flag. 685 */ 686 #ifdef CONFIG_44x 687 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 688 { 689 u32 hc_control; 690 691 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 692 if (operational) 693 hc_control |= OHCI_USB_OPER; 694 else 695 hc_control |= OHCI_USB_SUSPEND; 696 697 writel_be(hc_control, ehci->ohci_hcctrl_reg); 698 (void) readl_be(ehci->ohci_hcctrl_reg); 699 } 700 #else 701 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 702 { } 703 #endif 704 705 /*-------------------------------------------------------------------------*/ 706 707 /* 708 * The AMCC 440EPx not only implements its EHCI registers in big-endian 709 * format, but also its DMA data structures (descriptors). 710 * 711 * EHCI controllers accessed through PCI work normally (little-endian 712 * everywhere), so we won't bother supporting a BE-only mode for now. 713 */ 714 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 715 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 716 717 /* cpu to ehci */ 718 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 719 { 720 return ehci_big_endian_desc(ehci) 721 ? (__force __hc32)cpu_to_be32(x) 722 : (__force __hc32)cpu_to_le32(x); 723 } 724 725 /* ehci to cpu */ 726 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 727 { 728 return ehci_big_endian_desc(ehci) 729 ? be32_to_cpu((__force __be32)x) 730 : le32_to_cpu((__force __le32)x); 731 } 732 733 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 734 { 735 return ehci_big_endian_desc(ehci) 736 ? be32_to_cpup((__force __be32 *)x) 737 : le32_to_cpup((__force __le32 *)x); 738 } 739 740 #else 741 742 /* cpu to ehci */ 743 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 744 { 745 return cpu_to_le32(x); 746 } 747 748 /* ehci to cpu */ 749 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 750 { 751 return le32_to_cpu(x); 752 } 753 754 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 755 { 756 return le32_to_cpup(x); 757 } 758 759 #endif 760 761 /*-------------------------------------------------------------------------*/ 762 763 #define ehci_dbg(ehci, fmt, args...) \ 764 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 765 #define ehci_err(ehci, fmt, args...) \ 766 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 767 #define ehci_info(ehci, fmt, args...) \ 768 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 769 #define ehci_warn(ehci, fmt, args...) \ 770 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 771 772 #ifdef VERBOSE_DEBUG 773 # define ehci_vdbg ehci_dbg 774 #else 775 static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {} 776 #endif 777 778 #ifndef DEBUG 779 #define STUB_DEBUG_FILES 780 #endif /* DEBUG */ 781 782 /*-------------------------------------------------------------------------*/ 783 784 /* Declarations of things exported for use by ehci platform drivers */ 785 786 struct ehci_driver_overrides { 787 size_t extra_priv_size; 788 int (*reset)(struct usb_hcd *hcd); 789 }; 790 791 extern void ehci_init_driver(struct hc_driver *drv, 792 const struct ehci_driver_overrides *over); 793 extern int ehci_setup(struct usb_hcd *hcd); 794 795 #ifdef CONFIG_PM 796 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 797 extern int ehci_resume(struct usb_hcd *hcd, bool hibernated); 798 #endif /* CONFIG_PM */ 799 800 #endif /* __LINUX_EHCI_HCD_H */ 801