1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* list of itds completed while clock_frame was still active */ 91 struct list_head cached_itd_list; 92 unsigned clock_frame; 93 94 /* per root hub port */ 95 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 96 97 /* bit vectors (one bit per port) */ 98 unsigned long bus_suspended; /* which ports were 99 already suspended at the start of a bus suspend */ 100 unsigned long companion_ports; /* which ports are 101 dedicated to the companion controller */ 102 unsigned long owned_ports; /* which ports are 103 owned by the companion during a bus suspend */ 104 unsigned long port_c_suspend; /* which ports have 105 the change-suspend feature turned on */ 106 unsigned long suspended_ports; /* which ports are 107 suspended */ 108 109 /* per-HC memory pools (could be per-bus, but ...) */ 110 struct dma_pool *qh_pool; /* qh per active urb */ 111 struct dma_pool *qtd_pool; /* one or more per qh */ 112 struct dma_pool *itd_pool; /* itd per iso urb */ 113 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 114 115 struct timer_list iaa_watchdog; 116 struct timer_list watchdog; 117 unsigned long actions; 118 unsigned stamp; 119 unsigned long next_statechange; 120 u32 command; 121 122 /* SILICON QUIRKS */ 123 unsigned no_selective_suspend:1; 124 unsigned has_fsl_port_bug:1; /* FreeScale */ 125 unsigned big_endian_mmio:1; 126 unsigned big_endian_desc:1; 127 unsigned has_amcc_usb23:1; 128 129 /* required for usb32 quirk */ 130 #define OHCI_CTRL_HCFS (3 << 6) 131 #define OHCI_USB_OPER (2 << 6) 132 #define OHCI_USB_SUSPEND (3 << 6) 133 134 #define OHCI_HCCTRL_OFFSET 0x4 135 #define OHCI_HCCTRL_LEN 0x4 136 __hc32 *ohci_hcctrl_reg; 137 138 u8 sbrn; /* packed release number */ 139 140 /* irq statistics */ 141 #ifdef EHCI_STATS 142 struct ehci_stats stats; 143 # define COUNT(x) do { (x)++; } while (0) 144 #else 145 # define COUNT(x) do {} while (0) 146 #endif 147 148 /* debug files */ 149 #ifdef DEBUG 150 struct dentry *debug_dir; 151 struct dentry *debug_async; 152 struct dentry *debug_periodic; 153 struct dentry *debug_registers; 154 #endif 155 }; 156 157 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 158 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 159 { 160 return (struct ehci_hcd *) (hcd->hcd_priv); 161 } 162 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 163 { 164 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 165 } 166 167 168 static inline void 169 iaa_watchdog_start(struct ehci_hcd *ehci) 170 { 171 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 172 mod_timer(&ehci->iaa_watchdog, 173 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 174 } 175 176 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 177 { 178 del_timer(&ehci->iaa_watchdog); 179 } 180 181 enum ehci_timer_action { 182 TIMER_IO_WATCHDOG, 183 TIMER_ASYNC_SHRINK, 184 TIMER_ASYNC_OFF, 185 }; 186 187 static inline void 188 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 189 { 190 clear_bit (action, &ehci->actions); 191 } 192 193 static inline void 194 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 195 { 196 /* Don't override timeouts which shrink or (later) disable 197 * the async ring; just the I/O watchdog. Note that if a 198 * SHRINK were pending, OFF would never be requested. 199 */ 200 if (timer_pending(&ehci->watchdog) 201 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 202 & ehci->actions)) 203 return; 204 205 if (!test_and_set_bit (action, &ehci->actions)) { 206 unsigned long t; 207 208 switch (action) { 209 case TIMER_IO_WATCHDOG: 210 t = EHCI_IO_JIFFIES; 211 break; 212 case TIMER_ASYNC_OFF: 213 t = EHCI_ASYNC_JIFFIES; 214 break; 215 // case TIMER_ASYNC_SHRINK: 216 default: 217 /* add a jiffie since we synch against the 218 * 8 KHz uframe counter. 219 */ 220 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 221 break; 222 } 223 mod_timer(&ehci->watchdog, t + jiffies); 224 } 225 } 226 227 static void free_cached_itd_list(struct ehci_hcd *ehci); 228 229 /*-------------------------------------------------------------------------*/ 230 231 #include <linux/usb/ehci_def.h> 232 233 /*-------------------------------------------------------------------------*/ 234 235 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 236 237 /* 238 * EHCI Specification 0.95 Section 3.5 239 * QTD: describe data transfer components (buffer, direction, ...) 240 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 241 * 242 * These are associated only with "QH" (Queue Head) structures, 243 * used with control, bulk, and interrupt transfers. 244 */ 245 struct ehci_qtd { 246 /* first part defined by EHCI spec */ 247 __hc32 hw_next; /* see EHCI 3.5.1 */ 248 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 249 __hc32 hw_token; /* see EHCI 3.5.3 */ 250 #define QTD_TOGGLE (1 << 31) /* data toggle */ 251 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 252 #define QTD_IOC (1 << 15) /* interrupt on complete */ 253 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 254 #define QTD_PID(tok) (((tok)>>8) & 0x3) 255 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 256 #define QTD_STS_HALT (1 << 6) /* halted on error */ 257 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 258 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 259 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 260 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 261 #define QTD_STS_STS (1 << 1) /* split transaction state */ 262 #define QTD_STS_PING (1 << 0) /* issue PING? */ 263 264 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 265 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 266 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 267 268 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 269 __hc32 hw_buf_hi [5]; /* Appendix B */ 270 271 /* the rest is HCD-private */ 272 dma_addr_t qtd_dma; /* qtd address */ 273 struct list_head qtd_list; /* sw qtd list */ 274 struct urb *urb; /* qtd's urb */ 275 size_t length; /* length of buffer */ 276 } __attribute__ ((aligned (32))); 277 278 /* mask NakCnt+T in qh->hw_alt_next */ 279 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 280 281 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 282 283 /*-------------------------------------------------------------------------*/ 284 285 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 286 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 287 288 /* 289 * Now the following defines are not converted using the 290 * __constant_cpu_to_le32() macro anymore, since we have to support 291 * "dynamic" switching between be and le support, so that the driver 292 * can be used on one system with SoC EHCI controller using big-endian 293 * descriptors as well as a normal little-endian PCI EHCI controller. 294 */ 295 /* values for that type tag */ 296 #define Q_TYPE_ITD (0 << 1) 297 #define Q_TYPE_QH (1 << 1) 298 #define Q_TYPE_SITD (2 << 1) 299 #define Q_TYPE_FSTN (3 << 1) 300 301 /* next async queue entry, or pointer to interrupt/periodic QH */ 302 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 303 304 /* for periodic/async schedules and qtd lists, mark end of list */ 305 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 306 307 /* 308 * Entries in periodic shadow table are pointers to one of four kinds 309 * of data structure. That's dictated by the hardware; a type tag is 310 * encoded in the low bits of the hardware's periodic schedule. Use 311 * Q_NEXT_TYPE to get the tag. 312 * 313 * For entries in the async schedule, the type tag always says "qh". 314 */ 315 union ehci_shadow { 316 struct ehci_qh *qh; /* Q_TYPE_QH */ 317 struct ehci_itd *itd; /* Q_TYPE_ITD */ 318 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 319 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 320 __hc32 *hw_next; /* (all types) */ 321 void *ptr; 322 }; 323 324 /*-------------------------------------------------------------------------*/ 325 326 /* 327 * EHCI Specification 0.95 Section 3.6 328 * QH: describes control/bulk/interrupt endpoints 329 * See Fig 3-7 "Queue Head Structure Layout". 330 * 331 * These appear in both the async and (for interrupt) periodic schedules. 332 */ 333 334 struct ehci_qh { 335 /* first part defined by EHCI spec */ 336 __hc32 hw_next; /* see EHCI 3.6.1 */ 337 __hc32 hw_info1; /* see EHCI 3.6.2 */ 338 #define QH_HEAD 0x00008000 339 __hc32 hw_info2; /* see EHCI 3.6.2 */ 340 #define QH_SMASK 0x000000ff 341 #define QH_CMASK 0x0000ff00 342 #define QH_HUBADDR 0x007f0000 343 #define QH_HUBPORT 0x3f800000 344 #define QH_MULT 0xc0000000 345 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 346 347 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 348 __hc32 hw_qtd_next; 349 __hc32 hw_alt_next; 350 __hc32 hw_token; 351 __hc32 hw_buf [5]; 352 __hc32 hw_buf_hi [5]; 353 354 /* the rest is HCD-private */ 355 dma_addr_t qh_dma; /* address of qh */ 356 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 357 struct list_head qtd_list; /* sw qtd list */ 358 struct ehci_qtd *dummy; 359 struct ehci_qh *reclaim; /* next to reclaim */ 360 361 struct ehci_hcd *ehci; 362 363 /* 364 * Do NOT use atomic operations for QH refcounting. On some CPUs 365 * (PPC7448 for example), atomic operations cannot be performed on 366 * memory that is cache-inhibited (i.e. being used for DMA). 367 * Spinlocks are used to protect all QH fields. 368 */ 369 u32 refcount; 370 unsigned stamp; 371 372 u8 qh_state; 373 #define QH_STATE_LINKED 1 /* HC sees this */ 374 #define QH_STATE_UNLINK 2 /* HC may still see this */ 375 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 376 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 377 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 378 379 /* periodic schedule info */ 380 u8 usecs; /* intr bandwidth */ 381 u8 gap_uf; /* uframes split/csplit gap */ 382 u8 c_usecs; /* ... split completion bw */ 383 u16 tt_usecs; /* tt downstream bandwidth */ 384 unsigned short period; /* polling interval */ 385 unsigned short start; /* where polling starts */ 386 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 387 struct usb_device *dev; /* access to TT */ 388 } __attribute__ ((aligned (32))); 389 390 /*-------------------------------------------------------------------------*/ 391 392 /* description of one iso transaction (up to 3 KB data if highspeed) */ 393 struct ehci_iso_packet { 394 /* These will be copied to iTD when scheduling */ 395 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 396 __hc32 transaction; /* itd->hw_transaction[i] |= */ 397 u8 cross; /* buf crosses pages */ 398 /* for full speed OUT splits */ 399 u32 buf1; 400 }; 401 402 /* temporary schedule data for packets from iso urbs (both speeds) 403 * each packet is one logical usb transaction to the device (not TT), 404 * beginning at stream->next_uframe 405 */ 406 struct ehci_iso_sched { 407 struct list_head td_list; 408 unsigned span; 409 struct ehci_iso_packet packet [0]; 410 }; 411 412 /* 413 * ehci_iso_stream - groups all (s)itds for this endpoint. 414 * acts like a qh would, if EHCI had them for ISO. 415 */ 416 struct ehci_iso_stream { 417 /* first two fields match QH, but info1 == 0 */ 418 __hc32 hw_next; 419 __hc32 hw_info1; 420 421 u32 refcount; 422 u8 bEndpointAddress; 423 u8 highspeed; 424 u16 depth; /* depth in uframes */ 425 struct list_head td_list; /* queued itds/sitds */ 426 struct list_head free_list; /* list of unused itds/sitds */ 427 struct usb_device *udev; 428 struct usb_host_endpoint *ep; 429 430 /* output of (re)scheduling */ 431 unsigned long start; /* jiffies */ 432 unsigned long rescheduled; 433 int next_uframe; 434 __hc32 splits; 435 436 /* the rest is derived from the endpoint descriptor, 437 * trusting urb->interval == f(epdesc->bInterval) and 438 * including the extra info for hw_bufp[0..2] 439 */ 440 u8 usecs, c_usecs; 441 u16 interval; 442 u16 tt_usecs; 443 u16 maxp; 444 u16 raw_mask; 445 unsigned bandwidth; 446 447 /* This is used to initialize iTD's hw_bufp fields */ 448 __hc32 buf0; 449 __hc32 buf1; 450 __hc32 buf2; 451 452 /* this is used to initialize sITD's tt info */ 453 __hc32 address; 454 }; 455 456 /*-------------------------------------------------------------------------*/ 457 458 /* 459 * EHCI Specification 0.95 Section 3.3 460 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 461 * 462 * Schedule records for high speed iso xfers 463 */ 464 struct ehci_itd { 465 /* first part defined by EHCI spec */ 466 __hc32 hw_next; /* see EHCI 3.3.1 */ 467 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 468 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 469 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 470 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 471 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 472 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 473 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 474 475 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 476 477 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 478 __hc32 hw_bufp_hi [7]; /* Appendix B */ 479 480 /* the rest is HCD-private */ 481 dma_addr_t itd_dma; /* for this itd */ 482 union ehci_shadow itd_next; /* ptr to periodic q entry */ 483 484 struct urb *urb; 485 struct ehci_iso_stream *stream; /* endpoint's queue */ 486 struct list_head itd_list; /* list of stream's itds */ 487 488 /* any/all hw_transactions here may be used by that urb */ 489 unsigned frame; /* where scheduled */ 490 unsigned pg; 491 unsigned index[8]; /* in urb->iso_frame_desc */ 492 } __attribute__ ((aligned (32))); 493 494 /*-------------------------------------------------------------------------*/ 495 496 /* 497 * EHCI Specification 0.95 Section 3.4 498 * siTD, aka split-transaction isochronous Transfer Descriptor 499 * ... describe full speed iso xfers through TT in hubs 500 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 501 */ 502 struct ehci_sitd { 503 /* first part defined by EHCI spec */ 504 __hc32 hw_next; 505 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 506 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 507 __hc32 hw_uframe; /* EHCI table 3-10 */ 508 __hc32 hw_results; /* EHCI table 3-11 */ 509 #define SITD_IOC (1 << 31) /* interrupt on completion */ 510 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 511 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 512 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 513 #define SITD_STS_ERR (1 << 6) /* error from TT */ 514 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 515 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 516 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 517 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 518 #define SITD_STS_STS (1 << 1) /* split transaction state */ 519 520 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 521 522 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 523 __hc32 hw_backpointer; /* EHCI table 3-13 */ 524 __hc32 hw_buf_hi [2]; /* Appendix B */ 525 526 /* the rest is HCD-private */ 527 dma_addr_t sitd_dma; 528 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 529 530 struct urb *urb; 531 struct ehci_iso_stream *stream; /* endpoint's queue */ 532 struct list_head sitd_list; /* list of stream's sitds */ 533 unsigned frame; 534 unsigned index; 535 } __attribute__ ((aligned (32))); 536 537 /*-------------------------------------------------------------------------*/ 538 539 /* 540 * EHCI Specification 0.96 Section 3.7 541 * Periodic Frame Span Traversal Node (FSTN) 542 * 543 * Manages split interrupt transactions (using TT) that span frame boundaries 544 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 545 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 546 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 547 */ 548 struct ehci_fstn { 549 __hc32 hw_next; /* any periodic q entry */ 550 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 551 552 /* the rest is HCD-private */ 553 dma_addr_t fstn_dma; 554 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 555 } __attribute__ ((aligned (32))); 556 557 /*-------------------------------------------------------------------------*/ 558 559 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 560 561 /* 562 * Some EHCI controllers have a Transaction Translator built into the 563 * root hub. This is a non-standard feature. Each controller will need 564 * to add code to the following inline functions, and call them as 565 * needed (mostly in root hub code). 566 */ 567 568 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 569 570 /* Returns the speed of a device attached to a port on the root hub. */ 571 static inline unsigned int 572 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 573 { 574 if (ehci_is_TDI(ehci)) { 575 switch ((portsc>>26)&3) { 576 case 0: 577 return 0; 578 case 1: 579 return (1<<USB_PORT_FEAT_LOWSPEED); 580 case 2: 581 default: 582 return (1<<USB_PORT_FEAT_HIGHSPEED); 583 } 584 } 585 return (1<<USB_PORT_FEAT_HIGHSPEED); 586 } 587 588 #else 589 590 #define ehci_is_TDI(e) (0) 591 592 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 593 #endif 594 595 /*-------------------------------------------------------------------------*/ 596 597 #ifdef CONFIG_PPC_83xx 598 /* Some Freescale processors have an erratum in which the TT 599 * port number in the queue head was 0..N-1 instead of 1..N. 600 */ 601 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 602 #else 603 #define ehci_has_fsl_portno_bug(e) (0) 604 #endif 605 606 /* 607 * While most USB host controllers implement their registers in 608 * little-endian format, a minority (celleb companion chip) implement 609 * them in big endian format. 610 * 611 * This attempts to support either format at compile time without a 612 * runtime penalty, or both formats with the additional overhead 613 * of checking a flag bit. 614 */ 615 616 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 617 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 618 #else 619 #define ehci_big_endian_mmio(e) 0 620 #endif 621 622 /* 623 * Big-endian read/write functions are arch-specific. 624 * Other arches can be added if/when they're needed. 625 */ 626 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 627 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 628 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 629 #endif 630 631 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 632 __u32 __iomem * regs) 633 { 634 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 635 return ehci_big_endian_mmio(ehci) ? 636 readl_be(regs) : 637 readl(regs); 638 #else 639 return readl(regs); 640 #endif 641 } 642 643 static inline void ehci_writel(const struct ehci_hcd *ehci, 644 const unsigned int val, __u32 __iomem *regs) 645 { 646 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 647 ehci_big_endian_mmio(ehci) ? 648 writel_be(val, regs) : 649 writel(val, regs); 650 #else 651 writel(val, regs); 652 #endif 653 } 654 655 /* 656 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 657 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 658 * Other common bits are dependant on has_amcc_usb23 quirk flag. 659 */ 660 #ifdef CONFIG_44x 661 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 662 { 663 u32 hc_control; 664 665 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 666 if (operational) 667 hc_control |= OHCI_USB_OPER; 668 else 669 hc_control |= OHCI_USB_SUSPEND; 670 671 writel_be(hc_control, ehci->ohci_hcctrl_reg); 672 (void) readl_be(ehci->ohci_hcctrl_reg); 673 } 674 #else 675 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 676 { } 677 #endif 678 679 /*-------------------------------------------------------------------------*/ 680 681 /* 682 * The AMCC 440EPx not only implements its EHCI registers in big-endian 683 * format, but also its DMA data structures (descriptors). 684 * 685 * EHCI controllers accessed through PCI work normally (little-endian 686 * everywhere), so we won't bother supporting a BE-only mode for now. 687 */ 688 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 689 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 690 691 /* cpu to ehci */ 692 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 693 { 694 return ehci_big_endian_desc(ehci) 695 ? (__force __hc32)cpu_to_be32(x) 696 : (__force __hc32)cpu_to_le32(x); 697 } 698 699 /* ehci to cpu */ 700 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 701 { 702 return ehci_big_endian_desc(ehci) 703 ? be32_to_cpu((__force __be32)x) 704 : le32_to_cpu((__force __le32)x); 705 } 706 707 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 708 { 709 return ehci_big_endian_desc(ehci) 710 ? be32_to_cpup((__force __be32 *)x) 711 : le32_to_cpup((__force __le32 *)x); 712 } 713 714 #else 715 716 /* cpu to ehci */ 717 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 718 { 719 return cpu_to_le32(x); 720 } 721 722 /* ehci to cpu */ 723 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 724 { 725 return le32_to_cpu(x); 726 } 727 728 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 729 { 730 return le32_to_cpup(x); 731 } 732 733 #endif 734 735 /*-------------------------------------------------------------------------*/ 736 737 #ifndef DEBUG 738 #define STUB_DEBUG_FILES 739 #endif /* DEBUG */ 740 741 /*-------------------------------------------------------------------------*/ 742 743 #endif /* __LINUX_EHCI_HCD_H */ 744