1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /*-------------------------------------------------------------------------*/ 26 27 /* called after powerup, by probe or system-pm "wakeup" */ 28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 29 { 30 u32 temp; 31 int retval; 32 33 /* optional debug port, normally in the first BAR */ 34 temp = pci_find_capability(pdev, 0x0a); 35 if (temp) { 36 pci_read_config_dword(pdev, temp, &temp); 37 temp >>= 16; 38 if ((temp & (3 << 13)) == (1 << 13)) { 39 temp &= 0x1fff; 40 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 41 temp = readl(&ehci->debug->control); 42 ehci_info(ehci, "debug port %d%s\n", 43 HCS_DEBUG_PORT(ehci->hcs_params), 44 (temp & DBGP_ENABLED) 45 ? " IN USE" 46 : ""); 47 if (!(temp & DBGP_ENABLED)) 48 ehci->debug = NULL; 49 } 50 } 51 52 /* we expect static quirk code to handle the "extended capabilities" 53 * (currently just BIOS handoff) allowed starting with EHCI 0.96 54 */ 55 56 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 57 retval = pci_set_mwi(pdev); 58 if (!retval) 59 ehci_dbg(ehci, "MWI active\n"); 60 61 ehci_port_power(ehci, 0); 62 63 return 0; 64 } 65 66 /* called during probe() after chip reset completes */ 67 static int ehci_pci_setup(struct usb_hcd *hcd) 68 { 69 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 70 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 71 u32 temp; 72 int retval; 73 74 ehci->caps = hcd->regs; 75 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); 76 dbg_hcs_params(ehci, "reset"); 77 dbg_hcc_params(ehci, "reset"); 78 79 /* ehci_init() causes memory for DMA transfers to be 80 * allocated. Thus, any vendor-specific workarounds based on 81 * limiting the type of memory used for DMA transfers must 82 * happen before ehci_init() is called. */ 83 switch (pdev->vendor) { 84 case PCI_VENDOR_ID_NVIDIA: 85 /* NVidia reports that certain chips don't handle 86 * QH, ITD, or SITD addresses above 2GB. (But TD, 87 * data buffer, and periodic schedule are normal.) 88 */ 89 switch (pdev->device) { 90 case 0x003c: /* MCP04 */ 91 case 0x005b: /* CK804 */ 92 case 0x00d8: /* CK8 */ 93 case 0x00e8: /* CK8S */ 94 if (pci_set_consistent_dma_mask(pdev, 95 DMA_31BIT_MASK) < 0) 96 ehci_warn(ehci, "can't enable NVidia " 97 "workaround for >2GB RAM\n"); 98 break; 99 } 100 break; 101 } 102 103 /* cache this readonly data; minimize chip reads */ 104 ehci->hcs_params = readl(&ehci->caps->hcs_params); 105 106 retval = ehci_halt(ehci); 107 if (retval) 108 return retval; 109 110 /* data structure init */ 111 retval = ehci_init(hcd); 112 if (retval) 113 return retval; 114 115 switch (pdev->vendor) { 116 case PCI_VENDOR_ID_TDI: 117 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 118 ehci->is_tdi_rh_tt = 1; 119 tdi_reset(ehci); 120 } 121 break; 122 case PCI_VENDOR_ID_AMD: 123 /* AMD8111 EHCI doesn't work, according to AMD errata */ 124 if (pdev->device == 0x7463) { 125 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 126 retval = -EIO; 127 goto done; 128 } 129 break; 130 case PCI_VENDOR_ID_NVIDIA: 131 switch (pdev->device) { 132 /* Some NForce2 chips have problems with selective suspend; 133 * fixed in newer silicon. 134 */ 135 case 0x0068: 136 pci_read_config_dword(pdev, PCI_REVISION_ID, &temp); 137 if ((temp & 0xff) < 0xa4) 138 ehci->no_selective_suspend = 1; 139 break; 140 } 141 break; 142 } 143 144 if (ehci_is_TDI(ehci)) 145 ehci_reset(ehci); 146 147 /* at least the Genesys GL880S needs fixup here */ 148 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 149 temp &= 0x0f; 150 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 151 ehci_dbg(ehci, "bogus port configuration: " 152 "cc=%d x pcc=%d < ports=%d\n", 153 HCS_N_CC(ehci->hcs_params), 154 HCS_N_PCC(ehci->hcs_params), 155 HCS_N_PORTS(ehci->hcs_params)); 156 157 switch (pdev->vendor) { 158 case 0x17a0: /* GENESYS */ 159 /* GL880S: should be PORTS=2 */ 160 temp |= (ehci->hcs_params & ~0xf); 161 ehci->hcs_params = temp; 162 break; 163 case PCI_VENDOR_ID_NVIDIA: 164 /* NF4: should be PCC=10 */ 165 break; 166 } 167 } 168 169 /* Serial Bus Release Number is at PCI 0x60 offset */ 170 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 171 172 /* Workaround current PCI init glitch: wakeup bits aren't 173 * being set from PCI PM capability. 174 */ 175 if (!device_can_wakeup(&pdev->dev)) { 176 u16 port_wake; 177 178 pci_read_config_word(pdev, 0x62, &port_wake); 179 if (port_wake & 0x0001) 180 device_init_wakeup(&pdev->dev, 1); 181 } 182 183 #ifdef CONFIG_USB_SUSPEND 184 /* REVISIT: the controller works fine for wakeup iff the root hub 185 * itself is "globally" suspended, but usbcore currently doesn't 186 * understand such things. 187 * 188 * System suspend currently expects to be able to suspend the entire 189 * device tree, device-at-a-time. If we failed selective suspend 190 * reports, system suspend would fail; so the root hub code must claim 191 * success. That's lying to usbcore, and it matters for for runtime 192 * PM scenarios with selective suspend and remote wakeup... 193 */ 194 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 195 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 196 #endif 197 198 retval = ehci_pci_reinit(ehci, pdev); 199 done: 200 return retval; 201 } 202 203 /*-------------------------------------------------------------------------*/ 204 205 #ifdef CONFIG_PM 206 207 /* suspend/resume, section 4.3 */ 208 209 /* These routines rely on the PCI bus glue 210 * to handle powerdown and wakeup, and currently also on 211 * transceivers that don't need any software attention to set up 212 * the right sort of wakeup. 213 * Also they depend on separate root hub suspend/resume. 214 */ 215 216 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) 217 { 218 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 219 unsigned long flags; 220 int rc = 0; 221 222 if (time_before(jiffies, ehci->next_statechange)) 223 msleep(10); 224 225 /* Root hub was already suspended. Disable irq emission and 226 * mark HW unaccessible, bail out if RH has been resumed. Use 227 * the spinlock to properly synchronize with possible pending 228 * RH suspend or resume activity. 229 * 230 * This is still racy as hcd->state is manipulated outside of 231 * any locks =P But that will be a different fix. 232 */ 233 spin_lock_irqsave (&ehci->lock, flags); 234 if (hcd->state != HC_STATE_SUSPENDED) { 235 rc = -EINVAL; 236 goto bail; 237 } 238 writel (0, &ehci->regs->intr_enable); 239 (void)readl(&ehci->regs->intr_enable); 240 241 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 242 bail: 243 spin_unlock_irqrestore (&ehci->lock, flags); 244 245 // could save FLADJ in case of Vaux power loss 246 // ... we'd only use it to handle clock skew 247 248 return rc; 249 } 250 251 static int ehci_pci_resume(struct usb_hcd *hcd) 252 { 253 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 254 unsigned port; 255 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 256 int retval = -EINVAL; 257 258 // maybe restore FLADJ 259 260 if (time_before(jiffies, ehci->next_statechange)) 261 msleep(100); 262 263 /* Mark hardware accessible again as we are out of D3 state by now */ 264 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 265 266 /* If CF is clear, we lost PCI Vaux power and need to restart. */ 267 if (readl(&ehci->regs->configured_flag) != FLAG_CF) 268 goto restart; 269 270 /* If any port is suspended (or owned by the companion), 271 * we know we can/must resume the HC (and mustn't reset it). 272 * We just defer that to the root hub code. 273 */ 274 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { 275 u32 status; 276 port--; 277 status = readl(&ehci->regs->port_status [port]); 278 if (!(status & PORT_POWER)) 279 continue; 280 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { 281 usb_hcd_resume_root_hub(hcd); 282 return 0; 283 } 284 } 285 286 restart: 287 ehci_dbg(ehci, "lost power, restarting\n"); 288 usb_root_hub_lost_power(hcd->self.root_hub); 289 290 /* Else reset, to cope with power loss or flush-to-storage 291 * style "resume" having let BIOS kick in during reboot. 292 */ 293 (void) ehci_halt(ehci); 294 (void) ehci_reset(ehci); 295 (void) ehci_pci_reinit(ehci, pdev); 296 297 /* emptying the schedule aborts any urbs */ 298 spin_lock_irq(&ehci->lock); 299 if (ehci->reclaim) 300 ehci->reclaim_ready = 1; 301 ehci_work(ehci, NULL); 302 spin_unlock_irq(&ehci->lock); 303 304 /* restart; khubd will disconnect devices */ 305 retval = ehci_run(hcd); 306 307 /* here we "know" root ports should always stay powered */ 308 ehci_port_power(ehci, 1); 309 310 return retval; 311 } 312 #endif 313 314 static const struct hc_driver ehci_pci_hc_driver = { 315 .description = hcd_name, 316 .product_desc = "EHCI Host Controller", 317 .hcd_priv_size = sizeof(struct ehci_hcd), 318 319 /* 320 * generic hardware linkage 321 */ 322 .irq = ehci_irq, 323 .flags = HCD_MEMORY | HCD_USB2, 324 325 /* 326 * basic lifecycle operations 327 */ 328 .reset = ehci_pci_setup, 329 .start = ehci_run, 330 #ifdef CONFIG_PM 331 .suspend = ehci_pci_suspend, 332 .resume = ehci_pci_resume, 333 #endif 334 .stop = ehci_stop, 335 336 /* 337 * managing i/o requests and associated device resources 338 */ 339 .urb_enqueue = ehci_urb_enqueue, 340 .urb_dequeue = ehci_urb_dequeue, 341 .endpoint_disable = ehci_endpoint_disable, 342 343 /* 344 * scheduling support 345 */ 346 .get_frame_number = ehci_get_frame, 347 348 /* 349 * root hub support 350 */ 351 .hub_status_data = ehci_hub_status_data, 352 .hub_control = ehci_hub_control, 353 .bus_suspend = ehci_bus_suspend, 354 .bus_resume = ehci_bus_resume, 355 }; 356 357 /*-------------------------------------------------------------------------*/ 358 359 /* PCI driver selection metadata; PCI hotplugging uses this */ 360 static const struct pci_device_id pci_ids [] = { { 361 /* handle any USB 2.0 EHCI controller */ 362 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 363 .driver_data = (unsigned long) &ehci_pci_hc_driver, 364 }, 365 { /* end: all zeroes */ } 366 }; 367 MODULE_DEVICE_TABLE(pci, pci_ids); 368 369 /* pci driver glue; this is a "new style" PCI driver module */ 370 static struct pci_driver ehci_pci_driver = { 371 .name = (char *) hcd_name, 372 .id_table = pci_ids, 373 374 .probe = usb_hcd_pci_probe, 375 .remove = usb_hcd_pci_remove, 376 377 #ifdef CONFIG_PM 378 .suspend = usb_hcd_pci_suspend, 379 .resume = usb_hcd_pci_resume, 380 #endif 381 }; 382