1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /*-------------------------------------------------------------------------*/ 26 27 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/... 28 * off the controller (maybe it can boot from highspeed USB disks). 29 */ 30 static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap) 31 { 32 struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller); 33 34 /* always say Linux will own the hardware */ 35 pci_write_config_byte(pdev, where + 3, 1); 36 37 /* maybe wait a while for BIOS to respond */ 38 if (cap & (1 << 16)) { 39 int msec = 5000; 40 41 do { 42 msleep(10); 43 msec -= 10; 44 pci_read_config_dword(pdev, where, &cap); 45 } while ((cap & (1 << 16)) && msec); 46 if (cap & (1 << 16)) { 47 ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n", 48 where, cap); 49 // some BIOS versions seem buggy... 50 // return 1; 51 ehci_warn(ehci, "continuing after BIOS bug...\n"); 52 /* disable all SMIs, and clear "BIOS owns" flag */ 53 pci_write_config_dword(pdev, where + 4, 0); 54 pci_write_config_byte(pdev, where + 2, 0); 55 } else 56 ehci_dbg(ehci, "BIOS handoff succeeded\n"); 57 } 58 return 0; 59 } 60 61 /* called after powerup, by probe or system-pm "wakeup" */ 62 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 63 { 64 u32 temp; 65 int retval; 66 unsigned count = 256/4; 67 68 /* optional debug port, normally in the first BAR */ 69 temp = pci_find_capability(pdev, 0x0a); 70 if (temp) { 71 pci_read_config_dword(pdev, temp, &temp); 72 temp >>= 16; 73 if ((temp & (3 << 13)) == (1 << 13)) { 74 temp &= 0x1fff; 75 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 76 temp = readl(&ehci->debug->control); 77 ehci_info(ehci, "debug port %d%s\n", 78 HCS_DEBUG_PORT(ehci->hcs_params), 79 (temp & DBGP_ENABLED) 80 ? " IN USE" 81 : ""); 82 if (!(temp & DBGP_ENABLED)) 83 ehci->debug = NULL; 84 } 85 } 86 87 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params)); 88 89 /* EHCI 0.96 and later may have "extended capabilities" */ 90 while (temp && count--) { 91 u32 cap; 92 93 pci_read_config_dword(pdev, temp, &cap); 94 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp); 95 switch (cap & 0xff) { 96 case 1: /* BIOS/SMM/... handoff */ 97 if (bios_handoff(ehci, temp, cap) != 0) 98 return -EOPNOTSUPP; 99 break; 100 case 0: /* illegal reserved capability */ 101 ehci_dbg(ehci, "illegal capability!\n"); 102 cap = 0; 103 /* FALLTHROUGH */ 104 default: /* unknown */ 105 break; 106 } 107 temp = (cap >> 8) & 0xff; 108 } 109 if (!count) { 110 ehci_err(ehci, "bogus capabilities ... PCI problems!\n"); 111 return -EIO; 112 } 113 114 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 115 retval = pci_set_mwi(pdev); 116 if (!retval) 117 ehci_dbg(ehci, "MWI active\n"); 118 119 ehci_port_power(ehci, 0); 120 121 return 0; 122 } 123 124 /* called during probe() after chip reset completes */ 125 static int ehci_pci_setup(struct usb_hcd *hcd) 126 { 127 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 128 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 129 u32 temp; 130 int retval; 131 132 ehci->caps = hcd->regs; 133 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); 134 dbg_hcs_params(ehci, "reset"); 135 dbg_hcc_params(ehci, "reset"); 136 137 /* cache this readonly data; minimize chip reads */ 138 ehci->hcs_params = readl(&ehci->caps->hcs_params); 139 140 retval = ehci_halt(ehci); 141 if (retval) 142 return retval; 143 144 /* data structure init */ 145 retval = ehci_init(hcd); 146 if (retval) 147 return retval; 148 149 /* NOTE: only the parts below this line are PCI-specific */ 150 151 switch (pdev->vendor) { 152 case PCI_VENDOR_ID_TDI: 153 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 154 ehci->is_tdi_rh_tt = 1; 155 tdi_reset(ehci); 156 } 157 break; 158 case PCI_VENDOR_ID_AMD: 159 /* AMD8111 EHCI doesn't work, according to AMD errata */ 160 if (pdev->device == 0x7463) { 161 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 162 retval = -EIO; 163 goto done; 164 } 165 break; 166 case PCI_VENDOR_ID_NVIDIA: 167 /* NVidia reports that certain chips don't handle 168 * QH, ITD, or SITD addresses above 2GB. (But TD, 169 * data buffer, and periodic schedule are normal.) 170 */ 171 switch (pdev->device) { 172 case 0x003c: /* MCP04 */ 173 case 0x005b: /* CK804 */ 174 case 0x00d8: /* CK8 */ 175 case 0x00e8: /* CK8S */ 176 if (pci_set_consistent_dma_mask(pdev, 177 DMA_31BIT_MASK) < 0) 178 ehci_warn(ehci, "can't enable NVidia " 179 "workaround for >2GB RAM\n"); 180 break; 181 } 182 break; 183 } 184 185 if (ehci_is_TDI(ehci)) 186 ehci_reset(ehci); 187 188 /* at least the Genesys GL880S needs fixup here */ 189 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 190 temp &= 0x0f; 191 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 192 ehci_dbg(ehci, "bogus port configuration: " 193 "cc=%d x pcc=%d < ports=%d\n", 194 HCS_N_CC(ehci->hcs_params), 195 HCS_N_PCC(ehci->hcs_params), 196 HCS_N_PORTS(ehci->hcs_params)); 197 198 switch (pdev->vendor) { 199 case 0x17a0: /* GENESYS */ 200 /* GL880S: should be PORTS=2 */ 201 temp |= (ehci->hcs_params & ~0xf); 202 ehci->hcs_params = temp; 203 break; 204 case PCI_VENDOR_ID_NVIDIA: 205 /* NF4: should be PCC=10 */ 206 break; 207 } 208 } 209 210 /* Serial Bus Release Number is at PCI 0x60 offset */ 211 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 212 213 /* REVISIT: per-port wake capability (PCI 0x62) currently unused */ 214 215 retval = ehci_pci_reinit(ehci, pdev); 216 done: 217 return retval; 218 } 219 220 /*-------------------------------------------------------------------------*/ 221 222 #ifdef CONFIG_PM 223 224 /* suspend/resume, section 4.3 */ 225 226 /* These routines rely on the PCI bus glue 227 * to handle powerdown and wakeup, and currently also on 228 * transceivers that don't need any software attention to set up 229 * the right sort of wakeup. 230 * Also they depend on separate root hub suspend/resume. 231 */ 232 233 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) 234 { 235 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 236 unsigned long flags; 237 int rc = 0; 238 239 if (time_before(jiffies, ehci->next_statechange)) 240 msleep(10); 241 242 /* Root hub was already suspended. Disable irq emission and 243 * mark HW unaccessible, bail out if RH has been resumed. Use 244 * the spinlock to properly synchronize with possible pending 245 * RH suspend or resume activity. 246 * 247 * This is still racy as hcd->state is manipulated outside of 248 * any locks =P But that will be a different fix. 249 */ 250 spin_lock_irqsave (&ehci->lock, flags); 251 if (hcd->state != HC_STATE_SUSPENDED) { 252 rc = -EINVAL; 253 goto bail; 254 } 255 writel (0, &ehci->regs->intr_enable); 256 (void)readl(&ehci->regs->intr_enable); 257 258 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 259 bail: 260 spin_unlock_irqrestore (&ehci->lock, flags); 261 262 // could save FLADJ in case of Vaux power loss 263 // ... we'd only use it to handle clock skew 264 265 return rc; 266 } 267 268 static int ehci_pci_resume(struct usb_hcd *hcd) 269 { 270 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 271 unsigned port; 272 struct usb_device *root = hcd->self.root_hub; 273 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 274 int retval = -EINVAL; 275 276 // maybe restore FLADJ 277 278 if (time_before(jiffies, ehci->next_statechange)) 279 msleep(100); 280 281 /* Mark hardware accessible again as we are out of D3 state by now */ 282 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 283 284 /* If CF is clear, we lost PCI Vaux power and need to restart. */ 285 if (readl(&ehci->regs->configured_flag) != FLAG_CF) 286 goto restart; 287 288 /* If any port is suspended (or owned by the companion), 289 * we know we can/must resume the HC (and mustn't reset it). 290 * We just defer that to the root hub code. 291 */ 292 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { 293 u32 status; 294 port--; 295 status = readl(&ehci->regs->port_status [port]); 296 if (!(status & PORT_POWER)) 297 continue; 298 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { 299 usb_hcd_resume_root_hub(hcd); 300 return 0; 301 } 302 } 303 304 restart: 305 ehci_dbg(ehci, "lost power, restarting\n"); 306 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { 307 port--; 308 if (!root->children [port]) 309 continue; 310 usb_set_device_state(root->children[port], 311 USB_STATE_NOTATTACHED); 312 } 313 314 /* Else reset, to cope with power loss or flush-to-storage 315 * style "resume" having let BIOS kick in during reboot. 316 */ 317 (void) ehci_halt(ehci); 318 (void) ehci_reset(ehci); 319 (void) ehci_pci_reinit(ehci, pdev); 320 321 /* emptying the schedule aborts any urbs */ 322 spin_lock_irq(&ehci->lock); 323 if (ehci->reclaim) 324 ehci->reclaim_ready = 1; 325 ehci_work(ehci, NULL); 326 spin_unlock_irq(&ehci->lock); 327 328 /* restart; khubd will disconnect devices */ 329 retval = ehci_run(hcd); 330 331 /* here we "know" root ports should always stay powered */ 332 ehci_port_power(ehci, 1); 333 334 return retval; 335 } 336 #endif 337 338 static const struct hc_driver ehci_pci_hc_driver = { 339 .description = hcd_name, 340 .product_desc = "EHCI Host Controller", 341 .hcd_priv_size = sizeof(struct ehci_hcd), 342 343 /* 344 * generic hardware linkage 345 */ 346 .irq = ehci_irq, 347 .flags = HCD_MEMORY | HCD_USB2, 348 349 /* 350 * basic lifecycle operations 351 */ 352 .reset = ehci_pci_setup, 353 .start = ehci_run, 354 #ifdef CONFIG_PM 355 .suspend = ehci_pci_suspend, 356 .resume = ehci_pci_resume, 357 #endif 358 .stop = ehci_stop, 359 360 /* 361 * managing i/o requests and associated device resources 362 */ 363 .urb_enqueue = ehci_urb_enqueue, 364 .urb_dequeue = ehci_urb_dequeue, 365 .endpoint_disable = ehci_endpoint_disable, 366 367 /* 368 * scheduling support 369 */ 370 .get_frame_number = ehci_get_frame, 371 372 /* 373 * root hub support 374 */ 375 .hub_status_data = ehci_hub_status_data, 376 .hub_control = ehci_hub_control, 377 .bus_suspend = ehci_bus_suspend, 378 .bus_resume = ehci_bus_resume, 379 }; 380 381 /*-------------------------------------------------------------------------*/ 382 383 /* PCI driver selection metadata; PCI hotplugging uses this */ 384 static const struct pci_device_id pci_ids [] = { { 385 /* handle any USB 2.0 EHCI controller */ 386 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0), 387 .driver_data = (unsigned long) &ehci_pci_hc_driver, 388 }, 389 { /* end: all zeroes */ } 390 }; 391 MODULE_DEVICE_TABLE(pci, pci_ids); 392 393 /* pci driver glue; this is a "new style" PCI driver module */ 394 static struct pci_driver ehci_pci_driver = { 395 .name = (char *) hcd_name, 396 .id_table = pci_ids, 397 398 .probe = usb_hcd_pci_probe, 399 .remove = usb_hcd_pci_remove, 400 401 #ifdef CONFIG_PM 402 .suspend = usb_hcd_pci_suspend, 403 .resume = usb_hcd_pci_resume, 404 #endif 405 }; 406 407 static int __init ehci_hcd_pci_init(void) 408 { 409 if (usb_disabled()) 410 return -ENODEV; 411 412 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 413 hcd_name, 414 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 415 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 416 417 return pci_register_driver(&ehci_pci_driver); 418 } 419 module_init(ehci_hcd_pci_init); 420 421 static void __exit ehci_hcd_pci_cleanup(void) 422 { 423 pci_unregister_driver(&ehci_pci_driver); 424 } 425 module_exit(ehci_hcd_pci_cleanup); 426