1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /*-------------------------------------------------------------------------*/ 26 27 /* called after powerup, by probe or system-pm "wakeup" */ 28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 29 { 30 u32 temp; 31 int retval; 32 33 /* optional debug port, normally in the first BAR */ 34 temp = pci_find_capability(pdev, 0x0a); 35 if (temp) { 36 pci_read_config_dword(pdev, temp, &temp); 37 temp >>= 16; 38 if ((temp & (3 << 13)) == (1 << 13)) { 39 temp &= 0x1fff; 40 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 41 temp = readl(&ehci->debug->control); 42 ehci_info(ehci, "debug port %d%s\n", 43 HCS_DEBUG_PORT(ehci->hcs_params), 44 (temp & DBGP_ENABLED) 45 ? " IN USE" 46 : ""); 47 if (!(temp & DBGP_ENABLED)) 48 ehci->debug = NULL; 49 } 50 } 51 52 /* we expect static quirk code to handle the "extended capabilities" 53 * (currently just BIOS handoff) allowed starting with EHCI 0.96 54 */ 55 56 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 57 retval = pci_set_mwi(pdev); 58 if (!retval) 59 ehci_dbg(ehci, "MWI active\n"); 60 61 ehci_port_power(ehci, 0); 62 63 return 0; 64 } 65 66 /* called during probe() after chip reset completes */ 67 static int ehci_pci_setup(struct usb_hcd *hcd) 68 { 69 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 70 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 71 u32 temp; 72 int retval; 73 74 ehci->caps = hcd->regs; 75 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); 76 dbg_hcs_params(ehci, "reset"); 77 dbg_hcc_params(ehci, "reset"); 78 79 /* cache this readonly data; minimize chip reads */ 80 ehci->hcs_params = readl(&ehci->caps->hcs_params); 81 82 retval = ehci_halt(ehci); 83 if (retval) 84 return retval; 85 86 /* data structure init */ 87 retval = ehci_init(hcd); 88 if (retval) 89 return retval; 90 91 /* NOTE: only the parts below this line are PCI-specific */ 92 93 switch (pdev->vendor) { 94 case PCI_VENDOR_ID_TDI: 95 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 96 ehci->is_tdi_rh_tt = 1; 97 tdi_reset(ehci); 98 } 99 break; 100 case PCI_VENDOR_ID_AMD: 101 /* AMD8111 EHCI doesn't work, according to AMD errata */ 102 if (pdev->device == 0x7463) { 103 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 104 retval = -EIO; 105 goto done; 106 } 107 break; 108 case PCI_VENDOR_ID_NVIDIA: 109 switch (pdev->device) { 110 /* NVidia reports that certain chips don't handle 111 * QH, ITD, or SITD addresses above 2GB. (But TD, 112 * data buffer, and periodic schedule are normal.) 113 */ 114 case 0x003c: /* MCP04 */ 115 case 0x005b: /* CK804 */ 116 case 0x00d8: /* CK8 */ 117 case 0x00e8: /* CK8S */ 118 if (pci_set_consistent_dma_mask(pdev, 119 DMA_31BIT_MASK) < 0) 120 ehci_warn(ehci, "can't enable NVidia " 121 "workaround for >2GB RAM\n"); 122 break; 123 /* Some NForce2 chips have problems with selective suspend; 124 * fixed in newer silicon. 125 */ 126 case 0x0068: 127 pci_read_config_dword(pdev, PCI_REVISION_ID, &temp); 128 if ((temp & 0xff) < 0xa4) 129 ehci->no_selective_suspend = 1; 130 break; 131 } 132 break; 133 } 134 135 if (ehci_is_TDI(ehci)) 136 ehci_reset(ehci); 137 138 /* at least the Genesys GL880S needs fixup here */ 139 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 140 temp &= 0x0f; 141 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 142 ehci_dbg(ehci, "bogus port configuration: " 143 "cc=%d x pcc=%d < ports=%d\n", 144 HCS_N_CC(ehci->hcs_params), 145 HCS_N_PCC(ehci->hcs_params), 146 HCS_N_PORTS(ehci->hcs_params)); 147 148 switch (pdev->vendor) { 149 case 0x17a0: /* GENESYS */ 150 /* GL880S: should be PORTS=2 */ 151 temp |= (ehci->hcs_params & ~0xf); 152 ehci->hcs_params = temp; 153 break; 154 case PCI_VENDOR_ID_NVIDIA: 155 /* NF4: should be PCC=10 */ 156 break; 157 } 158 } 159 160 /* Serial Bus Release Number is at PCI 0x60 offset */ 161 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 162 163 /* Workaround current PCI init glitch: wakeup bits aren't 164 * being set from PCI PM capability. 165 */ 166 if (!device_can_wakeup(&pdev->dev)) { 167 u16 port_wake; 168 169 pci_read_config_word(pdev, 0x62, &port_wake); 170 if (port_wake & 0x0001) 171 device_init_wakeup(&pdev->dev, 1); 172 } 173 174 #ifdef CONFIG_USB_SUSPEND 175 /* REVISIT: the controller works fine for wakeup iff the root hub 176 * itself is "globally" suspended, but usbcore currently doesn't 177 * understand such things. 178 * 179 * System suspend currently expects to be able to suspend the entire 180 * device tree, device-at-a-time. If we failed selective suspend 181 * reports, system suspend would fail; so the root hub code must claim 182 * success. That's lying to usbcore, and it matters for for runtime 183 * PM scenarios with selective suspend and remote wakeup... 184 */ 185 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 186 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 187 #endif 188 189 retval = ehci_pci_reinit(ehci, pdev); 190 done: 191 return retval; 192 } 193 194 /*-------------------------------------------------------------------------*/ 195 196 #ifdef CONFIG_PM 197 198 /* suspend/resume, section 4.3 */ 199 200 /* These routines rely on the PCI bus glue 201 * to handle powerdown and wakeup, and currently also on 202 * transceivers that don't need any software attention to set up 203 * the right sort of wakeup. 204 * Also they depend on separate root hub suspend/resume. 205 */ 206 207 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) 208 { 209 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 210 unsigned long flags; 211 int rc = 0; 212 213 if (time_before(jiffies, ehci->next_statechange)) 214 msleep(10); 215 216 /* Root hub was already suspended. Disable irq emission and 217 * mark HW unaccessible, bail out if RH has been resumed. Use 218 * the spinlock to properly synchronize with possible pending 219 * RH suspend or resume activity. 220 * 221 * This is still racy as hcd->state is manipulated outside of 222 * any locks =P But that will be a different fix. 223 */ 224 spin_lock_irqsave (&ehci->lock, flags); 225 if (hcd->state != HC_STATE_SUSPENDED) { 226 rc = -EINVAL; 227 goto bail; 228 } 229 writel (0, &ehci->regs->intr_enable); 230 (void)readl(&ehci->regs->intr_enable); 231 232 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 233 bail: 234 spin_unlock_irqrestore (&ehci->lock, flags); 235 236 // could save FLADJ in case of Vaux power loss 237 // ... we'd only use it to handle clock skew 238 239 return rc; 240 } 241 242 static int ehci_pci_resume(struct usb_hcd *hcd) 243 { 244 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 245 unsigned port; 246 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 247 int retval = -EINVAL; 248 249 // maybe restore FLADJ 250 251 if (time_before(jiffies, ehci->next_statechange)) 252 msleep(100); 253 254 /* Mark hardware accessible again as we are out of D3 state by now */ 255 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 256 257 /* If CF is clear, we lost PCI Vaux power and need to restart. */ 258 if (readl(&ehci->regs->configured_flag) != FLAG_CF) 259 goto restart; 260 261 /* If any port is suspended (or owned by the companion), 262 * we know we can/must resume the HC (and mustn't reset it). 263 * We just defer that to the root hub code. 264 */ 265 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { 266 u32 status; 267 port--; 268 status = readl(&ehci->regs->port_status [port]); 269 if (!(status & PORT_POWER)) 270 continue; 271 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { 272 usb_hcd_resume_root_hub(hcd); 273 return 0; 274 } 275 } 276 277 restart: 278 ehci_dbg(ehci, "lost power, restarting\n"); 279 usb_root_hub_lost_power(hcd->self.root_hub); 280 281 /* Else reset, to cope with power loss or flush-to-storage 282 * style "resume" having let BIOS kick in during reboot. 283 */ 284 (void) ehci_halt(ehci); 285 (void) ehci_reset(ehci); 286 (void) ehci_pci_reinit(ehci, pdev); 287 288 /* emptying the schedule aborts any urbs */ 289 spin_lock_irq(&ehci->lock); 290 if (ehci->reclaim) 291 ehci->reclaim_ready = 1; 292 ehci_work(ehci, NULL); 293 spin_unlock_irq(&ehci->lock); 294 295 /* restart; khubd will disconnect devices */ 296 retval = ehci_run(hcd); 297 298 /* here we "know" root ports should always stay powered */ 299 ehci_port_power(ehci, 1); 300 301 return retval; 302 } 303 #endif 304 305 static const struct hc_driver ehci_pci_hc_driver = { 306 .description = hcd_name, 307 .product_desc = "EHCI Host Controller", 308 .hcd_priv_size = sizeof(struct ehci_hcd), 309 310 /* 311 * generic hardware linkage 312 */ 313 .irq = ehci_irq, 314 .flags = HCD_MEMORY | HCD_USB2, 315 316 /* 317 * basic lifecycle operations 318 */ 319 .reset = ehci_pci_setup, 320 .start = ehci_run, 321 #ifdef CONFIG_PM 322 .suspend = ehci_pci_suspend, 323 .resume = ehci_pci_resume, 324 #endif 325 .stop = ehci_stop, 326 327 /* 328 * managing i/o requests and associated device resources 329 */ 330 .urb_enqueue = ehci_urb_enqueue, 331 .urb_dequeue = ehci_urb_dequeue, 332 .endpoint_disable = ehci_endpoint_disable, 333 334 /* 335 * scheduling support 336 */ 337 .get_frame_number = ehci_get_frame, 338 339 /* 340 * root hub support 341 */ 342 .hub_status_data = ehci_hub_status_data, 343 .hub_control = ehci_hub_control, 344 .bus_suspend = ehci_bus_suspend, 345 .bus_resume = ehci_bus_resume, 346 }; 347 348 /*-------------------------------------------------------------------------*/ 349 350 /* PCI driver selection metadata; PCI hotplugging uses this */ 351 static const struct pci_device_id pci_ids [] = { { 352 /* handle any USB 2.0 EHCI controller */ 353 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 354 .driver_data = (unsigned long) &ehci_pci_hc_driver, 355 }, 356 { /* end: all zeroes */ } 357 }; 358 MODULE_DEVICE_TABLE(pci, pci_ids); 359 360 /* pci driver glue; this is a "new style" PCI driver module */ 361 static struct pci_driver ehci_pci_driver = { 362 .name = (char *) hcd_name, 363 .id_table = pci_ids, 364 365 .probe = usb_hcd_pci_probe, 366 .remove = usb_hcd_pci_remove, 367 368 #ifdef CONFIG_PM 369 .suspend = usb_hcd_pci_suspend, 370 .resume = usb_hcd_pci_resume, 371 #endif 372 }; 373 374 static int __init ehci_hcd_pci_init(void) 375 { 376 if (usb_disabled()) 377 return -ENODEV; 378 379 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 380 hcd_name, 381 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 382 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 383 384 return pci_register_driver(&ehci_pci_driver); 385 } 386 module_init(ehci_hcd_pci_init); 387 388 static void __exit ehci_hcd_pci_cleanup(void) 389 { 390 pci_unregister_driver(&ehci_pci_driver); 391 } 392 module_exit(ehci_hcd_pci_cleanup); 393