1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /*-------------------------------------------------------------------------*/ 26 27 /* called after powerup, by probe or system-pm "wakeup" */ 28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 29 { 30 int retval; 31 32 /* we expect static quirk code to handle the "extended capabilities" 33 * (currently just BIOS handoff) allowed starting with EHCI 0.96 34 */ 35 36 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 37 retval = pci_set_mwi(pdev); 38 if (!retval) 39 ehci_dbg(ehci, "MWI active\n"); 40 41 return 0; 42 } 43 44 /* called during probe() after chip reset completes */ 45 static int ehci_pci_setup(struct usb_hcd *hcd) 46 { 47 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 48 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 49 struct pci_dev *p_smbus; 50 u8 rev; 51 u32 temp; 52 int retval; 53 54 switch (pdev->vendor) { 55 case PCI_VENDOR_ID_TOSHIBA_2: 56 /* celleb's companion chip */ 57 if (pdev->device == 0x01b5) { 58 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 59 ehci->big_endian_mmio = 1; 60 #else 61 ehci_warn(ehci, 62 "unsupported big endian Toshiba quirk\n"); 63 #endif 64 } 65 break; 66 } 67 68 ehci->caps = hcd->regs; 69 ehci->regs = hcd->regs + 70 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 71 72 dbg_hcs_params(ehci, "reset"); 73 dbg_hcc_params(ehci, "reset"); 74 75 /* ehci_init() causes memory for DMA transfers to be 76 * allocated. Thus, any vendor-specific workarounds based on 77 * limiting the type of memory used for DMA transfers must 78 * happen before ehci_init() is called. */ 79 switch (pdev->vendor) { 80 case PCI_VENDOR_ID_NVIDIA: 81 /* NVidia reports that certain chips don't handle 82 * QH, ITD, or SITD addresses above 2GB. (But TD, 83 * data buffer, and periodic schedule are normal.) 84 */ 85 switch (pdev->device) { 86 case 0x003c: /* MCP04 */ 87 case 0x005b: /* CK804 */ 88 case 0x00d8: /* CK8 */ 89 case 0x00e8: /* CK8S */ 90 if (pci_set_consistent_dma_mask(pdev, 91 DMA_BIT_MASK(31)) < 0) 92 ehci_warn(ehci, "can't enable NVidia " 93 "workaround for >2GB RAM\n"); 94 break; 95 } 96 break; 97 } 98 99 /* cache this readonly data; minimize chip reads */ 100 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 101 102 retval = ehci_halt(ehci); 103 if (retval) 104 return retval; 105 106 /* data structure init */ 107 retval = ehci_init(hcd); 108 if (retval) 109 return retval; 110 111 switch (pdev->vendor) { 112 case PCI_VENDOR_ID_NEC: 113 ehci->need_io_watchdog = 0; 114 break; 115 case PCI_VENDOR_ID_INTEL: 116 ehci->need_io_watchdog = 0; 117 if (pdev->device == 0x27cc) { 118 ehci->broken_periodic = 1; 119 ehci_info(ehci, "using broken periodic workaround\n"); 120 } 121 break; 122 case PCI_VENDOR_ID_TDI: 123 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 124 hcd->has_tt = 1; 125 tdi_reset(ehci); 126 } 127 break; 128 case PCI_VENDOR_ID_AMD: 129 /* AMD8111 EHCI doesn't work, according to AMD errata */ 130 if (pdev->device == 0x7463) { 131 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 132 retval = -EIO; 133 goto done; 134 } 135 break; 136 case PCI_VENDOR_ID_NVIDIA: 137 switch (pdev->device) { 138 /* Some NForce2 chips have problems with selective suspend; 139 * fixed in newer silicon. 140 */ 141 case 0x0068: 142 if (pdev->revision < 0xa4) 143 ehci->no_selective_suspend = 1; 144 break; 145 } 146 break; 147 case PCI_VENDOR_ID_VIA: 148 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 149 u8 tmp; 150 151 /* The VT6212 defaults to a 1 usec EHCI sleep time which 152 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 153 * that sleep time use the conventional 10 usec. 154 */ 155 pci_read_config_byte(pdev, 0x4b, &tmp); 156 if (tmp & 0x20) 157 break; 158 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 159 } 160 break; 161 case PCI_VENDOR_ID_ATI: 162 /* SB600 and old version of SB700 have a bug in EHCI controller, 163 * which causes usb devices lose response in some cases. 164 */ 165 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { 166 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 167 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 168 NULL); 169 if (!p_smbus) 170 break; 171 rev = p_smbus->revision; 172 if ((pdev->device == 0x4386) || (rev == 0x3a) 173 || (rev == 0x3b)) { 174 u8 tmp; 175 ehci_info(ehci, "applying AMD SB600/SB700 USB " 176 "freeze workaround\n"); 177 pci_read_config_byte(pdev, 0x53, &tmp); 178 pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); 179 } 180 pci_dev_put(p_smbus); 181 } 182 break; 183 } 184 185 /* optional debug port, normally in the first BAR */ 186 temp = pci_find_capability(pdev, 0x0a); 187 if (temp) { 188 pci_read_config_dword(pdev, temp, &temp); 189 temp >>= 16; 190 if ((temp & (3 << 13)) == (1 << 13)) { 191 temp &= 0x1fff; 192 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 193 temp = ehci_readl(ehci, &ehci->debug->control); 194 ehci_info(ehci, "debug port %d%s\n", 195 HCS_DEBUG_PORT(ehci->hcs_params), 196 (temp & DBGP_ENABLED) 197 ? " IN USE" 198 : ""); 199 if (!(temp & DBGP_ENABLED)) 200 ehci->debug = NULL; 201 } 202 } 203 204 ehci_reset(ehci); 205 206 /* at least the Genesys GL880S needs fixup here */ 207 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 208 temp &= 0x0f; 209 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 210 ehci_dbg(ehci, "bogus port configuration: " 211 "cc=%d x pcc=%d < ports=%d\n", 212 HCS_N_CC(ehci->hcs_params), 213 HCS_N_PCC(ehci->hcs_params), 214 HCS_N_PORTS(ehci->hcs_params)); 215 216 switch (pdev->vendor) { 217 case 0x17a0: /* GENESYS */ 218 /* GL880S: should be PORTS=2 */ 219 temp |= (ehci->hcs_params & ~0xf); 220 ehci->hcs_params = temp; 221 break; 222 case PCI_VENDOR_ID_NVIDIA: 223 /* NF4: should be PCC=10 */ 224 break; 225 } 226 } 227 228 /* Serial Bus Release Number is at PCI 0x60 offset */ 229 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 230 231 /* Keep this around for a while just in case some EHCI 232 * implementation uses legacy PCI PM support. This test 233 * can be removed on 17 Dec 2009 if the dev_warn() hasn't 234 * been triggered by then. 235 */ 236 if (!device_can_wakeup(&pdev->dev)) { 237 u16 port_wake; 238 239 pci_read_config_word(pdev, 0x62, &port_wake); 240 if (port_wake & 0x0001) { 241 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); 242 device_set_wakeup_capable(&pdev->dev, 1); 243 } 244 } 245 246 #ifdef CONFIG_USB_SUSPEND 247 /* REVISIT: the controller works fine for wakeup iff the root hub 248 * itself is "globally" suspended, but usbcore currently doesn't 249 * understand such things. 250 * 251 * System suspend currently expects to be able to suspend the entire 252 * device tree, device-at-a-time. If we failed selective suspend 253 * reports, system suspend would fail; so the root hub code must claim 254 * success. That's lying to usbcore, and it matters for runtime 255 * PM scenarios with selective suspend and remote wakeup... 256 */ 257 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 258 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 259 #endif 260 261 ehci_port_power(ehci, 1); 262 retval = ehci_pci_reinit(ehci, pdev); 263 done: 264 return retval; 265 } 266 267 /*-------------------------------------------------------------------------*/ 268 269 #ifdef CONFIG_PM 270 271 /* suspend/resume, section 4.3 */ 272 273 /* These routines rely on the PCI bus glue 274 * to handle powerdown and wakeup, and currently also on 275 * transceivers that don't need any software attention to set up 276 * the right sort of wakeup. 277 * Also they depend on separate root hub suspend/resume. 278 */ 279 280 static int ehci_pci_suspend(struct usb_hcd *hcd) 281 { 282 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 283 unsigned long flags; 284 int rc = 0; 285 286 if (time_before(jiffies, ehci->next_statechange)) 287 msleep(10); 288 289 /* Root hub was already suspended. Disable irq emission and 290 * mark HW unaccessible. The PM and USB cores make sure that 291 * the root hub is either suspended or stopped. 292 */ 293 spin_lock_irqsave (&ehci->lock, flags); 294 ehci_prepare_ports_for_controller_suspend(ehci); 295 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 296 (void)ehci_readl(ehci, &ehci->regs->intr_enable); 297 298 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 299 spin_unlock_irqrestore (&ehci->lock, flags); 300 301 // could save FLADJ in case of Vaux power loss 302 // ... we'd only use it to handle clock skew 303 304 return rc; 305 } 306 307 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) 308 { 309 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 310 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 311 312 // maybe restore FLADJ 313 314 if (time_before(jiffies, ehci->next_statechange)) 315 msleep(100); 316 317 /* Mark hardware accessible again as we are out of D3 state by now */ 318 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 319 320 /* If CF is still set and we aren't resuming from hibernation 321 * then we maintained PCI Vaux power. 322 * Just undo the effect of ehci_pci_suspend(). 323 */ 324 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && 325 !hibernated) { 326 int mask = INTR_MASK; 327 328 ehci_prepare_ports_for_controller_resume(ehci); 329 if (!hcd->self.root_hub->do_remote_wakeup) 330 mask &= ~STS_PCD; 331 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 332 ehci_readl(ehci, &ehci->regs->intr_enable); 333 return 0; 334 } 335 336 usb_root_hub_lost_power(hcd->self.root_hub); 337 338 /* Else reset, to cope with power loss or flush-to-storage 339 * style "resume" having let BIOS kick in during reboot. 340 */ 341 (void) ehci_halt(ehci); 342 (void) ehci_reset(ehci); 343 (void) ehci_pci_reinit(ehci, pdev); 344 345 /* emptying the schedule aborts any urbs */ 346 spin_lock_irq(&ehci->lock); 347 if (ehci->reclaim) 348 end_unlink_async(ehci); 349 ehci_work(ehci); 350 spin_unlock_irq(&ehci->lock); 351 352 ehci_writel(ehci, ehci->command, &ehci->regs->command); 353 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 354 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 355 356 /* here we "know" root ports should always stay powered */ 357 ehci_port_power(ehci, 1); 358 359 hcd->state = HC_STATE_SUSPENDED; 360 return 0; 361 } 362 #endif 363 364 static const struct hc_driver ehci_pci_hc_driver = { 365 .description = hcd_name, 366 .product_desc = "EHCI Host Controller", 367 .hcd_priv_size = sizeof(struct ehci_hcd), 368 369 /* 370 * generic hardware linkage 371 */ 372 .irq = ehci_irq, 373 .flags = HCD_MEMORY | HCD_USB2, 374 375 /* 376 * basic lifecycle operations 377 */ 378 .reset = ehci_pci_setup, 379 .start = ehci_run, 380 #ifdef CONFIG_PM 381 .pci_suspend = ehci_pci_suspend, 382 .pci_resume = ehci_pci_resume, 383 #endif 384 .stop = ehci_stop, 385 .shutdown = ehci_shutdown, 386 387 /* 388 * managing i/o requests and associated device resources 389 */ 390 .urb_enqueue = ehci_urb_enqueue, 391 .urb_dequeue = ehci_urb_dequeue, 392 .endpoint_disable = ehci_endpoint_disable, 393 .endpoint_reset = ehci_endpoint_reset, 394 395 /* 396 * scheduling support 397 */ 398 .get_frame_number = ehci_get_frame, 399 400 /* 401 * root hub support 402 */ 403 .hub_status_data = ehci_hub_status_data, 404 .hub_control = ehci_hub_control, 405 .bus_suspend = ehci_bus_suspend, 406 .bus_resume = ehci_bus_resume, 407 .relinquish_port = ehci_relinquish_port, 408 .port_handed_over = ehci_port_handed_over, 409 410 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 411 }; 412 413 /*-------------------------------------------------------------------------*/ 414 415 /* PCI driver selection metadata; PCI hotplugging uses this */ 416 static const struct pci_device_id pci_ids [] = { { 417 /* handle any USB 2.0 EHCI controller */ 418 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 419 .driver_data = (unsigned long) &ehci_pci_hc_driver, 420 }, 421 { /* end: all zeroes */ } 422 }; 423 MODULE_DEVICE_TABLE(pci, pci_ids); 424 425 /* pci driver glue; this is a "new style" PCI driver module */ 426 static struct pci_driver ehci_pci_driver = { 427 .name = (char *) hcd_name, 428 .id_table = pci_ids, 429 430 .probe = usb_hcd_pci_probe, 431 .remove = usb_hcd_pci_remove, 432 .shutdown = usb_hcd_pci_shutdown, 433 434 #ifdef CONFIG_PM_SLEEP 435 .driver = { 436 .pm = &usb_hcd_pci_pm_ops 437 }, 438 #endif 439 }; 440