1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 4 * 5 * Copyright (c) 2000-2004 by David Brownell 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/usb.h> 12 #include <linux/usb/hcd.h> 13 14 #include "ehci.h" 15 #include "pci-quirks.h" 16 17 #define DRIVER_DESC "EHCI PCI platform driver" 18 19 static const char hcd_name[] = "ehci-pci"; 20 21 /* defined here to avoid adding to pci_ids.h for single instance use */ 22 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 23 24 #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 25 26 /*-------------------------------------------------------------------------*/ 27 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939 28 static inline bool is_intel_quark_x1000(struct pci_dev *pdev) 29 { 30 return pdev->vendor == PCI_VENDOR_ID_INTEL && 31 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC; 32 } 33 34 /* 35 * This is the list of PCI IDs for the devices that have EHCI USB class and 36 * specific drivers for that. One of the example is a ChipIdea device installed 37 * on some Intel MID platforms. 38 */ 39 static const struct pci_device_id bypass_pci_id_table[] = { 40 /* ChipIdea on Intel MID platform */ 41 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), }, 42 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), }, 43 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), }, 44 {} 45 }; 46 47 static inline bool is_bypassed_id(struct pci_dev *pdev) 48 { 49 return !!pci_match_id(bypass_pci_id_table, pdev); 50 } 51 52 /* 53 * 0x84 is the offset of in/out threshold register, 54 * and it is the same offset as the register of 'hostpc'. 55 */ 56 #define intel_quark_x1000_insnreg01 hostpc 57 58 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */ 59 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f 60 61 /* called after powerup, by probe or system-pm "wakeup" */ 62 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 63 { 64 int retval; 65 66 /* we expect static quirk code to handle the "extended capabilities" 67 * (currently just BIOS handoff) allowed starting with EHCI 0.96 68 */ 69 70 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 71 retval = pci_set_mwi(pdev); 72 if (!retval) 73 ehci_dbg(ehci, "MWI active\n"); 74 75 /* Reset the threshold limit */ 76 if (is_intel_quark_x1000(pdev)) { 77 /* 78 * For the Intel QUARK X1000, raise the I/O threshold to the 79 * maximum usable value in order to improve performance. 80 */ 81 ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD, 82 ehci->regs->intel_quark_x1000_insnreg01); 83 } 84 85 return 0; 86 } 87 88 /* called during probe() after chip reset completes */ 89 static int ehci_pci_setup(struct usb_hcd *hcd) 90 { 91 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 92 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 93 u32 temp; 94 int retval; 95 96 ehci->caps = hcd->regs; 97 98 /* 99 * ehci_init() causes memory for DMA transfers to be 100 * allocated. Thus, any vendor-specific workarounds based on 101 * limiting the type of memory used for DMA transfers must 102 * happen before ehci_setup() is called. 103 * 104 * Most other workarounds can be done either before or after 105 * init and reset; they are located here too. 106 */ 107 switch (pdev->vendor) { 108 case PCI_VENDOR_ID_TOSHIBA_2: 109 /* celleb's companion chip */ 110 if (pdev->device == 0x01b5) { 111 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 112 ehci->big_endian_mmio = 1; 113 #else 114 ehci_warn(ehci, 115 "unsupported big endian Toshiba quirk\n"); 116 #endif 117 } 118 break; 119 case PCI_VENDOR_ID_NVIDIA: 120 /* NVidia reports that certain chips don't handle 121 * QH, ITD, or SITD addresses above 2GB. (But TD, 122 * data buffer, and periodic schedule are normal.) 123 */ 124 switch (pdev->device) { 125 case 0x003c: /* MCP04 */ 126 case 0x005b: /* CK804 */ 127 case 0x00d8: /* CK8 */ 128 case 0x00e8: /* CK8S */ 129 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0) 130 ehci_warn(ehci, "can't enable NVidia " 131 "workaround for >2GB RAM\n"); 132 break; 133 134 /* Some NForce2 chips have problems with selective suspend; 135 * fixed in newer silicon. 136 */ 137 case 0x0068: 138 if (pdev->revision < 0xa4) 139 ehci->no_selective_suspend = 1; 140 break; 141 } 142 break; 143 case PCI_VENDOR_ID_INTEL: 144 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) 145 hcd->has_tt = 1; 146 break; 147 case PCI_VENDOR_ID_TDI: 148 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) 149 hcd->has_tt = 1; 150 break; 151 case PCI_VENDOR_ID_AMD: 152 /* AMD PLL quirk */ 153 if (usb_amd_quirk_pll_check()) 154 ehci->amd_pll_fix = 1; 155 /* AMD8111 EHCI doesn't work, according to AMD errata */ 156 if (pdev->device == 0x7463) { 157 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 158 retval = -EIO; 159 goto done; 160 } 161 162 /* 163 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may 164 * read/write memory space which does not belong to it when 165 * there is NULL pointer with T-bit set to 1 in the frame list 166 * table. To avoid the issue, the frame list link pointer 167 * should always contain a valid pointer to a inactive qh. 168 */ 169 if (pdev->device == 0x7808) { 170 ehci->use_dummy_qh = 1; 171 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); 172 } 173 break; 174 case PCI_VENDOR_ID_VIA: 175 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 176 u8 tmp; 177 178 /* The VT6212 defaults to a 1 usec EHCI sleep time which 179 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 180 * that sleep time use the conventional 10 usec. 181 */ 182 pci_read_config_byte(pdev, 0x4b, &tmp); 183 if (tmp & 0x20) 184 break; 185 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 186 } 187 break; 188 case PCI_VENDOR_ID_ATI: 189 /* AMD PLL quirk */ 190 if (usb_amd_quirk_pll_check()) 191 ehci->amd_pll_fix = 1; 192 193 /* 194 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may 195 * read/write memory space which does not belong to it when 196 * there is NULL pointer with T-bit set to 1 in the frame list 197 * table. To avoid the issue, the frame list link pointer 198 * should always contain a valid pointer to a inactive qh. 199 */ 200 if (pdev->device == 0x4396) { 201 ehci->use_dummy_qh = 1; 202 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); 203 } 204 /* SB600 and old version of SB700 have a bug in EHCI controller, 205 * which causes usb devices lose response in some cases. 206 */ 207 if ((pdev->device == 0x4386 || pdev->device == 0x4396) && 208 usb_amd_hang_symptom_quirk()) { 209 u8 tmp; 210 ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n"); 211 pci_read_config_byte(pdev, 0x53, &tmp); 212 pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); 213 } 214 break; 215 case PCI_VENDOR_ID_NETMOS: 216 /* MosChip frame-index-register bug */ 217 ehci_info(ehci, "applying MosChip frame-index workaround\n"); 218 ehci->frame_index_bug = 1; 219 break; 220 case PCI_VENDOR_ID_HUAWEI: 221 /* Synopsys HC bug */ 222 if (pdev->device == 0xa239) { 223 ehci_info(ehci, "applying Synopsys HC workaround\n"); 224 ehci->has_synopsys_hc_bug = 1; 225 } 226 break; 227 case PCI_VENDOR_ID_ASPEED: 228 if (pdev->device == PCI_DEVICE_ID_ASPEED_EHCI) { 229 ehci_info(ehci, "applying Aspeed HC workaround\n"); 230 ehci->is_aspeed = 1; 231 } 232 break; 233 case PCI_VENDOR_ID_ZHAOXIN: 234 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x90) 235 ehci->zx_wakeup_clear_needed = 1; 236 break; 237 } 238 239 /* optional debug port, normally in the first BAR */ 240 temp = pci_find_capability(pdev, PCI_CAP_ID_DBG); 241 if (temp) { 242 pci_read_config_dword(pdev, temp, &temp); 243 temp >>= 16; 244 if (((temp >> 13) & 7) == 1) { 245 u32 hcs_params = ehci_readl(ehci, 246 &ehci->caps->hcs_params); 247 248 temp &= 0x1fff; 249 ehci->debug = hcd->regs + temp; 250 temp = ehci_readl(ehci, &ehci->debug->control); 251 ehci_info(ehci, "debug port %d%s\n", 252 HCS_DEBUG_PORT(hcs_params), 253 (temp & DBGP_ENABLED) ? " IN USE" : ""); 254 if (!(temp & DBGP_ENABLED)) 255 ehci->debug = NULL; 256 } 257 } 258 259 retval = ehci_setup(hcd); 260 if (retval) 261 return retval; 262 263 /* These workarounds need to be applied after ehci_setup() */ 264 switch (pdev->vendor) { 265 case PCI_VENDOR_ID_NEC: 266 case PCI_VENDOR_ID_INTEL: 267 case PCI_VENDOR_ID_AMD: 268 ehci->need_io_watchdog = 0; 269 break; 270 case PCI_VENDOR_ID_NVIDIA: 271 switch (pdev->device) { 272 /* MCP89 chips on the MacBookAir3,1 give EPROTO when 273 * fetching device descriptors unless LPM is disabled. 274 * There are also intermittent problems enumerating 275 * devices with PPCD enabled. 276 */ 277 case 0x0d9d: 278 ehci_info(ehci, "disable ppcd for nvidia mcp89\n"); 279 ehci->has_ppcd = 0; 280 ehci->command &= ~CMD_PPCEE; 281 break; 282 } 283 break; 284 } 285 286 /* at least the Genesys GL880S needs fixup here */ 287 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 288 temp &= 0x0f; 289 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 290 ehci_dbg(ehci, "bogus port configuration: " 291 "cc=%d x pcc=%d < ports=%d\n", 292 HCS_N_CC(ehci->hcs_params), 293 HCS_N_PCC(ehci->hcs_params), 294 HCS_N_PORTS(ehci->hcs_params)); 295 296 switch (pdev->vendor) { 297 case 0x17a0: /* GENESYS */ 298 /* GL880S: should be PORTS=2 */ 299 temp |= (ehci->hcs_params & ~0xf); 300 ehci->hcs_params = temp; 301 break; 302 case PCI_VENDOR_ID_NVIDIA: 303 /* NF4: should be PCC=10 */ 304 break; 305 } 306 } 307 308 /* Serial Bus Release Number is at PCI 0x60 offset */ 309 if (pdev->vendor == PCI_VENDOR_ID_STMICRO 310 && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST) 311 ; /* ConneXT has no sbrn register */ 312 else if (pdev->vendor == PCI_VENDOR_ID_HUAWEI 313 && pdev->device == 0xa239) 314 ; /* HUAWEI Kunpeng920 USB EHCI has no sbrn register */ 315 else 316 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 317 318 /* Keep this around for a while just in case some EHCI 319 * implementation uses legacy PCI PM support. This test 320 * can be removed on 17 Dec 2009 if the dev_warn() hasn't 321 * been triggered by then. 322 */ 323 if (!device_can_wakeup(&pdev->dev)) { 324 u16 port_wake; 325 326 pci_read_config_word(pdev, 0x62, &port_wake); 327 if (port_wake & 0x0001) { 328 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); 329 device_set_wakeup_capable(&pdev->dev, 1); 330 } 331 } 332 333 #ifdef CONFIG_PM 334 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 335 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 336 #endif 337 338 retval = ehci_pci_reinit(ehci, pdev); 339 done: 340 return retval; 341 } 342 343 /*-------------------------------------------------------------------------*/ 344 345 #ifdef CONFIG_PM 346 347 /* suspend/resume, section 4.3 */ 348 349 /* These routines rely on the PCI bus glue 350 * to handle powerdown and wakeup, and currently also on 351 * transceivers that don't need any software attention to set up 352 * the right sort of wakeup. 353 * Also they depend on separate root hub suspend/resume. 354 */ 355 356 static int ehci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 357 { 358 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 359 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 360 bool hibernated = (msg.event == PM_EVENT_RESTORE); 361 362 if (ehci_resume(hcd, hibernated) != 0) 363 (void) ehci_pci_reinit(ehci, pdev); 364 return 0; 365 } 366 367 #else 368 369 #define ehci_suspend NULL 370 #define ehci_pci_resume NULL 371 #endif /* CONFIG_PM */ 372 373 static struct hc_driver __read_mostly ehci_pci_hc_driver; 374 375 static const struct ehci_driver_overrides pci_overrides __initconst = { 376 .reset = ehci_pci_setup, 377 }; 378 379 /*-------------------------------------------------------------------------*/ 380 381 static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 382 { 383 if (is_bypassed_id(pdev)) 384 return -ENODEV; 385 return usb_hcd_pci_probe(pdev, &ehci_pci_hc_driver); 386 } 387 388 static void ehci_pci_remove(struct pci_dev *pdev) 389 { 390 pci_clear_mwi(pdev); 391 usb_hcd_pci_remove(pdev); 392 } 393 394 /* PCI driver selection metadata; PCI hotplugging uses this */ 395 static const struct pci_device_id pci_ids [] = { { 396 /* handle any USB 2.0 EHCI controller */ 397 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 398 }, { 399 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST), 400 }, 401 { /* end: all zeroes */ } 402 }; 403 MODULE_DEVICE_TABLE(pci, pci_ids); 404 405 /* pci driver glue; this is a "new style" PCI driver module */ 406 static struct pci_driver ehci_pci_driver = { 407 .name = hcd_name, 408 .id_table = pci_ids, 409 410 .probe = ehci_pci_probe, 411 .remove = ehci_pci_remove, 412 .shutdown = usb_hcd_pci_shutdown, 413 414 .driver = { 415 #ifdef CONFIG_PM 416 .pm = &usb_hcd_pci_pm_ops, 417 #endif 418 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 419 }, 420 }; 421 422 static int __init ehci_pci_init(void) 423 { 424 if (usb_disabled()) 425 return -ENODEV; 426 427 ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides); 428 429 /* Entries for the PCI suspend/resume callbacks are special */ 430 ehci_pci_hc_driver.pci_suspend = ehci_suspend; 431 ehci_pci_hc_driver.pci_resume = ehci_pci_resume; 432 433 return pci_register_driver(&ehci_pci_driver); 434 } 435 module_init(ehci_pci_init); 436 437 static void __exit ehci_pci_cleanup(void) 438 { 439 pci_unregister_driver(&ehci_pci_driver); 440 } 441 module_exit(ehci_pci_cleanup); 442 443 MODULE_DESCRIPTION(DRIVER_DESC); 444 MODULE_AUTHOR("David Brownell"); 445 MODULE_AUTHOR("Alan Stern"); 446 MODULE_LICENSE("GPL"); 447