1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/usb/host/ehci-orion.c 4 * 5 * Tzachi Perelstein <tzachi@marvell.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/mbus.h> 12 #include <linux/clk.h> 13 #include <linux/platform_data/usb-ehci-orion.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/usb.h> 17 #include <linux/usb/hcd.h> 18 #include <linux/io.h> 19 #include <linux/dma-mapping.h> 20 21 #include "ehci.h" 22 23 #define rdl(off) readl_relaxed(hcd->regs + (off)) 24 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off)) 25 26 #define USB_CMD 0x140 27 #define USB_CMD_RUN BIT(0) 28 #define USB_CMD_RESET BIT(1) 29 #define USB_MODE 0x1a8 30 #define USB_MODE_MASK GENMASK(1, 0) 31 #define USB_MODE_DEVICE 0x2 32 #define USB_MODE_HOST 0x3 33 #define USB_MODE_SDIS BIT(4) 34 #define USB_CAUSE 0x310 35 #define USB_MASK 0x314 36 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) 37 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) 38 #define USB_IPG 0x360 39 #define USB_PHY_PWR_CTRL 0x400 40 #define USB_PHY_TX_CTRL 0x420 41 #define USB_PHY_RX_CTRL 0x430 42 #define USB_PHY_IVREF_CTRL 0x440 43 #define USB_PHY_TST_GRP_CTRL 0x450 44 45 #define USB_SBUSCFG 0x90 46 47 /* BAWR = BARD = 3 : Align read/write bursts packets larger than 128 bytes */ 48 #define USB_SBUSCFG_BAWR_ALIGN_128B (0x3 << 6) 49 #define USB_SBUSCFG_BARD_ALIGN_128B (0x3 << 3) 50 /* AHBBRST = 3 : Align AHB Burst to INCR16 (64 bytes) */ 51 #define USB_SBUSCFG_AHBBRST_INCR16 (0x3 << 0) 52 53 #define USB_SBUSCFG_DEF_VAL (USB_SBUSCFG_BAWR_ALIGN_128B \ 54 | USB_SBUSCFG_BARD_ALIGN_128B \ 55 | USB_SBUSCFG_AHBBRST_INCR16) 56 57 #define DRIVER_DESC "EHCI orion driver" 58 59 #define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv) 60 61 struct orion_ehci_hcd { 62 struct clk *clk; 63 struct phy *phy; 64 }; 65 66 static struct hc_driver __read_mostly ehci_orion_hc_driver; 67 68 /* 69 * Legacy DMA mask is 32 bit. 70 * AC5 has the DDR starting at 8GB, hence it requires 71 * a larger (34-bit) DMA mask, in order for DMA allocations 72 * to succeed: 73 */ 74 static const u64 dma_mask_orion = DMA_BIT_MASK(32); 75 static const u64 dma_mask_ac5 = DMA_BIT_MASK(34); 76 77 /* 78 * Implement Orion USB controller specification guidelines 79 */ 80 static void orion_usb_phy_v1_setup(struct usb_hcd *hcd) 81 { 82 /* The below GLs are according to the Orion Errata document */ 83 /* 84 * Clear interrupt cause and mask 85 */ 86 wrl(USB_CAUSE, 0); 87 wrl(USB_MASK, 0); 88 89 /* 90 * Reset controller 91 */ 92 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET); 93 while (rdl(USB_CMD) & USB_CMD_RESET); 94 95 /* 96 * GL# USB-10: Set IPG for non start of frame packets 97 * Bits[14:8]=0xc 98 */ 99 wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00); 100 101 /* 102 * GL# USB-9: USB 2.0 Power Control 103 * BG_VSEL[7:6]=0x1 104 */ 105 wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40); 106 107 /* 108 * GL# USB-1: USB PHY Tx Control - force calibration to '8' 109 * TXDATA_BLOCK_EN[21]=0x1, EXT_RCAL_EN[13]=0x1, IMP_CAL[6:3]=0x8 110 */ 111 wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040); 112 113 /* 114 * GL# USB-3 GL# USB-9: USB PHY Rx Control 115 * RXDATA_BLOCK_LENGHT[31:30]=0x3, EDGE_DET_SEL[27:26]=0, 116 * CDR_FASTLOCK_EN[21]=0, DISCON_THRESHOLD[9:8]=0, SQ_THRESH[7:4]=0x1 117 */ 118 wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010); 119 120 /* 121 * GL# USB-3 GL# USB-9: USB PHY IVREF Control 122 * PLLVDD12[1:0]=0x2, RXVDD[5:4]=0x3, Reserved[19]=0 123 */ 124 wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32); 125 126 /* 127 * GL# USB-3 GL# USB-9: USB PHY Test Group Control 128 * REG_FIFO_SQ_RST[15]=0 129 */ 130 wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000); 131 132 /* 133 * Stop and reset controller 134 */ 135 wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN); 136 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET); 137 while (rdl(USB_CMD) & USB_CMD_RESET); 138 139 /* 140 * GL# USB-5 Streaming disable REG_USB_MODE[4]=1 141 * TBD: This need to be done after each reset! 142 * GL# USB-4 Setup USB Host mode 143 */ 144 wrl(USB_MODE, USB_MODE_SDIS | USB_MODE_HOST); 145 } 146 147 static void 148 ehci_orion_conf_mbus_windows(struct usb_hcd *hcd, 149 const struct mbus_dram_target_info *dram) 150 { 151 int i; 152 153 for (i = 0; i < 4; i++) { 154 wrl(USB_WINDOW_CTRL(i), 0); 155 wrl(USB_WINDOW_BASE(i), 0); 156 } 157 158 for (i = 0; i < dram->num_cs; i++) { 159 const struct mbus_dram_window *cs = dram->cs + i; 160 161 wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | 162 (cs->mbus_attr << 8) | 163 (dram->mbus_dram_target_id << 4) | 1); 164 wrl(USB_WINDOW_BASE(i), cs->base); 165 } 166 } 167 168 static int ehci_orion_drv_reset(struct usb_hcd *hcd) 169 { 170 struct device *dev = hcd->self.controller; 171 int ret; 172 173 ret = ehci_setup(hcd); 174 if (ret) 175 return ret; 176 177 /* 178 * For SoC without hlock, need to program sbuscfg value to guarantee 179 * AHB master's burst would not overrun or underrun FIFO. 180 * 181 * sbuscfg reg has to be set after usb controller reset, otherwise 182 * the value would be override to 0. 183 */ 184 if (of_device_is_compatible(dev->of_node, "marvell,armada-3700-ehci")) 185 wrl(USB_SBUSCFG, USB_SBUSCFG_DEF_VAL); 186 187 return ret; 188 } 189 190 static int __maybe_unused ehci_orion_drv_suspend(struct device *dev) 191 { 192 struct usb_hcd *hcd = dev_get_drvdata(dev); 193 194 return ehci_suspend(hcd, device_may_wakeup(dev)); 195 } 196 197 static int __maybe_unused ehci_orion_drv_resume(struct device *dev) 198 { 199 struct usb_hcd *hcd = dev_get_drvdata(dev); 200 201 return ehci_resume(hcd, false); 202 } 203 204 static SIMPLE_DEV_PM_OPS(ehci_orion_pm_ops, ehci_orion_drv_suspend, 205 ehci_orion_drv_resume); 206 207 static const struct ehci_driver_overrides orion_overrides __initconst = { 208 .extra_priv_size = sizeof(struct orion_ehci_hcd), 209 .reset = ehci_orion_drv_reset, 210 }; 211 212 static int ehci_orion_drv_probe(struct platform_device *pdev) 213 { 214 struct orion_ehci_data *pd = dev_get_platdata(&pdev->dev); 215 const struct mbus_dram_target_info *dram; 216 struct resource *res; 217 struct usb_hcd *hcd; 218 struct ehci_hcd *ehci; 219 void __iomem *regs; 220 int irq, err; 221 enum orion_ehci_phy_ver phy_version; 222 struct orion_ehci_hcd *priv; 223 u64 *dma_mask_ptr; 224 225 if (usb_disabled()) 226 return -ENODEV; 227 228 pr_debug("Initializing Orion-SoC USB Host Controller\n"); 229 230 irq = platform_get_irq(pdev, 0); 231 if (irq < 0) { 232 err = irq; 233 goto err; 234 } 235 236 /* 237 * Right now device-tree probed devices don't get dma_mask 238 * set. Since shared usb code relies on it, set it here for 239 * now. Once we have dma capability bindings this can go away. 240 */ 241 dma_mask_ptr = (u64 *)of_device_get_match_data(&pdev->dev); 242 err = dma_coerce_mask_and_coherent(&pdev->dev, *dma_mask_ptr); 243 if (err) 244 goto err; 245 246 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 247 if (IS_ERR(regs)) { 248 err = PTR_ERR(regs); 249 goto err; 250 } 251 252 hcd = usb_create_hcd(&ehci_orion_hc_driver, 253 &pdev->dev, dev_name(&pdev->dev)); 254 if (!hcd) { 255 err = -ENOMEM; 256 goto err; 257 } 258 259 hcd->rsrc_start = res->start; 260 hcd->rsrc_len = resource_size(res); 261 hcd->regs = regs; 262 263 ehci = hcd_to_ehci(hcd); 264 ehci->caps = hcd->regs + 0x100; 265 hcd->has_tt = 1; 266 267 priv = hcd_to_orion_priv(hcd); 268 /* 269 * Not all platforms can gate the clock, so it is not an error if 270 * the clock does not exists. 271 */ 272 priv->clk = devm_clk_get(&pdev->dev, NULL); 273 if (!IS_ERR(priv->clk)) { 274 err = clk_prepare_enable(priv->clk); 275 if (err) 276 goto err_put_hcd; 277 } 278 279 priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); 280 if (IS_ERR(priv->phy)) { 281 err = PTR_ERR(priv->phy); 282 if (err != -ENOSYS) 283 goto err_dis_clk; 284 } 285 286 /* 287 * (Re-)program MBUS remapping windows if we are asked to. 288 */ 289 dram = mv_mbus_dram_info(); 290 if (dram) 291 ehci_orion_conf_mbus_windows(hcd, dram); 292 293 /* 294 * setup Orion USB controller. 295 */ 296 if (pdev->dev.of_node) 297 phy_version = EHCI_PHY_NA; 298 else 299 phy_version = pd->phy_version; 300 301 switch (phy_version) { 302 case EHCI_PHY_NA: /* dont change USB phy settings */ 303 break; 304 case EHCI_PHY_ORION: 305 orion_usb_phy_v1_setup(hcd); 306 break; 307 case EHCI_PHY_DD: 308 case EHCI_PHY_KW: 309 default: 310 dev_warn(&pdev->dev, "USB phy version isn't supported.\n"); 311 } 312 313 err = usb_add_hcd(hcd, irq, IRQF_SHARED); 314 if (err) 315 goto err_dis_clk; 316 317 device_wakeup_enable(hcd->self.controller); 318 return 0; 319 320 err_dis_clk: 321 if (!IS_ERR(priv->clk)) 322 clk_disable_unprepare(priv->clk); 323 err_put_hcd: 324 usb_put_hcd(hcd); 325 err: 326 dev_err(&pdev->dev, "init %s fail, %d\n", 327 dev_name(&pdev->dev), err); 328 329 return err; 330 } 331 332 static void ehci_orion_drv_remove(struct platform_device *pdev) 333 { 334 struct usb_hcd *hcd = platform_get_drvdata(pdev); 335 struct orion_ehci_hcd *priv = hcd_to_orion_priv(hcd); 336 337 usb_remove_hcd(hcd); 338 339 if (!IS_ERR(priv->clk)) 340 clk_disable_unprepare(priv->clk); 341 342 usb_put_hcd(hcd); 343 } 344 345 static const struct of_device_id ehci_orion_dt_ids[] = { 346 { .compatible = "marvell,orion-ehci", .data = &dma_mask_orion}, 347 { .compatible = "marvell,armada-3700-ehci", .data = &dma_mask_orion}, 348 { .compatible = "marvell,ac5-ehci", .data = &dma_mask_ac5}, 349 {}, 350 }; 351 MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids); 352 353 static struct platform_driver ehci_orion_driver = { 354 .probe = ehci_orion_drv_probe, 355 .remove_new = ehci_orion_drv_remove, 356 .shutdown = usb_hcd_platform_shutdown, 357 .driver = { 358 .name = "orion-ehci", 359 .of_match_table = ehci_orion_dt_ids, 360 .pm = &ehci_orion_pm_ops, 361 }, 362 }; 363 364 static int __init ehci_orion_init(void) 365 { 366 if (usb_disabled()) 367 return -ENODEV; 368 369 ehci_init_driver(&ehci_orion_hc_driver, &orion_overrides); 370 return platform_driver_register(&ehci_orion_driver); 371 } 372 module_init(ehci_orion_init); 373 374 static void __exit ehci_orion_cleanup(void) 375 { 376 platform_driver_unregister(&ehci_orion_driver); 377 } 378 module_exit(ehci_orion_cleanup); 379 380 MODULE_DESCRIPTION(DRIVER_DESC); 381 MODULE_ALIAS("platform:orion-ehci"); 382 MODULE_AUTHOR("Tzachi Perelstein"); 383 MODULE_LICENSE("GPL v2"); 384