1 /* 2 * ehci-omap.c - driver for USBHOST on OMAP 34xx processor 3 * 4 * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller 5 * Tested on OMAP3430 ES2.0 SDP 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Author: Vikram Pandita <vikram.pandita@ti.com> 9 * 10 * Copyright (C) 2009 Nokia Corporation 11 * Contact: Felipe Balbi <felipe.balbi@nokia.com> 12 * 13 * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 * 29 * TODO (last updated Feb 12, 2010): 30 * - add kernel-doc 31 * - enable AUTOIDLE 32 * - add suspend/resume 33 * - move workarounds to board-files 34 */ 35 36 #include <linux/platform_device.h> 37 #include <linux/clk.h> 38 #include <linux/gpio.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/slab.h> 41 #include <plat/usb.h> 42 43 /* 44 * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES 45 * Use ehci_omap_readl()/ehci_omap_writel() functions 46 */ 47 48 /* TLL Register Set */ 49 #define OMAP_USBTLL_REVISION (0x00) 50 #define OMAP_USBTLL_SYSCONFIG (0x10) 51 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) 52 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) 53 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) 54 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) 55 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) 56 57 #define OMAP_USBTLL_SYSSTATUS (0x14) 58 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) 59 60 #define OMAP_USBTLL_IRQSTATUS (0x18) 61 #define OMAP_USBTLL_IRQENABLE (0x1C) 62 63 #define OMAP_TLL_SHARED_CONF (0x30) 64 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) 65 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) 66 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) 67 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) 68 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) 69 70 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) 71 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) 72 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) 73 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) 74 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) 75 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) 76 77 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) 78 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) 79 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) 80 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) 81 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) 82 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) 83 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) 84 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) 85 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) 86 87 #define OMAP_TLL_CHANNEL_COUNT 3 88 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1) 89 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2) 90 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4) 91 92 /* UHH Register Set */ 93 #define OMAP_UHH_REVISION (0x00) 94 #define OMAP_UHH_SYSCONFIG (0x10) 95 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) 96 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) 97 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) 98 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) 99 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) 100 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) 101 102 #define OMAP_UHH_SYSSTATUS (0x14) 103 #define OMAP_UHH_HOSTCONFIG (0x40) 104 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) 105 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) 106 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) 107 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) 108 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) 109 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) 110 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) 111 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) 112 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) 113 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) 114 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) 115 116 #define OMAP_UHH_DEBUG_CSR (0x44) 117 118 /* EHCI Register Set */ 119 #define EHCI_INSNREG04 (0xA0) 120 #define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 121 #define EHCI_INSNREG05_ULPI (0xA4) 122 #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 123 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 124 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 125 #define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 126 #define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 127 #define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 128 129 /*-------------------------------------------------------------------------*/ 130 131 static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val) 132 { 133 __raw_writel(val, base + reg); 134 } 135 136 static inline u32 ehci_omap_readl(void __iomem *base, u32 reg) 137 { 138 return __raw_readl(base + reg); 139 } 140 141 static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val) 142 { 143 __raw_writeb(val, base + reg); 144 } 145 146 static inline u8 ehci_omap_readb(void __iomem *base, u8 reg) 147 { 148 return __raw_readb(base + reg); 149 } 150 151 /*-------------------------------------------------------------------------*/ 152 153 struct ehci_hcd_omap { 154 struct ehci_hcd *ehci; 155 struct device *dev; 156 157 struct clk *usbhost_ick; 158 struct clk *usbhost2_120m_fck; 159 struct clk *usbhost1_48m_fck; 160 struct clk *usbtll_fck; 161 struct clk *usbtll_ick; 162 163 /* FIXME the following two workarounds are 164 * board specific not silicon-specific so these 165 * should be moved to board-file instead. 166 * 167 * Maybe someone from TI will know better which 168 * board is affected and needs the workarounds 169 * to be applied 170 */ 171 172 /* gpio for resetting phy */ 173 int reset_gpio_port[OMAP3_HS_USB_PORTS]; 174 175 /* phy reset workaround */ 176 int phy_reset; 177 178 /* desired phy_mode: TLL, PHY */ 179 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; 180 181 void __iomem *uhh_base; 182 void __iomem *tll_base; 183 void __iomem *ehci_base; 184 185 /* Regulators for USB PHYs. 186 * Each PHY can have a separate regulator. 187 */ 188 struct regulator *regulator[OMAP3_HS_USB_PORTS]; 189 }; 190 191 /*-------------------------------------------------------------------------*/ 192 193 static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask) 194 { 195 unsigned reg; 196 int i; 197 198 /* Program the 3 TLL channels upfront */ 199 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { 200 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); 201 202 /* Disable AutoIdle, BitStuffing and use SDR Mode */ 203 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE 204 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 205 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); 206 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); 207 } 208 209 /* Program Common TLL register */ 210 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); 211 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON 212 | OMAP_TLL_SHARED_CONF_USB_DIVRATION 213 | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN); 214 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; 215 216 ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); 217 218 /* Enable channels now */ 219 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { 220 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); 221 222 /* Enable only the reg that is needed */ 223 if (!(tll_channel_mask & 1<<i)) 224 continue; 225 226 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; 227 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); 228 229 ehci_omap_writeb(omap->tll_base, 230 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); 231 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n", 232 i+1, ehci_omap_readb(omap->tll_base, 233 OMAP_TLL_ULPI_SCRATCH_REGISTER(i))); 234 } 235 } 236 237 /*-------------------------------------------------------------------------*/ 238 239 /* omap_start_ehc 240 * - Start the TI USBHOST controller 241 */ 242 static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) 243 { 244 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 245 u8 tll_ch_mask = 0; 246 unsigned reg = 0; 247 int ret = 0; 248 249 dev_dbg(omap->dev, "starting TI EHCI USB Controller\n"); 250 251 /* Enable Clocks for USBHOST */ 252 omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); 253 if (IS_ERR(omap->usbhost_ick)) { 254 ret = PTR_ERR(omap->usbhost_ick); 255 goto err_host_ick; 256 } 257 clk_enable(omap->usbhost_ick); 258 259 omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); 260 if (IS_ERR(omap->usbhost2_120m_fck)) { 261 ret = PTR_ERR(omap->usbhost2_120m_fck); 262 goto err_host_120m_fck; 263 } 264 clk_enable(omap->usbhost2_120m_fck); 265 266 omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); 267 if (IS_ERR(omap->usbhost1_48m_fck)) { 268 ret = PTR_ERR(omap->usbhost1_48m_fck); 269 goto err_host_48m_fck; 270 } 271 clk_enable(omap->usbhost1_48m_fck); 272 273 if (omap->phy_reset) { 274 /* Refer: ISSUE1 */ 275 if (gpio_is_valid(omap->reset_gpio_port[0])) { 276 gpio_request(omap->reset_gpio_port[0], 277 "USB1 PHY reset"); 278 gpio_direction_output(omap->reset_gpio_port[0], 0); 279 } 280 281 if (gpio_is_valid(omap->reset_gpio_port[1])) { 282 gpio_request(omap->reset_gpio_port[1], 283 "USB2 PHY reset"); 284 gpio_direction_output(omap->reset_gpio_port[1], 0); 285 } 286 287 /* Hold the PHY in RESET for enough time till DIR is high */ 288 udelay(10); 289 } 290 291 /* Configure TLL for 60Mhz clk for ULPI */ 292 omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); 293 if (IS_ERR(omap->usbtll_fck)) { 294 ret = PTR_ERR(omap->usbtll_fck); 295 goto err_tll_fck; 296 } 297 clk_enable(omap->usbtll_fck); 298 299 omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); 300 if (IS_ERR(omap->usbtll_ick)) { 301 ret = PTR_ERR(omap->usbtll_ick); 302 goto err_tll_ick; 303 } 304 clk_enable(omap->usbtll_ick); 305 306 /* perform TLL soft reset, and wait until reset is complete */ 307 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 308 OMAP_USBTLL_SYSCONFIG_SOFTRESET); 309 310 /* Wait for TLL reset to complete */ 311 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 312 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { 313 cpu_relax(); 314 315 if (time_after(jiffies, timeout)) { 316 dev_dbg(omap->dev, "operation timed out\n"); 317 ret = -EINVAL; 318 goto err_sys_status; 319 } 320 } 321 322 dev_dbg(omap->dev, "TLL RESET DONE\n"); 323 324 /* (1<<3) = no idle mode only for initial debugging */ 325 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 326 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 327 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 328 OMAP_USBTLL_SYSCONFIG_CACTIVITY); 329 330 331 /* Put UHH in NoIdle/NoStandby mode */ 332 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); 333 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP 334 | OMAP_UHH_SYSCONFIG_SIDLEMODE 335 | OMAP_UHH_SYSCONFIG_CACTIVITY 336 | OMAP_UHH_SYSCONFIG_MIDLEMODE); 337 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; 338 339 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); 340 341 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); 342 343 /* setup ULPI bypass and burst configurations */ 344 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN 345 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN 346 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); 347 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; 348 349 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) 350 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; 351 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) 352 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; 353 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) 354 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 355 356 /* Bypass the TLL module for PHY mode operation */ 357 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { 358 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n"); 359 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) || 360 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) || 361 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)) 362 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 363 else 364 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 365 } else { 366 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); 367 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) 368 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 369 else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) 370 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 371 372 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) 373 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 374 else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) 375 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 376 377 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY) 378 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 379 else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) 380 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 381 382 } 383 ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); 384 dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); 385 386 387 /* 388 * An undocumented "feature" in the OMAP3 EHCI controller, 389 * causes suspended ports to be taken out of suspend when 390 * the USBCMD.Run/Stop bit is cleared (for example when 391 * we do ehci_bus_suspend). 392 * This breaks suspend-resume if the root-hub is allowed 393 * to suspend. Writing 1 to this undocumented register bit 394 * disables this feature and restores normal behavior. 395 */ 396 ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, 397 EHCI_INSNREG04_DISABLE_UNSUSPEND); 398 399 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || 400 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) || 401 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) { 402 403 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) 404 tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK; 405 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) 406 tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK; 407 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) 408 tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK; 409 410 /* Enable UTMI mode for required TLL channels */ 411 omap_usb_utmi_init(omap, tll_ch_mask); 412 } 413 414 if (omap->phy_reset) { 415 /* Refer ISSUE1: 416 * Hold the PHY in RESET for enough time till 417 * PHY is settled and ready 418 */ 419 udelay(10); 420 421 if (gpio_is_valid(omap->reset_gpio_port[0])) 422 gpio_set_value(omap->reset_gpio_port[0], 1); 423 424 if (gpio_is_valid(omap->reset_gpio_port[1])) 425 gpio_set_value(omap->reset_gpio_port[1], 1); 426 } 427 428 return 0; 429 430 err_sys_status: 431 clk_disable(omap->usbtll_ick); 432 clk_put(omap->usbtll_ick); 433 434 err_tll_ick: 435 clk_disable(omap->usbtll_fck); 436 clk_put(omap->usbtll_fck); 437 438 err_tll_fck: 439 clk_disable(omap->usbhost1_48m_fck); 440 clk_put(omap->usbhost1_48m_fck); 441 442 if (omap->phy_reset) { 443 if (gpio_is_valid(omap->reset_gpio_port[0])) 444 gpio_free(omap->reset_gpio_port[0]); 445 446 if (gpio_is_valid(omap->reset_gpio_port[1])) 447 gpio_free(omap->reset_gpio_port[1]); 448 } 449 450 err_host_48m_fck: 451 clk_disable(omap->usbhost2_120m_fck); 452 clk_put(omap->usbhost2_120m_fck); 453 454 err_host_120m_fck: 455 clk_disable(omap->usbhost_ick); 456 clk_put(omap->usbhost_ick); 457 458 err_host_ick: 459 return ret; 460 } 461 462 static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) 463 { 464 unsigned long timeout = jiffies + msecs_to_jiffies(100); 465 466 dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); 467 468 /* Reset OMAP modules for insmod/rmmod to work */ 469 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, 470 OMAP_UHH_SYSCONFIG_SOFTRESET); 471 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 472 & (1 << 0))) { 473 cpu_relax(); 474 475 if (time_after(jiffies, timeout)) 476 dev_dbg(omap->dev, "operation timed out\n"); 477 } 478 479 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 480 & (1 << 1))) { 481 cpu_relax(); 482 483 if (time_after(jiffies, timeout)) 484 dev_dbg(omap->dev, "operation timed out\n"); 485 } 486 487 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) 488 & (1 << 2))) { 489 cpu_relax(); 490 491 if (time_after(jiffies, timeout)) 492 dev_dbg(omap->dev, "operation timed out\n"); 493 } 494 495 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); 496 497 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 498 & (1 << 0))) { 499 cpu_relax(); 500 501 if (time_after(jiffies, timeout)) 502 dev_dbg(omap->dev, "operation timed out\n"); 503 } 504 505 if (omap->usbtll_fck != NULL) { 506 clk_disable(omap->usbtll_fck); 507 clk_put(omap->usbtll_fck); 508 omap->usbtll_fck = NULL; 509 } 510 511 if (omap->usbhost_ick != NULL) { 512 clk_disable(omap->usbhost_ick); 513 clk_put(omap->usbhost_ick); 514 omap->usbhost_ick = NULL; 515 } 516 517 if (omap->usbhost1_48m_fck != NULL) { 518 clk_disable(omap->usbhost1_48m_fck); 519 clk_put(omap->usbhost1_48m_fck); 520 omap->usbhost1_48m_fck = NULL; 521 } 522 523 if (omap->usbhost2_120m_fck != NULL) { 524 clk_disable(omap->usbhost2_120m_fck); 525 clk_put(omap->usbhost2_120m_fck); 526 omap->usbhost2_120m_fck = NULL; 527 } 528 529 if (omap->usbtll_ick != NULL) { 530 clk_disable(omap->usbtll_ick); 531 clk_put(omap->usbtll_ick); 532 omap->usbtll_ick = NULL; 533 } 534 535 if (omap->phy_reset) { 536 if (gpio_is_valid(omap->reset_gpio_port[0])) 537 gpio_free(omap->reset_gpio_port[0]); 538 539 if (gpio_is_valid(omap->reset_gpio_port[1])) 540 gpio_free(omap->reset_gpio_port[1]); 541 } 542 543 dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); 544 } 545 546 /*-------------------------------------------------------------------------*/ 547 548 static const struct hc_driver ehci_omap_hc_driver; 549 550 /* configure so an HC device and id are always provided */ 551 /* always called with process context; sleeping is OK */ 552 553 /** 554 * ehci_hcd_omap_probe - initialize TI-based HCDs 555 * 556 * Allocates basic resources for this USB host controller, and 557 * then invokes the start() method for the HCD associated with it 558 * through the hotplug entry's driver_data. 559 */ 560 static int ehci_hcd_omap_probe(struct platform_device *pdev) 561 { 562 struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; 563 struct ehci_hcd_omap *omap; 564 struct resource *res; 565 struct usb_hcd *hcd; 566 567 int irq = platform_get_irq(pdev, 0); 568 int ret = -ENODEV; 569 int i; 570 char supply[7]; 571 572 if (!pdata) { 573 dev_dbg(&pdev->dev, "missing platform_data\n"); 574 goto err_pdata; 575 } 576 577 if (usb_disabled()) 578 goto err_disabled; 579 580 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 581 if (!omap) { 582 ret = -ENOMEM; 583 goto err_disabled; 584 } 585 586 hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev, 587 dev_name(&pdev->dev)); 588 if (!hcd) { 589 dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret); 590 ret = -ENOMEM; 591 goto err_create_hcd; 592 } 593 594 platform_set_drvdata(pdev, omap); 595 omap->dev = &pdev->dev; 596 omap->phy_reset = pdata->phy_reset; 597 omap->reset_gpio_port[0] = pdata->reset_gpio_port[0]; 598 omap->reset_gpio_port[1] = pdata->reset_gpio_port[1]; 599 omap->reset_gpio_port[2] = pdata->reset_gpio_port[2]; 600 omap->port_mode[0] = pdata->port_mode[0]; 601 omap->port_mode[1] = pdata->port_mode[1]; 602 omap->port_mode[2] = pdata->port_mode[2]; 603 omap->ehci = hcd_to_ehci(hcd); 604 omap->ehci->sbrn = 0x20; 605 606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 607 608 hcd->rsrc_start = res->start; 609 hcd->rsrc_len = resource_size(res); 610 611 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); 612 if (!hcd->regs) { 613 dev_err(&pdev->dev, "EHCI ioremap failed\n"); 614 ret = -ENOMEM; 615 goto err_ioremap; 616 } 617 618 /* we know this is the memory we want, no need to ioremap again */ 619 omap->ehci->caps = hcd->regs; 620 omap->ehci_base = hcd->regs; 621 622 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 623 omap->uhh_base = ioremap(res->start, resource_size(res)); 624 if (!omap->uhh_base) { 625 dev_err(&pdev->dev, "UHH ioremap failed\n"); 626 ret = -ENOMEM; 627 goto err_uhh_ioremap; 628 } 629 630 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 631 omap->tll_base = ioremap(res->start, resource_size(res)); 632 if (!omap->tll_base) { 633 dev_err(&pdev->dev, "TLL ioremap failed\n"); 634 ret = -ENOMEM; 635 goto err_tll_ioremap; 636 } 637 638 /* get ehci regulator and enable */ 639 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 640 if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) { 641 omap->regulator[i] = NULL; 642 continue; 643 } 644 snprintf(supply, sizeof(supply), "hsusb%d", i); 645 omap->regulator[i] = regulator_get(omap->dev, supply); 646 if (IS_ERR(omap->regulator[i])) { 647 omap->regulator[i] = NULL; 648 dev_dbg(&pdev->dev, 649 "failed to get ehci port%d regulator\n", i); 650 } else { 651 regulator_enable(omap->regulator[i]); 652 } 653 } 654 655 ret = omap_start_ehc(omap, hcd); 656 if (ret) { 657 dev_dbg(&pdev->dev, "failed to start ehci\n"); 658 goto err_start; 659 } 660 661 omap->ehci->regs = hcd->regs 662 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); 663 664 dbg_hcs_params(omap->ehci, "reset"); 665 dbg_hcc_params(omap->ehci, "reset"); 666 667 /* cache this readonly data; minimize chip reads */ 668 omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); 669 670 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); 671 if (ret) { 672 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); 673 goto err_add_hcd; 674 } 675 676 /* root ports should always stay powered */ 677 ehci_port_power(omap->ehci, 1); 678 679 return 0; 680 681 err_add_hcd: 682 omap_stop_ehc(omap, hcd); 683 684 err_start: 685 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 686 if (omap->regulator[i]) { 687 regulator_disable(omap->regulator[i]); 688 regulator_put(omap->regulator[i]); 689 } 690 } 691 iounmap(omap->tll_base); 692 693 err_tll_ioremap: 694 iounmap(omap->uhh_base); 695 696 err_uhh_ioremap: 697 iounmap(hcd->regs); 698 699 err_ioremap: 700 usb_put_hcd(hcd); 701 702 err_create_hcd: 703 kfree(omap); 704 err_disabled: 705 err_pdata: 706 return ret; 707 } 708 709 /* may be called without controller electrically present */ 710 /* may be called with controller, bus, and devices active */ 711 712 /** 713 * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs 714 * @pdev: USB Host Controller being removed 715 * 716 * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking 717 * the HCD's stop() method. It is always called from a thread 718 * context, normally "rmmod", "apmd", or something similar. 719 */ 720 static int ehci_hcd_omap_remove(struct platform_device *pdev) 721 { 722 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 723 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); 724 int i; 725 726 usb_remove_hcd(hcd); 727 omap_stop_ehc(omap, hcd); 728 iounmap(hcd->regs); 729 for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { 730 if (omap->regulator[i]) { 731 regulator_disable(omap->regulator[i]); 732 regulator_put(omap->regulator[i]); 733 } 734 } 735 iounmap(omap->tll_base); 736 iounmap(omap->uhh_base); 737 usb_put_hcd(hcd); 738 kfree(omap); 739 740 return 0; 741 } 742 743 static void ehci_hcd_omap_shutdown(struct platform_device *pdev) 744 { 745 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); 746 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); 747 748 if (hcd->driver->shutdown) 749 hcd->driver->shutdown(hcd); 750 } 751 752 static struct platform_driver ehci_hcd_omap_driver = { 753 .probe = ehci_hcd_omap_probe, 754 .remove = ehci_hcd_omap_remove, 755 .shutdown = ehci_hcd_omap_shutdown, 756 /*.suspend = ehci_hcd_omap_suspend, */ 757 /*.resume = ehci_hcd_omap_resume, */ 758 .driver = { 759 .name = "ehci-omap", 760 } 761 }; 762 763 /*-------------------------------------------------------------------------*/ 764 765 static const struct hc_driver ehci_omap_hc_driver = { 766 .description = hcd_name, 767 .product_desc = "OMAP-EHCI Host Controller", 768 .hcd_priv_size = sizeof(struct ehci_hcd), 769 770 /* 771 * generic hardware linkage 772 */ 773 .irq = ehci_irq, 774 .flags = HCD_MEMORY | HCD_USB2, 775 776 /* 777 * basic lifecycle operations 778 */ 779 .reset = ehci_init, 780 .start = ehci_run, 781 .stop = ehci_stop, 782 .shutdown = ehci_shutdown, 783 784 /* 785 * managing i/o requests and associated device resources 786 */ 787 .urb_enqueue = ehci_urb_enqueue, 788 .urb_dequeue = ehci_urb_dequeue, 789 .endpoint_disable = ehci_endpoint_disable, 790 .endpoint_reset = ehci_endpoint_reset, 791 792 /* 793 * scheduling support 794 */ 795 .get_frame_number = ehci_get_frame, 796 797 /* 798 * root hub support 799 */ 800 .hub_status_data = ehci_hub_status_data, 801 .hub_control = ehci_hub_control, 802 .bus_suspend = ehci_bus_suspend, 803 .bus_resume = ehci_bus_resume, 804 805 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 806 }; 807 808 MODULE_ALIAS("platform:omap-ehci"); 809 MODULE_AUTHOR("Texas Instruments, Inc."); 810 MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>"); 811 812