1 /* 2 * Enhanced Host Controller Interface (EHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * Copyright (c) 2000-2004 by David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/dmapool.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/vmalloc.h> 31 #include <linux/errno.h> 32 #include <linux/init.h> 33 #include <linux/timer.h> 34 #include <linux/ktime.h> 35 #include <linux/list.h> 36 #include <linux/interrupt.h> 37 #include <linux/usb.h> 38 #include <linux/usb/hcd.h> 39 #include <linux/moduleparam.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/debugfs.h> 42 #include <linux/slab.h> 43 #include <linux/uaccess.h> 44 45 #include <asm/byteorder.h> 46 #include <asm/io.h> 47 #include <asm/irq.h> 48 #include <asm/system.h> 49 #include <asm/unaligned.h> 50 51 /*-------------------------------------------------------------------------*/ 52 53 /* 54 * EHCI hc_driver implementation ... experimental, incomplete. 55 * Based on the final 1.0 register interface specification. 56 * 57 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 58 * First was PCMCIA, like ISA; then CardBus, which is PCI. 59 * Next comes "CardBay", using USB 2.0 signals. 60 * 61 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 62 * Special thanks to Intel and VIA for providing host controllers to 63 * test this driver on, and Cypress (including In-System Design) for 64 * providing early devices for those host controllers to talk to! 65 */ 66 67 #define DRIVER_AUTHOR "David Brownell" 68 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 69 70 static const char hcd_name [] = "ehci_hcd"; 71 72 73 #undef VERBOSE_DEBUG 74 #undef EHCI_URB_TRACE 75 76 #ifdef DEBUG 77 #define EHCI_STATS 78 #endif 79 80 /* magic numbers that can affect system performance */ 81 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 82 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 83 #define EHCI_TUNE_RL_TT 0 84 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 85 #define EHCI_TUNE_MULT_TT 1 86 /* 87 * Some drivers think it's safe to schedule isochronous transfers more than 88 * 256 ms into the future (partly as a result of an old bug in the scheduling 89 * code). In an attempt to avoid trouble, we will use a minimum scheduling 90 * length of 512 frames instead of 256. 91 */ 92 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 93 94 #define EHCI_IAA_MSECS 10 /* arbitrary */ 95 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 96 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 97 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) 98 /* 5-ms async qh unlink delay */ 99 100 /* Initial IRQ latency: faster than hw default */ 101 static int log2_irq_thresh = 0; // 0 to 6 102 module_param (log2_irq_thresh, int, S_IRUGO); 103 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 104 105 /* initial park setting: slower than hw default */ 106 static unsigned park = 0; 107 module_param (park, uint, S_IRUGO); 108 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 109 110 /* for flakey hardware, ignore overcurrent indicators */ 111 static int ignore_oc = 0; 112 module_param (ignore_oc, bool, S_IRUGO); 113 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 114 115 /* for link power management(LPM) feature */ 116 static unsigned int hird; 117 module_param(hird, int, S_IRUGO); 118 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); 119 120 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 121 122 /*-------------------------------------------------------------------------*/ 123 124 #include "ehci.h" 125 #include "ehci-dbg.c" 126 #include "pci-quirks.h" 127 128 /*-------------------------------------------------------------------------*/ 129 130 static void 131 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 132 { 133 /* Don't override timeouts which shrink or (later) disable 134 * the async ring; just the I/O watchdog. Note that if a 135 * SHRINK were pending, OFF would never be requested. 136 */ 137 if (timer_pending(&ehci->watchdog) 138 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 139 & ehci->actions)) 140 return; 141 142 if (!test_and_set_bit(action, &ehci->actions)) { 143 unsigned long t; 144 145 switch (action) { 146 case TIMER_IO_WATCHDOG: 147 if (!ehci->need_io_watchdog) 148 return; 149 t = EHCI_IO_JIFFIES; 150 break; 151 case TIMER_ASYNC_OFF: 152 t = EHCI_ASYNC_JIFFIES; 153 break; 154 /* case TIMER_ASYNC_SHRINK: */ 155 default: 156 t = EHCI_SHRINK_JIFFIES; 157 break; 158 } 159 mod_timer(&ehci->watchdog, t + jiffies); 160 } 161 } 162 163 /*-------------------------------------------------------------------------*/ 164 165 /* 166 * handshake - spin reading hc until handshake completes or fails 167 * @ptr: address of hc register to be read 168 * @mask: bits to look at in result of read 169 * @done: value of those bits when handshake succeeds 170 * @usec: timeout in microseconds 171 * 172 * Returns negative errno, or zero on success 173 * 174 * Success happens when the "mask" bits have the specified value (hardware 175 * handshake done). There are two failure modes: "usec" have passed (major 176 * hardware flakeout), or the register reads as all-ones (hardware removed). 177 * 178 * That last failure should_only happen in cases like physical cardbus eject 179 * before driver shutdown. But it also seems to be caused by bugs in cardbus 180 * bridge shutdown: shutting down the bridge before the devices using it. 181 */ 182 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 183 u32 mask, u32 done, int usec) 184 { 185 u32 result; 186 187 do { 188 result = ehci_readl(ehci, ptr); 189 if (result == ~(u32)0) /* card removed */ 190 return -ENODEV; 191 result &= mask; 192 if (result == done) 193 return 0; 194 udelay (1); 195 usec--; 196 } while (usec > 0); 197 return -ETIMEDOUT; 198 } 199 200 /* check TDI/ARC silicon is in host mode */ 201 static int tdi_in_host_mode (struct ehci_hcd *ehci) 202 { 203 u32 __iomem *reg_ptr; 204 u32 tmp; 205 206 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 207 tmp = ehci_readl(ehci, reg_ptr); 208 return (tmp & 3) == USBMODE_CM_HC; 209 } 210 211 /* force HC to halt state from unknown (EHCI spec section 2.3) */ 212 static int ehci_halt (struct ehci_hcd *ehci) 213 { 214 u32 temp = ehci_readl(ehci, &ehci->regs->status); 215 216 /* disable any irqs left enabled by previous code */ 217 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 218 219 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 220 return 0; 221 } 222 223 if ((temp & STS_HALT) != 0) 224 return 0; 225 226 temp = ehci_readl(ehci, &ehci->regs->command); 227 temp &= ~CMD_RUN; 228 ehci_writel(ehci, temp, &ehci->regs->command); 229 return handshake (ehci, &ehci->regs->status, 230 STS_HALT, STS_HALT, 16 * 125); 231 } 232 233 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 234 u32 mask, u32 done, int usec) 235 { 236 int error; 237 238 error = handshake(ehci, ptr, mask, done, usec); 239 if (error) { 240 ehci_halt(ehci); 241 ehci->rh_state = EHCI_RH_HALTED; 242 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 243 ptr, mask, done, error); 244 } 245 246 return error; 247 } 248 249 /* put TDI/ARC silicon into EHCI mode */ 250 static void tdi_reset (struct ehci_hcd *ehci) 251 { 252 u32 __iomem *reg_ptr; 253 u32 tmp; 254 255 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 256 tmp = ehci_readl(ehci, reg_ptr); 257 tmp |= USBMODE_CM_HC; 258 /* The default byte access to MMR space is LE after 259 * controller reset. Set the required endian mode 260 * for transfer buffers to match the host microprocessor 261 */ 262 if (ehci_big_endian_mmio(ehci)) 263 tmp |= USBMODE_BE; 264 ehci_writel(ehci, tmp, reg_ptr); 265 } 266 267 /* reset a non-running (STS_HALT == 1) controller */ 268 static int ehci_reset (struct ehci_hcd *ehci) 269 { 270 int retval; 271 u32 command = ehci_readl(ehci, &ehci->regs->command); 272 273 /* If the EHCI debug controller is active, special care must be 274 * taken before and after a host controller reset */ 275 if (ehci->debug && !dbgp_reset_prep()) 276 ehci->debug = NULL; 277 278 command |= CMD_RESET; 279 dbg_cmd (ehci, "reset", command); 280 ehci_writel(ehci, command, &ehci->regs->command); 281 ehci->rh_state = EHCI_RH_HALTED; 282 ehci->next_statechange = jiffies; 283 retval = handshake (ehci, &ehci->regs->command, 284 CMD_RESET, 0, 250 * 1000); 285 286 if (ehci->has_hostpc) { 287 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 288 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 289 ehci_writel(ehci, TXFIFO_DEFAULT, 290 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 291 } 292 if (retval) 293 return retval; 294 295 if (ehci_is_TDI(ehci)) 296 tdi_reset (ehci); 297 298 if (ehci->debug) 299 dbgp_external_startup(); 300 301 return retval; 302 } 303 304 /* idle the controller (from running) */ 305 static void ehci_quiesce (struct ehci_hcd *ehci) 306 { 307 u32 temp; 308 309 #ifdef DEBUG 310 if (ehci->rh_state != EHCI_RH_RUNNING) 311 BUG (); 312 #endif 313 314 /* wait for any schedule enables/disables to take effect */ 315 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 316 temp &= STS_ASS | STS_PSS; 317 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 318 STS_ASS | STS_PSS, temp, 16 * 125)) 319 return; 320 321 /* then disable anything that's still active */ 322 temp = ehci_readl(ehci, &ehci->regs->command); 323 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 324 ehci_writel(ehci, temp, &ehci->regs->command); 325 326 /* hardware can take 16 microframes to turn off ... */ 327 handshake_on_error_set_halt(ehci, &ehci->regs->status, 328 STS_ASS | STS_PSS, 0, 16 * 125); 329 } 330 331 /*-------------------------------------------------------------------------*/ 332 333 static void end_unlink_async(struct ehci_hcd *ehci); 334 static void ehci_work(struct ehci_hcd *ehci); 335 336 #include "ehci-hub.c" 337 #include "ehci-lpm.c" 338 #include "ehci-mem.c" 339 #include "ehci-q.c" 340 #include "ehci-sched.c" 341 #include "ehci-sysfs.c" 342 343 /*-------------------------------------------------------------------------*/ 344 345 static void ehci_iaa_watchdog(unsigned long param) 346 { 347 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 348 unsigned long flags; 349 350 spin_lock_irqsave (&ehci->lock, flags); 351 352 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 353 * So we need this watchdog, but must protect it against both 354 * (a) SMP races against real IAA firing and retriggering, and 355 * (b) clean HC shutdown, when IAA watchdog was pending. 356 */ 357 if (ehci->reclaim 358 && !timer_pending(&ehci->iaa_watchdog) 359 && ehci->rh_state == EHCI_RH_RUNNING) { 360 u32 cmd, status; 361 362 /* If we get here, IAA is *REALLY* late. It's barely 363 * conceivable that the system is so busy that CMD_IAAD 364 * is still legitimately set, so let's be sure it's 365 * clear before we read STS_IAA. (The HC should clear 366 * CMD_IAAD when it sets STS_IAA.) 367 */ 368 cmd = ehci_readl(ehci, &ehci->regs->command); 369 if (cmd & CMD_IAAD) 370 ehci_writel(ehci, cmd & ~CMD_IAAD, 371 &ehci->regs->command); 372 373 /* If IAA is set here it either legitimately triggered 374 * before we cleared IAAD above (but _way_ late, so we'll 375 * still count it as lost) ... or a silicon erratum: 376 * - VIA seems to set IAA without triggering the IRQ; 377 * - IAAD potentially cleared without setting IAA. 378 */ 379 status = ehci_readl(ehci, &ehci->regs->status); 380 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 381 COUNT (ehci->stats.lost_iaa); 382 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 383 } 384 385 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 386 status, cmd); 387 end_unlink_async(ehci); 388 } 389 390 spin_unlock_irqrestore(&ehci->lock, flags); 391 } 392 393 static void ehci_watchdog(unsigned long param) 394 { 395 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 396 unsigned long flags; 397 398 spin_lock_irqsave(&ehci->lock, flags); 399 400 /* stop async processing after it's idled a bit */ 401 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 402 start_unlink_async (ehci, ehci->async); 403 404 /* ehci could run by timer, without IRQs ... */ 405 ehci_work (ehci); 406 407 spin_unlock_irqrestore (&ehci->lock, flags); 408 } 409 410 /* On some systems, leaving remote wakeup enabled prevents system shutdown. 411 * The firmware seems to think that powering off is a wakeup event! 412 * This routine turns off remote wakeup and everything else, on all ports. 413 */ 414 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 415 { 416 int port = HCS_N_PORTS(ehci->hcs_params); 417 418 while (port--) 419 ehci_writel(ehci, PORT_RWC_BITS, 420 &ehci->regs->port_status[port]); 421 } 422 423 /* 424 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 425 * Should be called with ehci->lock held. 426 */ 427 static void ehci_silence_controller(struct ehci_hcd *ehci) 428 { 429 ehci_halt(ehci); 430 ehci_turn_off_all_ports(ehci); 431 432 /* make BIOS/etc use companion controller during reboot */ 433 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 434 435 /* unblock posted writes */ 436 ehci_readl(ehci, &ehci->regs->configured_flag); 437 } 438 439 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 440 * This forcibly disables dma and IRQs, helping kexec and other cases 441 * where the next system software may expect clean state. 442 */ 443 static void ehci_shutdown(struct usb_hcd *hcd) 444 { 445 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 446 447 del_timer_sync(&ehci->watchdog); 448 del_timer_sync(&ehci->iaa_watchdog); 449 450 spin_lock_irq(&ehci->lock); 451 ehci_silence_controller(ehci); 452 spin_unlock_irq(&ehci->lock); 453 } 454 455 static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 456 { 457 unsigned port; 458 459 if (!HCS_PPC (ehci->hcs_params)) 460 return; 461 462 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 463 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 464 (void) ehci_hub_control(ehci_to_hcd(ehci), 465 is_on ? SetPortFeature : ClearPortFeature, 466 USB_PORT_FEAT_POWER, 467 port--, NULL, 0); 468 /* Flush those writes */ 469 ehci_readl(ehci, &ehci->regs->command); 470 msleep(20); 471 } 472 473 /*-------------------------------------------------------------------------*/ 474 475 /* 476 * ehci_work is called from some interrupts, timers, and so on. 477 * it calls driver completion functions, after dropping ehci->lock. 478 */ 479 static void ehci_work (struct ehci_hcd *ehci) 480 { 481 timer_action_done (ehci, TIMER_IO_WATCHDOG); 482 483 /* another CPU may drop ehci->lock during a schedule scan while 484 * it reports urb completions. this flag guards against bogus 485 * attempts at re-entrant schedule scanning. 486 */ 487 if (ehci->scanning) 488 return; 489 ehci->scanning = 1; 490 scan_async (ehci); 491 if (ehci->next_uframe != -1) 492 scan_periodic (ehci); 493 ehci->scanning = 0; 494 495 /* the IO watchdog guards against hardware or driver bugs that 496 * misplace IRQs, and should let us run completely without IRQs. 497 * such lossage has been observed on both VT6202 and VT8235. 498 */ 499 if (ehci->rh_state == EHCI_RH_RUNNING && 500 (ehci->async->qh_next.ptr != NULL || 501 ehci->periodic_sched != 0)) 502 timer_action (ehci, TIMER_IO_WATCHDOG); 503 } 504 505 /* 506 * Called when the ehci_hcd module is removed. 507 */ 508 static void ehci_stop (struct usb_hcd *hcd) 509 { 510 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 511 512 ehci_dbg (ehci, "stop\n"); 513 514 /* no more interrupts ... */ 515 del_timer_sync (&ehci->watchdog); 516 del_timer_sync(&ehci->iaa_watchdog); 517 518 spin_lock_irq(&ehci->lock); 519 if (ehci->rh_state == EHCI_RH_RUNNING) 520 ehci_quiesce (ehci); 521 522 ehci_silence_controller(ehci); 523 ehci_reset (ehci); 524 spin_unlock_irq(&ehci->lock); 525 526 remove_sysfs_files(ehci); 527 remove_debug_files (ehci); 528 529 /* root hub is shut down separately (first, when possible) */ 530 spin_lock_irq (&ehci->lock); 531 if (ehci->async) 532 ehci_work (ehci); 533 spin_unlock_irq (&ehci->lock); 534 ehci_mem_cleanup (ehci); 535 536 if (ehci->amd_pll_fix == 1) 537 usb_amd_dev_put(); 538 539 #ifdef EHCI_STATS 540 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 541 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 542 ehci->stats.lost_iaa); 543 ehci_dbg (ehci, "complete %ld unlink %ld\n", 544 ehci->stats.complete, ehci->stats.unlink); 545 #endif 546 547 dbg_status (ehci, "ehci_stop completed", 548 ehci_readl(ehci, &ehci->regs->status)); 549 } 550 551 /* one-time init, only for memory state */ 552 static int ehci_init(struct usb_hcd *hcd) 553 { 554 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 555 u32 temp; 556 int retval; 557 u32 hcc_params; 558 struct ehci_qh_hw *hw; 559 560 spin_lock_init(&ehci->lock); 561 562 /* 563 * keep io watchdog by default, those good HCDs could turn off it later 564 */ 565 ehci->need_io_watchdog = 1; 566 init_timer(&ehci->watchdog); 567 ehci->watchdog.function = ehci_watchdog; 568 ehci->watchdog.data = (unsigned long) ehci; 569 570 init_timer(&ehci->iaa_watchdog); 571 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 572 ehci->iaa_watchdog.data = (unsigned long) ehci; 573 574 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 575 576 /* 577 * by default set standard 80% (== 100 usec/uframe) max periodic 578 * bandwidth as required by USB 2.0 579 */ 580 ehci->uframe_periodic_max = 100; 581 582 /* 583 * hw default: 1K periodic list heads, one per frame. 584 * periodic_size can shrink by USBCMD update if hcc_params allows. 585 */ 586 ehci->periodic_size = DEFAULT_I_TDPS; 587 INIT_LIST_HEAD(&ehci->cached_itd_list); 588 INIT_LIST_HEAD(&ehci->cached_sitd_list); 589 590 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 591 /* periodic schedule size can be smaller than default */ 592 switch (EHCI_TUNE_FLS) { 593 case 0: ehci->periodic_size = 1024; break; 594 case 1: ehci->periodic_size = 512; break; 595 case 2: ehci->periodic_size = 256; break; 596 default: BUG(); 597 } 598 } 599 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 600 return retval; 601 602 /* controllers may cache some of the periodic schedule ... */ 603 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 604 ehci->i_thresh = 2 + 8; 605 else // N microframes cached 606 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 607 608 ehci->reclaim = NULL; 609 ehci->next_uframe = -1; 610 ehci->clock_frame = -1; 611 612 /* 613 * dedicate a qh for the async ring head, since we couldn't unlink 614 * a 'real' qh without stopping the async schedule [4.8]. use it 615 * as the 'reclamation list head' too. 616 * its dummy is used in hw_alt_next of many tds, to prevent the qh 617 * from automatically advancing to the next td after short reads. 618 */ 619 ehci->async->qh_next.qh = NULL; 620 hw = ehci->async->hw; 621 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 622 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 623 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 624 hw->hw_qtd_next = EHCI_LIST_END(ehci); 625 ehci->async->qh_state = QH_STATE_LINKED; 626 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 627 628 /* clear interrupt enables, set irq latency */ 629 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 630 log2_irq_thresh = 0; 631 temp = 1 << (16 + log2_irq_thresh); 632 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 633 ehci->has_ppcd = 1; 634 ehci_dbg(ehci, "enable per-port change event\n"); 635 temp |= CMD_PPCEE; 636 } 637 if (HCC_CANPARK(hcc_params)) { 638 /* HW default park == 3, on hardware that supports it (like 639 * NVidia and ALI silicon), maximizes throughput on the async 640 * schedule by avoiding QH fetches between transfers. 641 * 642 * With fast usb storage devices and NForce2, "park" seems to 643 * make problems: throughput reduction (!), data errors... 644 */ 645 if (park) { 646 park = min(park, (unsigned) 3); 647 temp |= CMD_PARK; 648 temp |= park << 8; 649 } 650 ehci_dbg(ehci, "park %d\n", park); 651 } 652 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 653 /* periodic schedule size can be smaller than default */ 654 temp &= ~(3 << 2); 655 temp |= (EHCI_TUNE_FLS << 2); 656 } 657 if (HCC_LPM(hcc_params)) { 658 /* support link power management EHCI 1.1 addendum */ 659 ehci_dbg(ehci, "support lpm\n"); 660 ehci->has_lpm = 1; 661 if (hird > 0xf) { 662 ehci_dbg(ehci, "hird %d invalid, use default 0", 663 hird); 664 hird = 0; 665 } 666 temp |= hird << 24; 667 } 668 ehci->command = temp; 669 670 /* Accept arbitrarily long scatter-gather lists */ 671 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 672 hcd->self.sg_tablesize = ~0; 673 return 0; 674 } 675 676 /* start HC running; it's halted, ehci_init() has been run (once) */ 677 static int ehci_run (struct usb_hcd *hcd) 678 { 679 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 680 int retval; 681 u32 temp; 682 u32 hcc_params; 683 684 hcd->uses_new_polling = 1; 685 686 /* EHCI spec section 4.1 */ 687 /* 688 * TDI driver does the ehci_reset in their reset callback. 689 * Don't reset here, because configuration settings will 690 * vanish. 691 */ 692 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) { 693 ehci_mem_cleanup(ehci); 694 return retval; 695 } 696 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 697 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 698 699 /* 700 * hcc_params controls whether ehci->regs->segment must (!!!) 701 * be used; it constrains QH/ITD/SITD and QTD locations. 702 * pci_pool consistent memory always uses segment zero. 703 * streaming mappings for I/O buffers, like pci_map_single(), 704 * can return segments above 4GB, if the device allows. 705 * 706 * NOTE: the dma mask is visible through dma_supported(), so 707 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 708 * Scsi_Host.highmem_io, and so forth. It's readonly to all 709 * host side drivers though. 710 */ 711 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 712 if (HCC_64BIT_ADDR(hcc_params)) { 713 ehci_writel(ehci, 0, &ehci->regs->segment); 714 #if 0 715 // this is deeply broken on almost all architectures 716 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 717 ehci_info(ehci, "enabled 64bit DMA\n"); 718 #endif 719 } 720 721 722 // Philips, Intel, and maybe others need CMD_RUN before the 723 // root hub will detect new devices (why?); NEC doesn't 724 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 725 ehci->command |= CMD_RUN; 726 ehci_writel(ehci, ehci->command, &ehci->regs->command); 727 dbg_cmd (ehci, "init", ehci->command); 728 729 /* 730 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 731 * are explicitly handed to companion controller(s), so no TT is 732 * involved with the root hub. (Except where one is integrated, 733 * and there's no companion controller unless maybe for USB OTG.) 734 * 735 * Turning on the CF flag will transfer ownership of all ports 736 * from the companions to the EHCI controller. If any of the 737 * companions are in the middle of a port reset at the time, it 738 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 739 * guarantees that no resets are in progress. After we set CF, 740 * a short delay lets the hardware catch up; new resets shouldn't 741 * be started before the port switching actions could complete. 742 */ 743 down_write(&ehci_cf_port_reset_rwsem); 744 ehci->rh_state = EHCI_RH_RUNNING; 745 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 746 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 747 msleep(5); 748 up_write(&ehci_cf_port_reset_rwsem); 749 ehci->last_periodic_enable = ktime_get_real(); 750 751 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 752 ehci_info (ehci, 753 "USB %x.%x started, EHCI %x.%02x%s\n", 754 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 755 temp >> 8, temp & 0xff, 756 ignore_oc ? ", overcurrent ignored" : ""); 757 758 ehci_writel(ehci, INTR_MASK, 759 &ehci->regs->intr_enable); /* Turn On Interrupts */ 760 761 /* GRR this is run-once init(), being done every time the HC starts. 762 * So long as they're part of class devices, we can't do it init() 763 * since the class device isn't created that early. 764 */ 765 create_debug_files(ehci); 766 create_sysfs_files(ehci); 767 768 return 0; 769 } 770 771 static int __maybe_unused ehci_setup (struct usb_hcd *hcd) 772 { 773 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 774 int retval; 775 776 ehci->regs = (void __iomem *)ehci->caps + 777 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 778 dbg_hcs_params(ehci, "reset"); 779 dbg_hcc_params(ehci, "reset"); 780 781 /* cache this readonly data; minimize chip reads */ 782 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 783 784 ehci->sbrn = HCD_USB2; 785 786 retval = ehci_halt(ehci); 787 if (retval) 788 return retval; 789 790 /* data structure init */ 791 retval = ehci_init(hcd); 792 if (retval) 793 return retval; 794 795 ehci_reset(ehci); 796 797 return 0; 798 } 799 800 /*-------------------------------------------------------------------------*/ 801 802 static irqreturn_t ehci_irq (struct usb_hcd *hcd) 803 { 804 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 805 u32 status, masked_status, pcd_status = 0, cmd; 806 int bh; 807 808 spin_lock (&ehci->lock); 809 810 status = ehci_readl(ehci, &ehci->regs->status); 811 812 /* e.g. cardbus physical eject */ 813 if (status == ~(u32) 0) { 814 ehci_dbg (ehci, "device removed\n"); 815 goto dead; 816 } 817 818 /* Shared IRQ? */ 819 masked_status = status & INTR_MASK; 820 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { 821 spin_unlock(&ehci->lock); 822 return IRQ_NONE; 823 } 824 825 /* clear (just) interrupts */ 826 ehci_writel(ehci, masked_status, &ehci->regs->status); 827 cmd = ehci_readl(ehci, &ehci->regs->command); 828 bh = 0; 829 830 #ifdef VERBOSE_DEBUG 831 /* unrequested/ignored: Frame List Rollover */ 832 dbg_status (ehci, "irq", status); 833 #endif 834 835 /* INT, ERR, and IAA interrupt rates can be throttled */ 836 837 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 838 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 839 if (likely ((status & STS_ERR) == 0)) 840 COUNT (ehci->stats.normal); 841 else 842 COUNT (ehci->stats.error); 843 bh = 1; 844 } 845 846 /* complete the unlinking of some qh [4.15.2.3] */ 847 if (status & STS_IAA) { 848 /* guard against (alleged) silicon errata */ 849 if (cmd & CMD_IAAD) { 850 ehci_writel(ehci, cmd & ~CMD_IAAD, 851 &ehci->regs->command); 852 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 853 } 854 if (ehci->reclaim) { 855 COUNT(ehci->stats.reclaim); 856 end_unlink_async(ehci); 857 } else 858 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 859 } 860 861 /* remote wakeup [4.3.1] */ 862 if (status & STS_PCD) { 863 unsigned i = HCS_N_PORTS (ehci->hcs_params); 864 u32 ppcd = 0; 865 866 /* kick root hub later */ 867 pcd_status = status; 868 869 /* resume root hub? */ 870 if (!(cmd & CMD_RUN)) 871 usb_hcd_resume_root_hub(hcd); 872 873 /* get per-port change detect bits */ 874 if (ehci->has_ppcd) 875 ppcd = status >> 16; 876 877 while (i--) { 878 int pstatus; 879 880 /* leverage per-port change bits feature */ 881 if (ehci->has_ppcd && !(ppcd & (1 << i))) 882 continue; 883 pstatus = ehci_readl(ehci, 884 &ehci->regs->port_status[i]); 885 886 if (pstatus & PORT_OWNER) 887 continue; 888 if (!(test_bit(i, &ehci->suspended_ports) && 889 ((pstatus & PORT_RESUME) || 890 !(pstatus & PORT_SUSPEND)) && 891 (pstatus & PORT_PE) && 892 ehci->reset_done[i] == 0)) 893 continue; 894 895 /* start 20 msec resume signaling from this port, 896 * and make khubd collect PORT_STAT_C_SUSPEND to 897 * stop that signaling. Use 5 ms extra for safety, 898 * like usb_port_resume() does. 899 */ 900 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 901 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 902 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 903 } 904 } 905 906 /* PCI errors [4.15.2.4] */ 907 if (unlikely ((status & STS_FATAL) != 0)) { 908 ehci_err(ehci, "fatal error\n"); 909 dbg_cmd(ehci, "fatal", cmd); 910 dbg_status(ehci, "fatal", status); 911 ehci_halt(ehci); 912 dead: 913 ehci_reset(ehci); 914 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 915 usb_hc_died(hcd); 916 /* generic layer kills/unlinks all urbs, then 917 * uses ehci_stop to clean up the rest 918 */ 919 bh = 1; 920 } 921 922 if (bh) 923 ehci_work (ehci); 924 spin_unlock (&ehci->lock); 925 if (pcd_status) 926 usb_hcd_poll_rh_status(hcd); 927 return IRQ_HANDLED; 928 } 929 930 /*-------------------------------------------------------------------------*/ 931 932 /* 933 * non-error returns are a promise to giveback() the urb later 934 * we drop ownership so next owner (or urb unlink) can get it 935 * 936 * urb + dev is in hcd.self.controller.urb_list 937 * we're queueing TDs onto software and hardware lists 938 * 939 * hcd-specific init for hcpriv hasn't been done yet 940 * 941 * NOTE: control, bulk, and interrupt share the same code to append TDs 942 * to a (possibly active) QH, and the same QH scanning code. 943 */ 944 static int ehci_urb_enqueue ( 945 struct usb_hcd *hcd, 946 struct urb *urb, 947 gfp_t mem_flags 948 ) { 949 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 950 struct list_head qtd_list; 951 952 INIT_LIST_HEAD (&qtd_list); 953 954 switch (usb_pipetype (urb->pipe)) { 955 case PIPE_CONTROL: 956 /* qh_completions() code doesn't handle all the fault cases 957 * in multi-TD control transfers. Even 1KB is rare anyway. 958 */ 959 if (urb->transfer_buffer_length > (16 * 1024)) 960 return -EMSGSIZE; 961 /* FALLTHROUGH */ 962 /* case PIPE_BULK: */ 963 default: 964 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 965 return -ENOMEM; 966 return submit_async(ehci, urb, &qtd_list, mem_flags); 967 968 case PIPE_INTERRUPT: 969 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 970 return -ENOMEM; 971 return intr_submit(ehci, urb, &qtd_list, mem_flags); 972 973 case PIPE_ISOCHRONOUS: 974 if (urb->dev->speed == USB_SPEED_HIGH) 975 return itd_submit (ehci, urb, mem_flags); 976 else 977 return sitd_submit (ehci, urb, mem_flags); 978 } 979 } 980 981 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 982 { 983 /* failfast */ 984 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) 985 end_unlink_async(ehci); 986 987 /* If the QH isn't linked then there's nothing we can do 988 * unless we were called during a giveback, in which case 989 * qh_completions() has to deal with it. 990 */ 991 if (qh->qh_state != QH_STATE_LINKED) { 992 if (qh->qh_state == QH_STATE_COMPLETING) 993 qh->needs_rescan = 1; 994 return; 995 } 996 997 /* defer till later if busy */ 998 if (ehci->reclaim) { 999 struct ehci_qh *last; 1000 1001 for (last = ehci->reclaim; 1002 last->reclaim; 1003 last = last->reclaim) 1004 continue; 1005 qh->qh_state = QH_STATE_UNLINK_WAIT; 1006 last->reclaim = qh; 1007 1008 /* start IAA cycle */ 1009 } else 1010 start_unlink_async (ehci, qh); 1011 } 1012 1013 /* remove from hardware lists 1014 * completions normally happen asynchronously 1015 */ 1016 1017 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 1018 { 1019 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1020 struct ehci_qh *qh; 1021 unsigned long flags; 1022 int rc; 1023 1024 spin_lock_irqsave (&ehci->lock, flags); 1025 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 1026 if (rc) 1027 goto done; 1028 1029 switch (usb_pipetype (urb->pipe)) { 1030 // case PIPE_CONTROL: 1031 // case PIPE_BULK: 1032 default: 1033 qh = (struct ehci_qh *) urb->hcpriv; 1034 if (!qh) 1035 break; 1036 switch (qh->qh_state) { 1037 case QH_STATE_LINKED: 1038 case QH_STATE_COMPLETING: 1039 unlink_async(ehci, qh); 1040 break; 1041 case QH_STATE_UNLINK: 1042 case QH_STATE_UNLINK_WAIT: 1043 /* already started */ 1044 break; 1045 case QH_STATE_IDLE: 1046 /* QH might be waiting for a Clear-TT-Buffer */ 1047 qh_completions(ehci, qh); 1048 break; 1049 } 1050 break; 1051 1052 case PIPE_INTERRUPT: 1053 qh = (struct ehci_qh *) urb->hcpriv; 1054 if (!qh) 1055 break; 1056 switch (qh->qh_state) { 1057 case QH_STATE_LINKED: 1058 case QH_STATE_COMPLETING: 1059 intr_deschedule (ehci, qh); 1060 break; 1061 case QH_STATE_IDLE: 1062 qh_completions (ehci, qh); 1063 break; 1064 default: 1065 ehci_dbg (ehci, "bogus qh %p state %d\n", 1066 qh, qh->qh_state); 1067 goto done; 1068 } 1069 break; 1070 1071 case PIPE_ISOCHRONOUS: 1072 // itd or sitd ... 1073 1074 // wait till next completion, do it then. 1075 // completion irqs can wait up to 1024 msec, 1076 break; 1077 } 1078 done: 1079 spin_unlock_irqrestore (&ehci->lock, flags); 1080 return rc; 1081 } 1082 1083 /*-------------------------------------------------------------------------*/ 1084 1085 // bulk qh holds the data toggle 1086 1087 static void 1088 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1089 { 1090 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1091 unsigned long flags; 1092 struct ehci_qh *qh, *tmp; 1093 1094 /* ASSERT: any requests/urbs are being unlinked */ 1095 /* ASSERT: nobody can be submitting urbs for this any more */ 1096 1097 rescan: 1098 spin_lock_irqsave (&ehci->lock, flags); 1099 qh = ep->hcpriv; 1100 if (!qh) 1101 goto done; 1102 1103 /* endpoints can be iso streams. for now, we don't 1104 * accelerate iso completions ... so spin a while. 1105 */ 1106 if (qh->hw == NULL) { 1107 ehci_vdbg (ehci, "iso delay\n"); 1108 goto idle_timeout; 1109 } 1110 1111 if (ehci->rh_state != EHCI_RH_RUNNING) 1112 qh->qh_state = QH_STATE_IDLE; 1113 switch (qh->qh_state) { 1114 case QH_STATE_LINKED: 1115 case QH_STATE_COMPLETING: 1116 for (tmp = ehci->async->qh_next.qh; 1117 tmp && tmp != qh; 1118 tmp = tmp->qh_next.qh) 1119 continue; 1120 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1121 * may already be unlinked. 1122 */ 1123 if (tmp) 1124 unlink_async(ehci, qh); 1125 /* FALL THROUGH */ 1126 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1127 case QH_STATE_UNLINK_WAIT: 1128 idle_timeout: 1129 spin_unlock_irqrestore (&ehci->lock, flags); 1130 schedule_timeout_uninterruptible(1); 1131 goto rescan; 1132 case QH_STATE_IDLE: /* fully unlinked */ 1133 if (qh->clearing_tt) 1134 goto idle_timeout; 1135 if (list_empty (&qh->qtd_list)) { 1136 qh_put (qh); 1137 break; 1138 } 1139 /* else FALL THROUGH */ 1140 default: 1141 /* caller was supposed to have unlinked any requests; 1142 * that's not our job. just leak this memory. 1143 */ 1144 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1145 qh, ep->desc.bEndpointAddress, qh->qh_state, 1146 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1147 break; 1148 } 1149 ep->hcpriv = NULL; 1150 done: 1151 spin_unlock_irqrestore (&ehci->lock, flags); 1152 } 1153 1154 static void 1155 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1156 { 1157 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1158 struct ehci_qh *qh; 1159 int eptype = usb_endpoint_type(&ep->desc); 1160 int epnum = usb_endpoint_num(&ep->desc); 1161 int is_out = usb_endpoint_dir_out(&ep->desc); 1162 unsigned long flags; 1163 1164 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1165 return; 1166 1167 spin_lock_irqsave(&ehci->lock, flags); 1168 qh = ep->hcpriv; 1169 1170 /* For Bulk and Interrupt endpoints we maintain the toggle state 1171 * in the hardware; the toggle bits in udev aren't used at all. 1172 * When an endpoint is reset by usb_clear_halt() we must reset 1173 * the toggle bit in the QH. 1174 */ 1175 if (qh) { 1176 usb_settoggle(qh->dev, epnum, is_out, 0); 1177 if (!list_empty(&qh->qtd_list)) { 1178 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1179 } else if (qh->qh_state == QH_STATE_LINKED || 1180 qh->qh_state == QH_STATE_COMPLETING) { 1181 1182 /* The toggle value in the QH can't be updated 1183 * while the QH is active. Unlink it now; 1184 * re-linking will call qh_refresh(). 1185 */ 1186 if (eptype == USB_ENDPOINT_XFER_BULK) 1187 unlink_async(ehci, qh); 1188 else 1189 intr_deschedule(ehci, qh); 1190 } 1191 } 1192 spin_unlock_irqrestore(&ehci->lock, flags); 1193 } 1194 1195 static int ehci_get_frame (struct usb_hcd *hcd) 1196 { 1197 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1198 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; 1199 } 1200 1201 /*-------------------------------------------------------------------------*/ 1202 1203 MODULE_DESCRIPTION(DRIVER_DESC); 1204 MODULE_AUTHOR (DRIVER_AUTHOR); 1205 MODULE_LICENSE ("GPL"); 1206 1207 #ifdef CONFIG_PCI 1208 #include "ehci-pci.c" 1209 #define PCI_DRIVER ehci_pci_driver 1210 #endif 1211 1212 #ifdef CONFIG_USB_EHCI_FSL 1213 #include "ehci-fsl.c" 1214 #define PLATFORM_DRIVER ehci_fsl_driver 1215 #endif 1216 1217 #ifdef CONFIG_USB_EHCI_MXC 1218 #include "ehci-mxc.c" 1219 #define PLATFORM_DRIVER ehci_mxc_driver 1220 #endif 1221 1222 #ifdef CONFIG_USB_EHCI_SH 1223 #include "ehci-sh.c" 1224 #define PLATFORM_DRIVER ehci_hcd_sh_driver 1225 #endif 1226 1227 #ifdef CONFIG_SOC_AU1200 1228 #include "ehci-au1xxx.c" 1229 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1230 #endif 1231 1232 #ifdef CONFIG_USB_EHCI_HCD_OMAP 1233 #include "ehci-omap.c" 1234 #define PLATFORM_DRIVER ehci_hcd_omap_driver 1235 #endif 1236 1237 #ifdef CONFIG_PPC_PS3 1238 #include "ehci-ps3.c" 1239 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1240 #endif 1241 1242 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1243 #include "ehci-ppc-of.c" 1244 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1245 #endif 1246 1247 #ifdef CONFIG_XPS_USB_HCD_XILINX 1248 #include "ehci-xilinx-of.c" 1249 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1250 #endif 1251 1252 #ifdef CONFIG_PLAT_ORION 1253 #include "ehci-orion.c" 1254 #define PLATFORM_DRIVER ehci_orion_driver 1255 #endif 1256 1257 #ifdef CONFIG_ARCH_IXP4XX 1258 #include "ehci-ixp4xx.c" 1259 #define PLATFORM_DRIVER ixp4xx_ehci_driver 1260 #endif 1261 1262 #ifdef CONFIG_USB_W90X900_EHCI 1263 #include "ehci-w90x900.c" 1264 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1265 #endif 1266 1267 #ifdef CONFIG_ARCH_AT91 1268 #include "ehci-atmel.c" 1269 #define PLATFORM_DRIVER ehci_atmel_driver 1270 #endif 1271 1272 #ifdef CONFIG_USB_OCTEON_EHCI 1273 #include "ehci-octeon.c" 1274 #define PLATFORM_DRIVER ehci_octeon_driver 1275 #endif 1276 1277 #ifdef CONFIG_USB_CNS3XXX_EHCI 1278 #include "ehci-cns3xxx.c" 1279 #define PLATFORM_DRIVER cns3xxx_ehci_driver 1280 #endif 1281 1282 #ifdef CONFIG_ARCH_VT8500 1283 #include "ehci-vt8500.c" 1284 #define PLATFORM_DRIVER vt8500_ehci_driver 1285 #endif 1286 1287 #ifdef CONFIG_PLAT_SPEAR 1288 #include "ehci-spear.c" 1289 #define PLATFORM_DRIVER spear_ehci_hcd_driver 1290 #endif 1291 1292 #ifdef CONFIG_USB_EHCI_MSM 1293 #include "ehci-msm.c" 1294 #define PLATFORM_DRIVER ehci_msm_driver 1295 #endif 1296 1297 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1298 #include "ehci-pmcmsp.c" 1299 #define PLATFORM_DRIVER ehci_hcd_msp_driver 1300 #endif 1301 1302 #ifdef CONFIG_USB_EHCI_TEGRA 1303 #include "ehci-tegra.c" 1304 #define PLATFORM_DRIVER tegra_ehci_driver 1305 #endif 1306 1307 #ifdef CONFIG_USB_EHCI_S5P 1308 #include "ehci-s5p.c" 1309 #define PLATFORM_DRIVER s5p_ehci_driver 1310 #endif 1311 1312 #ifdef CONFIG_USB_EHCI_ATH79 1313 #include "ehci-ath79.c" 1314 #define PLATFORM_DRIVER ehci_ath79_driver 1315 #endif 1316 1317 #ifdef CONFIG_SPARC_LEON 1318 #include "ehci-grlib.c" 1319 #define PLATFORM_DRIVER ehci_grlib_driver 1320 #endif 1321 1322 #ifdef CONFIG_USB_PXA168_EHCI 1323 #include "ehci-pxa168.c" 1324 #define PLATFORM_DRIVER ehci_pxa168_driver 1325 #endif 1326 1327 #ifdef CONFIG_NLM_XLR 1328 #include "ehci-xls.c" 1329 #define PLATFORM_DRIVER ehci_xls_driver 1330 #endif 1331 1332 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1333 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1334 !defined(XILINX_OF_PLATFORM_DRIVER) 1335 #error "missing bus glue for ehci-hcd" 1336 #endif 1337 1338 static int __init ehci_hcd_init(void) 1339 { 1340 int retval = 0; 1341 1342 if (usb_disabled()) 1343 return -ENODEV; 1344 1345 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1346 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1347 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1348 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1349 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1350 " before uhci_hcd and ohci_hcd, not after\n"); 1351 1352 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1353 hcd_name, 1354 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1355 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1356 1357 #ifdef DEBUG 1358 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1359 if (!ehci_debug_root) { 1360 retval = -ENOENT; 1361 goto err_debug; 1362 } 1363 #endif 1364 1365 #ifdef PLATFORM_DRIVER 1366 retval = platform_driver_register(&PLATFORM_DRIVER); 1367 if (retval < 0) 1368 goto clean0; 1369 #endif 1370 1371 #ifdef PCI_DRIVER 1372 retval = pci_register_driver(&PCI_DRIVER); 1373 if (retval < 0) 1374 goto clean1; 1375 #endif 1376 1377 #ifdef PS3_SYSTEM_BUS_DRIVER 1378 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1379 if (retval < 0) 1380 goto clean2; 1381 #endif 1382 1383 #ifdef OF_PLATFORM_DRIVER 1384 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1385 if (retval < 0) 1386 goto clean3; 1387 #endif 1388 1389 #ifdef XILINX_OF_PLATFORM_DRIVER 1390 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); 1391 if (retval < 0) 1392 goto clean4; 1393 #endif 1394 return retval; 1395 1396 #ifdef XILINX_OF_PLATFORM_DRIVER 1397 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ 1398 clean4: 1399 #endif 1400 #ifdef OF_PLATFORM_DRIVER 1401 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1402 clean3: 1403 #endif 1404 #ifdef PS3_SYSTEM_BUS_DRIVER 1405 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1406 clean2: 1407 #endif 1408 #ifdef PCI_DRIVER 1409 pci_unregister_driver(&PCI_DRIVER); 1410 clean1: 1411 #endif 1412 #ifdef PLATFORM_DRIVER 1413 platform_driver_unregister(&PLATFORM_DRIVER); 1414 clean0: 1415 #endif 1416 #ifdef DEBUG 1417 debugfs_remove(ehci_debug_root); 1418 ehci_debug_root = NULL; 1419 err_debug: 1420 #endif 1421 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1422 return retval; 1423 } 1424 module_init(ehci_hcd_init); 1425 1426 static void __exit ehci_hcd_cleanup(void) 1427 { 1428 #ifdef XILINX_OF_PLATFORM_DRIVER 1429 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); 1430 #endif 1431 #ifdef OF_PLATFORM_DRIVER 1432 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1433 #endif 1434 #ifdef PLATFORM_DRIVER 1435 platform_driver_unregister(&PLATFORM_DRIVER); 1436 #endif 1437 #ifdef PCI_DRIVER 1438 pci_unregister_driver(&PCI_DRIVER); 1439 #endif 1440 #ifdef PS3_SYSTEM_BUS_DRIVER 1441 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1442 #endif 1443 #ifdef DEBUG 1444 debugfs_remove(ehci_debug_root); 1445 #endif 1446 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1447 } 1448 module_exit(ehci_hcd_cleanup); 1449 1450