1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2005-2009 MontaVista Software, Inc. 4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. 5 * 6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided 7 * by Hunter Wu. 8 * Power Management support by Dave Liu <daveliu@freescale.com>, 9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and 10 * Anton Vorontsov <avorontsov@ru.mvista.com>. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/err.h> 19 #include <linux/usb.h> 20 #include <linux/usb/ehci_def.h> 21 #include <linux/usb/hcd.h> 22 #include <linux/usb/otg.h> 23 #include <linux/platform_device.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/of_platform.h> 26 27 #include "ehci.h" 28 #include "ehci-fsl.h" 29 30 #define DRIVER_DESC "Freescale EHCI Host controller driver" 31 #define DRV_NAME "ehci-fsl" 32 33 static struct hc_driver __read_mostly fsl_ehci_hc_driver; 34 35 /* configure so an HC device and id are always provided */ 36 /* always called with process context; sleeping is OK */ 37 38 /* 39 * fsl_ehci_drv_probe - initialize FSL-based HCDs 40 * @pdev: USB Host Controller being probed 41 * Context: !in_interrupt() 42 * 43 * Allocates basic resources for this USB host controller. 44 * 45 */ 46 static int fsl_ehci_drv_probe(struct platform_device *pdev) 47 { 48 struct fsl_usb2_platform_data *pdata; 49 struct usb_hcd *hcd; 50 struct resource *res; 51 int irq; 52 int retval; 53 54 pr_debug("initializing FSL-SOC USB Controller\n"); 55 56 /* Need platform data for setup */ 57 pdata = dev_get_platdata(&pdev->dev); 58 if (!pdata) { 59 dev_err(&pdev->dev, 60 "No platform data for %s.\n", dev_name(&pdev->dev)); 61 return -ENODEV; 62 } 63 64 /* 65 * This is a host mode driver, verify that we're supposed to be 66 * in host mode. 67 */ 68 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || 69 (pdata->operating_mode == FSL_USB2_MPH_HOST) || 70 (pdata->operating_mode == FSL_USB2_DR_OTG))) { 71 dev_err(&pdev->dev, 72 "Non Host Mode configured for %s. Wrong driver linked.\n", 73 dev_name(&pdev->dev)); 74 return -ENODEV; 75 } 76 77 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 78 if (!res) { 79 dev_err(&pdev->dev, 80 "Found HC with no IRQ. Check %s setup!\n", 81 dev_name(&pdev->dev)); 82 return -ENODEV; 83 } 84 irq = res->start; 85 86 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, 87 &pdev->dev, dev_name(&pdev->dev), NULL); 88 if (!hcd) { 89 retval = -ENOMEM; 90 goto err1; 91 } 92 93 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 94 hcd->regs = devm_ioremap_resource(&pdev->dev, res); 95 if (IS_ERR(hcd->regs)) { 96 retval = PTR_ERR(hcd->regs); 97 goto err2; 98 } 99 100 hcd->rsrc_start = res->start; 101 hcd->rsrc_len = resource_size(res); 102 103 pdata->regs = hcd->regs; 104 105 if (pdata->power_budget) 106 hcd->power_budget = pdata->power_budget; 107 108 /* 109 * do platform specific init: check the clock, grab/config pins, etc. 110 */ 111 if (pdata->init && pdata->init(pdev)) { 112 retval = -ENODEV; 113 goto err2; 114 } 115 116 /* Enable USB controller, 83xx or 8536 */ 117 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) 118 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, 119 CONTROL_REGISTER_W1C_MASK, 0x4); 120 121 /* 122 * Enable UTMI phy and program PTS field in UTMI mode before asserting 123 * controller reset for USB Controller version 2.5 124 */ 125 if (pdata->has_fsl_erratum_a007792) { 126 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, 127 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN); 128 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); 129 } 130 131 /* Don't need to set host mode here. It will be done by tdi_reset() */ 132 133 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 134 if (retval != 0) 135 goto err2; 136 device_wakeup_enable(hcd->self.controller); 137 138 #ifdef CONFIG_USB_OTG 139 if (pdata->operating_mode == FSL_USB2_DR_OTG) { 140 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 141 142 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); 143 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", 144 hcd, ehci, hcd->usb_phy); 145 146 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 147 retval = otg_set_host(hcd->usb_phy->otg, 148 &ehci_to_hcd(ehci)->self); 149 if (retval) { 150 usb_put_phy(hcd->usb_phy); 151 goto err2; 152 } 153 } else { 154 dev_err(&pdev->dev, "can't find phy\n"); 155 retval = -ENODEV; 156 goto err2; 157 } 158 159 hcd->skip_phy_initialization = 1; 160 } 161 #endif 162 return retval; 163 164 err2: 165 usb_put_hcd(hcd); 166 err1: 167 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); 168 if (pdata->exit) 169 pdata->exit(pdev); 170 return retval; 171 } 172 173 static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 174 enum fsl_usb2_phy_modes phy_mode, 175 unsigned int port_offset) 176 { 177 u32 portsc; 178 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 179 void __iomem *non_ehci = hcd->regs; 180 struct device *dev = hcd->self.controller; 181 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 182 183 if (pdata->controller_ver < 0) { 184 dev_warn(hcd->self.controller, "Could not get controller version\n"); 185 return -ENODEV; 186 } 187 188 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); 189 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); 190 191 switch (phy_mode) { 192 case FSL_USB2_PHY_ULPI: 193 if (pdata->have_sysif_regs && pdata->controller_ver) { 194 /* controller version 1.6 or above */ 195 clrbits32(non_ehci + FSL_SOC_USB_CTRL, 196 CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); 197 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, 198 CONTROL_REGISTER_W1C_MASK, 199 ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); 200 } 201 portsc |= PORT_PTS_ULPI; 202 break; 203 case FSL_USB2_PHY_SERIAL: 204 portsc |= PORT_PTS_SERIAL; 205 break; 206 case FSL_USB2_PHY_UTMI_WIDE: 207 portsc |= PORT_PTS_PTW; 208 /* fall through */ 209 case FSL_USB2_PHY_UTMI: 210 case FSL_USB2_PHY_UTMI_DUAL: 211 if (pdata->have_sysif_regs && pdata->controller_ver) { 212 /* controller version 1.6 or above */ 213 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, 214 CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN); 215 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to 216 become stable - 10ms*/ 217 } 218 /* enable UTMI PHY */ 219 if (pdata->have_sysif_regs) 220 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, 221 CONTROL_REGISTER_W1C_MASK, 222 CTRL_UTMI_PHY_EN); 223 portsc |= PORT_PTS_UTMI; 224 break; 225 case FSL_USB2_PHY_NONE: 226 break; 227 } 228 229 /* 230 * check PHY_CLK_VALID to determine phy clock presence before writing 231 * to portsc 232 */ 233 if (pdata->check_phy_clk_valid) { 234 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & 235 PHY_CLK_VALID)) { 236 dev_warn(hcd->self.controller, 237 "USB PHY clock invalid\n"); 238 return -EINVAL; 239 } 240 } 241 242 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 243 244 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) 245 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, 246 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN); 247 248 return 0; 249 } 250 251 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) 252 { 253 struct usb_hcd *hcd = ehci_to_hcd(ehci); 254 struct fsl_usb2_platform_data *pdata; 255 void __iomem *non_ehci = hcd->regs; 256 257 pdata = dev_get_platdata(hcd->self.controller); 258 259 if (pdata->have_sysif_regs) { 260 /* 261 * Turn on cache snooping hardware, since some PowerPC platforms 262 * wholly rely on hardware to deal with cache coherent 263 */ 264 265 /* Setup Snooping for all the 4GB space */ 266 /* SNOOP1 starts from 0x0, size 2G */ 267 iowrite32be(0x0 | SNOOP_SIZE_2GB, 268 non_ehci + FSL_SOC_USB_SNOOP1); 269 /* SNOOP2 starts from 0x80000000, size 2G */ 270 iowrite32be(0x80000000 | SNOOP_SIZE_2GB, 271 non_ehci + FSL_SOC_USB_SNOOP2); 272 } 273 274 /* Deal with USB erratum A-005275 */ 275 if (pdata->has_fsl_erratum_a005275 == 1) 276 ehci->has_fsl_hs_errata = 1; 277 278 if (pdata->has_fsl_erratum_a005697 == 1) 279 ehci->has_fsl_susp_errata = 1; 280 281 if ((pdata->operating_mode == FSL_USB2_DR_HOST) || 282 (pdata->operating_mode == FSL_USB2_DR_OTG)) 283 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 284 return -EINVAL; 285 286 if (pdata->operating_mode == FSL_USB2_MPH_HOST) { 287 unsigned int chip, rev, svr; 288 289 svr = mfspr(SPRN_SVR); 290 chip = svr >> 16; 291 rev = (svr >> 4) & 0xf; 292 293 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ 294 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) 295 ehci->has_fsl_port_bug = 1; 296 297 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) 298 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 299 return -EINVAL; 300 301 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) 302 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) 303 return -EINVAL; 304 } 305 306 if (pdata->have_sysif_regs) { 307 #ifdef CONFIG_FSL_SOC_BOOKE 308 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); 309 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 310 #else 311 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); 312 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 313 #endif 314 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); 315 } 316 317 return 0; 318 } 319 320 /* called after powerup, by probe or system-pm "wakeup" */ 321 static int ehci_fsl_reinit(struct ehci_hcd *ehci) 322 { 323 if (ehci_fsl_usb_setup(ehci)) 324 return -EINVAL; 325 326 return 0; 327 } 328 329 /* called during probe() after chip reset completes */ 330 static int ehci_fsl_setup(struct usb_hcd *hcd) 331 { 332 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 333 int retval; 334 struct fsl_usb2_platform_data *pdata; 335 struct device *dev; 336 337 dev = hcd->self.controller; 338 pdata = dev_get_platdata(hcd->self.controller); 339 ehci->big_endian_desc = pdata->big_endian_desc; 340 ehci->big_endian_mmio = pdata->big_endian_mmio; 341 342 /* EHCI registers start at offset 0x100 */ 343 ehci->caps = hcd->regs + 0x100; 344 345 #ifdef CONFIG_PPC_83xx 346 /* 347 * Deal with MPC834X that need port power to be cycled after the power 348 * fault condition is removed. Otherwise the state machine does not 349 * reflect PORTSC[CSC] correctly. 350 */ 351 ehci->need_oc_pp_cycle = 1; 352 #endif 353 354 hcd->has_tt = 1; 355 356 retval = ehci_setup(hcd); 357 if (retval) 358 return retval; 359 360 if (of_device_is_compatible(dev->parent->of_node, 361 "fsl,mpc5121-usb2-dr")) { 362 /* 363 * set SBUSCFG:AHBBRST so that control msgs don't 364 * fail when doing heavy PATA writes. 365 */ 366 ehci_writel(ehci, SBUSCFG_INCR8, 367 hcd->regs + FSL_SOC_USB_SBUSCFG); 368 } 369 370 retval = ehci_fsl_reinit(ehci); 371 return retval; 372 } 373 374 struct ehci_fsl { 375 struct ehci_hcd ehci; 376 377 #ifdef CONFIG_PM 378 /* Saved USB PHY settings, need to restore after deep sleep. */ 379 u32 usb_ctrl; 380 #endif 381 }; 382 383 #ifdef CONFIG_PM 384 385 #ifdef CONFIG_PPC_MPC512x 386 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 387 { 388 struct usb_hcd *hcd = dev_get_drvdata(dev); 389 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 390 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 391 u32 tmp; 392 393 #ifdef CONFIG_DYNAMIC_DEBUG 394 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); 395 mode &= USBMODE_CM_MASK; 396 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ 397 398 dev_dbg(dev, "suspend=%d already_suspended=%d " 399 "mode=%d usbcmd %08x\n", pdata->suspended, 400 pdata->already_suspended, mode, tmp); 401 #endif 402 403 /* 404 * If the controller is already suspended, then this must be a 405 * PM suspend. Remember this fact, so that we will leave the 406 * controller suspended at PM resume time. 407 */ 408 if (pdata->suspended) { 409 dev_dbg(dev, "already suspended, leaving early\n"); 410 pdata->already_suspended = 1; 411 return 0; 412 } 413 414 dev_dbg(dev, "suspending...\n"); 415 416 ehci->rh_state = EHCI_RH_SUSPENDED; 417 dev->power.power_state = PMSG_SUSPEND; 418 419 /* ignore non-host interrupts */ 420 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 421 422 /* stop the controller */ 423 tmp = ehci_readl(ehci, &ehci->regs->command); 424 tmp &= ~CMD_RUN; 425 ehci_writel(ehci, tmp, &ehci->regs->command); 426 427 /* save EHCI registers */ 428 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); 429 pdata->pm_command &= ~CMD_RUN; 430 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); 431 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); 432 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); 433 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); 434 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); 435 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); 436 pdata->pm_configured_flag = 437 ehci_readl(ehci, &ehci->regs->configured_flag); 438 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); 439 pdata->pm_usbgenctrl = ehci_readl(ehci, 440 hcd->regs + FSL_SOC_USB_USBGENCTRL); 441 442 /* clear the W1C bits */ 443 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); 444 445 pdata->suspended = 1; 446 447 /* clear PP to cut power to the port */ 448 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); 449 tmp &= ~PORT_POWER; 450 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); 451 452 return 0; 453 } 454 455 static int ehci_fsl_mpc512x_drv_resume(struct device *dev) 456 { 457 struct usb_hcd *hcd = dev_get_drvdata(dev); 458 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 459 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 460 u32 tmp; 461 462 dev_dbg(dev, "suspend=%d already_suspended=%d\n", 463 pdata->suspended, pdata->already_suspended); 464 465 /* 466 * If the controller was already suspended at suspend time, 467 * then don't resume it now. 468 */ 469 if (pdata->already_suspended) { 470 dev_dbg(dev, "already suspended, leaving early\n"); 471 pdata->already_suspended = 0; 472 return 0; 473 } 474 475 if (!pdata->suspended) { 476 dev_dbg(dev, "not suspended, leaving early\n"); 477 return 0; 478 } 479 480 pdata->suspended = 0; 481 482 dev_dbg(dev, "resuming...\n"); 483 484 /* set host mode */ 485 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); 486 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); 487 488 ehci_writel(ehci, pdata->pm_usbgenctrl, 489 hcd->regs + FSL_SOC_USB_USBGENCTRL); 490 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, 491 hcd->regs + FSL_SOC_USB_ISIPHYCTRL); 492 493 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); 494 495 /* restore EHCI registers */ 496 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); 497 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); 498 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); 499 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); 500 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); 501 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); 502 ehci_writel(ehci, pdata->pm_configured_flag, 503 &ehci->regs->configured_flag); 504 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); 505 506 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 507 ehci->rh_state = EHCI_RH_RUNNING; 508 dev->power.power_state = PMSG_ON; 509 510 tmp = ehci_readl(ehci, &ehci->regs->command); 511 tmp |= CMD_RUN; 512 ehci_writel(ehci, tmp, &ehci->regs->command); 513 514 usb_hcd_resume_root_hub(hcd); 515 516 return 0; 517 } 518 #else 519 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 520 { 521 return 0; 522 } 523 524 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) 525 { 526 return 0; 527 } 528 #endif /* CONFIG_PPC_MPC512x */ 529 530 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) 531 { 532 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 533 534 return container_of(ehci, struct ehci_fsl, ehci); 535 } 536 537 static int ehci_fsl_drv_suspend(struct device *dev) 538 { 539 struct usb_hcd *hcd = dev_get_drvdata(dev); 540 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 541 void __iomem *non_ehci = hcd->regs; 542 543 if (of_device_is_compatible(dev->parent->of_node, 544 "fsl,mpc5121-usb2-dr")) { 545 return ehci_fsl_mpc512x_drv_suspend(dev); 546 } 547 548 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), 549 device_may_wakeup(dev)); 550 if (!fsl_deep_sleep()) 551 return 0; 552 553 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 554 return 0; 555 } 556 557 static int ehci_fsl_drv_resume(struct device *dev) 558 { 559 struct usb_hcd *hcd = dev_get_drvdata(dev); 560 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 561 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 562 void __iomem *non_ehci = hcd->regs; 563 564 if (of_device_is_compatible(dev->parent->of_node, 565 "fsl,mpc5121-usb2-dr")) { 566 return ehci_fsl_mpc512x_drv_resume(dev); 567 } 568 569 ehci_prepare_ports_for_controller_resume(ehci); 570 if (!fsl_deep_sleep()) 571 return 0; 572 573 usb_root_hub_lost_power(hcd->self.root_hub); 574 575 /* Restore USB PHY settings and enable the controller. */ 576 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); 577 578 ehci_reset(ehci); 579 ehci_fsl_reinit(ehci); 580 581 return 0; 582 } 583 584 static int ehci_fsl_drv_restore(struct device *dev) 585 { 586 struct usb_hcd *hcd = dev_get_drvdata(dev); 587 588 usb_root_hub_lost_power(hcd->self.root_hub); 589 return 0; 590 } 591 592 static const struct dev_pm_ops ehci_fsl_pm_ops = { 593 .suspend = ehci_fsl_drv_suspend, 594 .resume = ehci_fsl_drv_resume, 595 .restore = ehci_fsl_drv_restore, 596 }; 597 598 #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) 599 #else 600 #define EHCI_FSL_PM_OPS NULL 601 #endif /* CONFIG_PM */ 602 603 #ifdef CONFIG_USB_OTG 604 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) 605 { 606 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 607 u32 status; 608 609 if (!port) 610 return -EINVAL; 611 612 port--; 613 614 /* start port reset before HNP protocol time out */ 615 status = readl(&ehci->regs->port_status[port]); 616 if (!(status & PORT_CONNECT)) 617 return -ENODEV; 618 619 /* hub_wq will finish the reset later */ 620 if (ehci_is_TDI(ehci)) { 621 writel(PORT_RESET | 622 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), 623 &ehci->regs->port_status[port]); 624 } else { 625 writel(PORT_RESET, &ehci->regs->port_status[port]); 626 } 627 628 return 0; 629 } 630 #else 631 #define ehci_start_port_reset NULL 632 #endif /* CONFIG_USB_OTG */ 633 634 static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { 635 .extra_priv_size = sizeof(struct ehci_fsl), 636 .reset = ehci_fsl_setup, 637 }; 638 639 /** 640 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs 641 * @dev: USB Host Controller being removed 642 * Context: !in_interrupt() 643 * 644 * Reverses the effect of usb_hcd_fsl_probe(). 645 * 646 */ 647 648 static int fsl_ehci_drv_remove(struct platform_device *pdev) 649 { 650 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 651 struct usb_hcd *hcd = platform_get_drvdata(pdev); 652 653 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 654 otg_set_host(hcd->usb_phy->otg, NULL); 655 usb_put_phy(hcd->usb_phy); 656 } 657 658 usb_remove_hcd(hcd); 659 660 /* 661 * do platform specific un-initialization: 662 * release iomux pins, disable clock, etc. 663 */ 664 if (pdata->exit) 665 pdata->exit(pdev); 666 usb_put_hcd(hcd); 667 668 return 0; 669 } 670 671 static struct platform_driver ehci_fsl_driver = { 672 .probe = fsl_ehci_drv_probe, 673 .remove = fsl_ehci_drv_remove, 674 .shutdown = usb_hcd_platform_shutdown, 675 .driver = { 676 .name = "fsl-ehci", 677 .pm = EHCI_FSL_PM_OPS, 678 }, 679 }; 680 681 static int __init ehci_fsl_init(void) 682 { 683 if (usb_disabled()) 684 return -ENODEV; 685 686 pr_info(DRV_NAME ": " DRIVER_DESC "\n"); 687 688 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); 689 690 fsl_ehci_hc_driver.product_desc = 691 "Freescale On-Chip EHCI Host Controller"; 692 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; 693 694 695 return platform_driver_register(&ehci_fsl_driver); 696 } 697 module_init(ehci_fsl_init); 698 699 static void __exit ehci_fsl_cleanup(void) 700 { 701 platform_driver_unregister(&ehci_fsl_driver); 702 } 703 module_exit(ehci_fsl_cleanup); 704 705 MODULE_DESCRIPTION(DRIVER_DESC); 706 MODULE_LICENSE("GPL"); 707 MODULE_ALIAS("platform:" DRV_NAME); 708