1 /* 2 * Xilinx USB peripheral controller driver 3 * 4 * Copyright (C) 2004 by Thomas Rathbone 5 * Copyright (C) 2005 by HP Labs 6 * Copyright (C) 2005 by David Brownell 7 * Copyright (C) 2010 - 2014 Xilinx, Inc. 8 * 9 * Some parts of this driver code is based on the driver for at91-series 10 * USB peripheral controller (at91_udc.c). 11 * 12 * This program is free software; you can redistribute it 13 * and/or modify it under the terms of the GNU General Public 14 * License as published by the Free Software Foundation; 15 * either version 2 of the License, or (at your option) any 16 * later version. 17 */ 18 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/module.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_irq.h> 29 #include <linux/prefetch.h> 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 33 /* Register offsets for the USB device.*/ 34 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */ 35 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */ 36 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */ 37 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */ 38 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */ 39 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */ 40 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */ 41 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */ 42 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */ 43 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */ 44 #define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */ 45 #define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */ 46 #define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */ 47 #define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */ 48 #define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */ 49 50 /* Endpoint Configuration Space offsets */ 51 #define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */ 52 #define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */ 53 #define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */ 54 55 #define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */ 56 #define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */ 57 58 /* Interrupt register related masks.*/ 59 #define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */ 60 #define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */ 61 #define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */ 62 #define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */ 63 #define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */ 64 #define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */ 65 #define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */ 66 #define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */ 67 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */ 68 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */ 69 #define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */ 70 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */ 71 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */ 72 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */ 73 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */ 74 #define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */ 75 /* Suspend,Reset,Suspend and Disconnect Mask */ 76 #define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000 77 /* Buffers completion Mask */ 78 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF 79 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */ 80 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101 81 #define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */ 82 83 /* Endpoint Configuration Status Register */ 84 #define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */ 85 #define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */ 86 #define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */ 87 88 /* USB device specific global configuration constants.*/ 89 #define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */ 90 #define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */ 91 /* DPRAM is the source address for DMA transfer */ 92 #define XUSB_DMA_READ_FROM_DPRAM 0x80000000 93 #define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */ 94 #define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */ 95 /* 96 * When this bit is set, the DMA buffer ready bit is set by hardware upon 97 * DMA transfer completion. 98 */ 99 #define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */ 100 /* Phase States */ 101 #define SETUP_PHASE 0x0000 /* Setup Phase */ 102 #define DATA_PHASE 0x0001 /* Data Phase */ 103 #define STATUS_PHASE 0x0002 /* Status Phase */ 104 105 #define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */ 106 #define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */ 107 #define EPNAME_SIZE 4 /* Buffer size for endpoint name */ 108 109 /* container_of helper macros */ 110 #define to_udc(g) container_of((g), struct xusb_udc, gadget) 111 #define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb) 112 #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req) 113 114 /** 115 * struct xusb_req - Xilinx USB device request structure 116 * @usb_req: Linux usb request structure 117 * @queue: usb device request queue 118 * @ep: pointer to xusb_endpoint structure 119 */ 120 struct xusb_req { 121 struct usb_request usb_req; 122 struct list_head queue; 123 struct xusb_ep *ep; 124 }; 125 126 /** 127 * struct xusb_ep - USB end point structure. 128 * @ep_usb: usb endpoint instance 129 * @queue: endpoint message queue 130 * @udc: xilinx usb peripheral driver instance pointer 131 * @desc: pointer to the usb endpoint descriptor 132 * @rambase: the endpoint buffer address 133 * @offset: the endpoint register offset value 134 * @name: name of the endpoint 135 * @epnumber: endpoint number 136 * @maxpacket: maximum packet size the endpoint can store 137 * @buffer0count: the size of the packet recieved in the first buffer 138 * @buffer1count: the size of the packet received in the second buffer 139 * @curbufnum: current buffer of endpoint that will be processed next 140 * @buffer0ready: the busy state of first buffer 141 * @buffer1ready: the busy state of second buffer 142 * @is_in: endpoint direction (IN or OUT) 143 * @is_iso: endpoint type(isochronous or non isochronous) 144 */ 145 struct xusb_ep { 146 struct usb_ep ep_usb; 147 struct list_head queue; 148 struct xusb_udc *udc; 149 const struct usb_endpoint_descriptor *desc; 150 u32 rambase; 151 u32 offset; 152 char name[4]; 153 u16 epnumber; 154 u16 maxpacket; 155 u16 buffer0count; 156 u16 buffer1count; 157 u8 curbufnum; 158 bool buffer0ready; 159 bool buffer1ready; 160 bool is_in; 161 bool is_iso; 162 }; 163 164 /** 165 * struct xusb_udc - USB peripheral driver structure 166 * @gadget: USB gadget driver instance 167 * @ep: an array of endpoint structures 168 * @driver: pointer to the usb gadget driver instance 169 * @setup: usb_ctrlrequest structure for control requests 170 * @req: pointer to dummy request for get status command 171 * @dev: pointer to device structure in gadget 172 * @usb_state: device in suspended state or not 173 * @remote_wkp: remote wakeup enabled by host 174 * @setupseqtx: tx status 175 * @setupseqrx: rx status 176 * @addr: the usb device base address 177 * @lock: instance of spinlock 178 * @dma_enabled: flag indicating whether the dma is included in the system 179 * @read_fn: function pointer to read device registers 180 * @write_fn: function pointer to write to device registers 181 */ 182 struct xusb_udc { 183 struct usb_gadget gadget; 184 struct xusb_ep ep[8]; 185 struct usb_gadget_driver *driver; 186 struct usb_ctrlrequest setup; 187 struct xusb_req *req; 188 struct device *dev; 189 u32 usb_state; 190 u32 remote_wkp; 191 u32 setupseqtx; 192 u32 setupseqrx; 193 void __iomem *addr; 194 spinlock_t lock; 195 bool dma_enabled; 196 197 unsigned int (*read_fn)(void __iomem *); 198 void (*write_fn)(void __iomem *, u32, u32); 199 }; 200 201 /* Endpoint buffer start addresses in the core */ 202 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 203 0x1600 }; 204 205 static const char driver_name[] = "xilinx-udc"; 206 static const char ep0name[] = "ep0"; 207 208 /* Control endpoint configuration.*/ 209 static const struct usb_endpoint_descriptor config_bulk_out_desc = { 210 .bLength = USB_DT_ENDPOINT_SIZE, 211 .bDescriptorType = USB_DT_ENDPOINT, 212 .bEndpointAddress = USB_DIR_OUT, 213 .bmAttributes = USB_ENDPOINT_XFER_BULK, 214 .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET), 215 }; 216 217 /** 218 * xudc_write32 - little endian write to device registers 219 * @addr: base addr of device registers 220 * @offset: register offset 221 * @val: data to be written 222 */ 223 static void xudc_write32(void __iomem *addr, u32 offset, u32 val) 224 { 225 iowrite32(val, addr + offset); 226 } 227 228 /** 229 * xudc_read32 - little endian read from device registers 230 * @addr: addr of device register 231 * Return: value at addr 232 */ 233 static unsigned int xudc_read32(void __iomem *addr) 234 { 235 return ioread32(addr); 236 } 237 238 /** 239 * xudc_write32_be - big endian write to device registers 240 * @addr: base addr of device registers 241 * @offset: register offset 242 * @val: data to be written 243 */ 244 static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val) 245 { 246 iowrite32be(val, addr + offset); 247 } 248 249 /** 250 * xudc_read32_be - big endian read from device registers 251 * @addr: addr of device register 252 * Return: value at addr 253 */ 254 static unsigned int xudc_read32_be(void __iomem *addr) 255 { 256 return ioread32be(addr); 257 } 258 259 /** 260 * xudc_wrstatus - Sets up the usb device status stages. 261 * @udc: pointer to the usb device controller structure. 262 */ 263 static void xudc_wrstatus(struct xusb_udc *udc) 264 { 265 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 266 u32 epcfgreg; 267 268 epcfgreg = udc->read_fn(udc->addr + ep0->offset)| 269 XUSB_EP_CFG_DATA_TOGGLE_MASK; 270 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 271 udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0); 272 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 273 } 274 275 /** 276 * xudc_epconfig - Configures the given endpoint. 277 * @ep: pointer to the usb device endpoint structure. 278 * @udc: pointer to the usb peripheral controller structure. 279 * 280 * This function configures a specific endpoint with the given configuration 281 * data. 282 */ 283 static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc) 284 { 285 u32 epcfgreg; 286 287 /* 288 * Configure the end point direction, type, Max Packet Size and the 289 * EP buffer location. 290 */ 291 epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) | 292 (ep->ep_usb.maxpacket << 15) | (ep->rambase)); 293 udc->write_fn(udc->addr, ep->offset, epcfgreg); 294 295 /* Set the Buffer count and the Buffer ready bits.*/ 296 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, 297 ep->buffer0count); 298 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, 299 ep->buffer1count); 300 if (ep->buffer0ready) 301 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 302 1 << ep->epnumber); 303 if (ep->buffer1ready) 304 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 305 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 306 } 307 308 /** 309 * xudc_start_dma - Starts DMA transfer. 310 * @ep: pointer to the usb device endpoint structure. 311 * @src: DMA source address. 312 * @dst: DMA destination address. 313 * @length: number of bytes to transfer. 314 * 315 * Return: 0 on success, error code on failure 316 * 317 * This function starts DMA transfer by writing to DMA source, 318 * destination and lenth registers. 319 */ 320 static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src, 321 dma_addr_t dst, u32 length) 322 { 323 struct xusb_udc *udc = ep->udc; 324 int rc = 0; 325 u32 timeout = 500; 326 u32 reg; 327 328 /* 329 * Set the addresses in the DMA source and 330 * destination registers and then set the length 331 * into the DMA length register. 332 */ 333 udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src); 334 udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst); 335 udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length); 336 337 /* 338 * Wait till DMA transaction is complete and 339 * check whether the DMA transaction was 340 * successful. 341 */ 342 do { 343 reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET); 344 if (!(reg & XUSB_DMA_DMASR_BUSY)) 345 break; 346 347 /* 348 * We can't sleep here, because it's also called from 349 * interrupt context. 350 */ 351 timeout--; 352 if (!timeout) { 353 dev_err(udc->dev, "DMA timeout\n"); 354 return -ETIMEDOUT; 355 } 356 udelay(1); 357 } while (1); 358 359 if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) & 360 XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){ 361 dev_err(udc->dev, "DMA Error\n"); 362 rc = -EINVAL; 363 } 364 365 return rc; 366 } 367 368 /** 369 * xudc_dma_send - Sends IN data using DMA. 370 * @ep: pointer to the usb device endpoint structure. 371 * @req: pointer to the usb request structure. 372 * @buffer: pointer to data to be sent. 373 * @length: number of bytes to send. 374 * 375 * Return: 0 on success, -EAGAIN if no buffer is free and error 376 * code on failure. 377 * 378 * This function sends data using DMA. 379 */ 380 static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req, 381 u8 *buffer, u32 length) 382 { 383 u32 *eprambase; 384 dma_addr_t src; 385 dma_addr_t dst; 386 struct xusb_udc *udc = ep->udc; 387 388 src = req->usb_req.dma + req->usb_req.actual; 389 if (req->usb_req.length) 390 dma_sync_single_for_device(udc->dev, src, 391 length, DMA_TO_DEVICE); 392 if (!ep->curbufnum && !ep->buffer0ready) { 393 /* Get the Buffer address and copy the transmit data.*/ 394 eprambase = (u32 __force *)(udc->addr + ep->rambase); 395 dst = virt_to_phys(eprambase); 396 udc->write_fn(udc->addr, ep->offset + 397 XUSB_EP_BUF0COUNT_OFFSET, length); 398 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 399 XUSB_DMA_BRR_CTRL | (1 << ep->epnumber)); 400 ep->buffer0ready = 1; 401 ep->curbufnum = 1; 402 } else if (ep->curbufnum && !ep->buffer1ready) { 403 /* Get the Buffer address and copy the transmit data.*/ 404 eprambase = (u32 __force *)(udc->addr + ep->rambase + 405 ep->ep_usb.maxpacket); 406 dst = virt_to_phys(eprambase); 407 udc->write_fn(udc->addr, ep->offset + 408 XUSB_EP_BUF1COUNT_OFFSET, length); 409 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 410 XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber + 411 XUSB_STATUS_EP_BUFF2_SHIFT))); 412 ep->buffer1ready = 1; 413 ep->curbufnum = 0; 414 } else { 415 /* None of ping pong buffers are ready currently .*/ 416 return -EAGAIN; 417 } 418 419 return xudc_start_dma(ep, src, dst, length); 420 } 421 422 /** 423 * xudc_dma_receive - Receives OUT data using DMA. 424 * @ep: pointer to the usb device endpoint structure. 425 * @req: pointer to the usb request structure. 426 * @buffer: pointer to storage buffer of received data. 427 * @length: number of bytes to receive. 428 * 429 * Return: 0 on success, -EAGAIN if no buffer is free and error 430 * code on failure. 431 * 432 * This function receives data using DMA. 433 */ 434 static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req, 435 u8 *buffer, u32 length) 436 { 437 u32 *eprambase; 438 dma_addr_t src; 439 dma_addr_t dst; 440 struct xusb_udc *udc = ep->udc; 441 442 dst = req->usb_req.dma + req->usb_req.actual; 443 if (!ep->curbufnum && !ep->buffer0ready) { 444 /* Get the Buffer address and copy the transmit data */ 445 eprambase = (u32 __force *)(udc->addr + ep->rambase); 446 src = virt_to_phys(eprambase); 447 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 448 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 449 (1 << ep->epnumber)); 450 ep->buffer0ready = 1; 451 ep->curbufnum = 1; 452 } else if (ep->curbufnum && !ep->buffer1ready) { 453 /* Get the Buffer address and copy the transmit data */ 454 eprambase = (u32 __force *)(udc->addr + 455 ep->rambase + ep->ep_usb.maxpacket); 456 src = virt_to_phys(eprambase); 457 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 458 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 459 (1 << (ep->epnumber + 460 XUSB_STATUS_EP_BUFF2_SHIFT))); 461 ep->buffer1ready = 1; 462 ep->curbufnum = 0; 463 } else { 464 /* None of the ping-pong buffers are ready currently */ 465 return -EAGAIN; 466 } 467 468 return xudc_start_dma(ep, src, dst, length); 469 } 470 471 /** 472 * xudc_eptxrx - Transmits or receives data to or from an endpoint. 473 * @ep: pointer to the usb endpoint configuration structure. 474 * @req: pointer to the usb request structure. 475 * @bufferptr: pointer to buffer containing the data to be sent. 476 * @bufferlen: The number of data bytes to be sent. 477 * 478 * Return: 0 on success, -EAGAIN if no buffer is free. 479 * 480 * This function copies the transmit/receive data to/from the end point buffer 481 * and enables the buffer for transmission/reception. 482 */ 483 static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, 484 u8 *bufferptr, u32 bufferlen) 485 { 486 u32 *eprambase; 487 u32 bytestosend; 488 int rc = 0; 489 struct xusb_udc *udc = ep->udc; 490 491 bytestosend = bufferlen; 492 if (udc->dma_enabled) { 493 if (ep->is_in) 494 rc = xudc_dma_send(ep, req, bufferptr, bufferlen); 495 else 496 rc = xudc_dma_receive(ep, req, bufferptr, bufferlen); 497 return rc; 498 } 499 /* Put the transmit buffer into the correct ping-pong buffer.*/ 500 if (!ep->curbufnum && !ep->buffer0ready) { 501 /* Get the Buffer address and copy the transmit data.*/ 502 eprambase = (u32 __force *)(udc->addr + ep->rambase); 503 if (ep->is_in) { 504 memcpy(eprambase, bufferptr, bytestosend); 505 udc->write_fn(udc->addr, ep->offset + 506 XUSB_EP_BUF0COUNT_OFFSET, bufferlen); 507 } else { 508 memcpy(bufferptr, eprambase, bytestosend); 509 } 510 /* 511 * Enable the buffer for transmission. 512 */ 513 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 514 1 << ep->epnumber); 515 ep->buffer0ready = 1; 516 ep->curbufnum = 1; 517 } else if (ep->curbufnum && !ep->buffer1ready) { 518 /* Get the Buffer address and copy the transmit data.*/ 519 eprambase = (u32 __force *)(udc->addr + ep->rambase + 520 ep->ep_usb.maxpacket); 521 if (ep->is_in) { 522 memcpy(eprambase, bufferptr, bytestosend); 523 udc->write_fn(udc->addr, ep->offset + 524 XUSB_EP_BUF1COUNT_OFFSET, bufferlen); 525 } else { 526 memcpy(bufferptr, eprambase, bytestosend); 527 } 528 /* 529 * Enable the buffer for transmission. 530 */ 531 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 532 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 533 ep->buffer1ready = 1; 534 ep->curbufnum = 0; 535 } else { 536 /* None of the ping-pong buffers are ready currently */ 537 return -EAGAIN; 538 } 539 return rc; 540 } 541 542 /** 543 * xudc_done - Exeutes the endpoint data transfer completion tasks. 544 * @ep: pointer to the usb device endpoint structure. 545 * @req: pointer to the usb request structure. 546 * @status: Status of the data transfer. 547 * 548 * Deletes the message from the queue and updates data transfer completion 549 * status. 550 */ 551 static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status) 552 { 553 struct xusb_udc *udc = ep->udc; 554 555 list_del_init(&req->queue); 556 557 if (req->usb_req.status == -EINPROGRESS) 558 req->usb_req.status = status; 559 else 560 status = req->usb_req.status; 561 562 if (status && status != -ESHUTDOWN) 563 dev_dbg(udc->dev, "%s done %p, status %d\n", 564 ep->ep_usb.name, req, status); 565 /* unmap request if DMA is present*/ 566 if (udc->dma_enabled && ep->epnumber && req->usb_req.length) 567 usb_gadget_unmap_request(&udc->gadget, &req->usb_req, 568 ep->is_in); 569 570 if (req->usb_req.complete) { 571 spin_unlock(&udc->lock); 572 req->usb_req.complete(&ep->ep_usb, &req->usb_req); 573 spin_lock(&udc->lock); 574 } 575 } 576 577 /** 578 * xudc_read_fifo - Reads the data from the given endpoint buffer. 579 * @ep: pointer to the usb device endpoint structure. 580 * @req: pointer to the usb request structure. 581 * 582 * Return: 0 if request is completed and -EAGAIN if not completed. 583 * 584 * Pulls OUT packet data from the endpoint buffer. 585 */ 586 static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req) 587 { 588 u8 *buf; 589 u32 is_short, count, bufferspace; 590 u8 bufoffset; 591 u8 two_pkts = 0; 592 int ret; 593 int retval = -EAGAIN; 594 struct xusb_udc *udc = ep->udc; 595 596 if (ep->buffer0ready && ep->buffer1ready) { 597 dev_dbg(udc->dev, "Packet NOT ready!\n"); 598 return retval; 599 } 600 top: 601 if (ep->curbufnum) 602 bufoffset = XUSB_EP_BUF1COUNT_OFFSET; 603 else 604 bufoffset = XUSB_EP_BUF0COUNT_OFFSET; 605 606 count = udc->read_fn(udc->addr + ep->offset + bufoffset); 607 608 if (!ep->buffer0ready && !ep->buffer1ready) 609 two_pkts = 1; 610 611 buf = req->usb_req.buf + req->usb_req.actual; 612 prefetchw(buf); 613 bufferspace = req->usb_req.length - req->usb_req.actual; 614 is_short = count < ep->ep_usb.maxpacket; 615 616 if (unlikely(!bufferspace)) { 617 /* 618 * This happens when the driver's buffer 619 * is smaller than what the host sent. 620 * discard the extra data. 621 */ 622 if (req->usb_req.status != -EOVERFLOW) 623 dev_dbg(udc->dev, "%s overflow %d\n", 624 ep->ep_usb.name, count); 625 req->usb_req.status = -EOVERFLOW; 626 xudc_done(ep, req, -EOVERFLOW); 627 return 0; 628 } 629 630 ret = xudc_eptxrx(ep, req, buf, count); 631 switch (ret) { 632 case 0: 633 req->usb_req.actual += min(count, bufferspace); 634 dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n", 635 ep->ep_usb.name, count, is_short ? "/S" : "", req, 636 req->usb_req.actual, req->usb_req.length); 637 bufferspace -= count; 638 /* Completion */ 639 if ((req->usb_req.actual == req->usb_req.length) || is_short) { 640 if (udc->dma_enabled && req->usb_req.length) 641 dma_sync_single_for_cpu(udc->dev, 642 req->usb_req.dma, 643 req->usb_req.actual, 644 DMA_FROM_DEVICE); 645 xudc_done(ep, req, 0); 646 return 0; 647 } 648 if (two_pkts) { 649 two_pkts = 0; 650 goto top; 651 } 652 break; 653 case -EAGAIN: 654 dev_dbg(udc->dev, "receive busy\n"); 655 break; 656 case -EINVAL: 657 case -ETIMEDOUT: 658 /* DMA error, dequeue the request */ 659 xudc_done(ep, req, -ECONNRESET); 660 retval = 0; 661 break; 662 } 663 664 return retval; 665 } 666 667 /** 668 * xudc_write_fifo - Writes data into the given endpoint buffer. 669 * @ep: pointer to the usb device endpoint structure. 670 * @req: pointer to the usb request structure. 671 * 672 * Return: 0 if request is completed and -EAGAIN if not completed. 673 * 674 * Loads endpoint buffer for an IN packet. 675 */ 676 static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req) 677 { 678 u32 max; 679 u32 length; 680 int ret; 681 int retval = -EAGAIN; 682 struct xusb_udc *udc = ep->udc; 683 int is_last, is_short = 0; 684 u8 *buf; 685 686 max = le16_to_cpu(ep->desc->wMaxPacketSize); 687 buf = req->usb_req.buf + req->usb_req.actual; 688 prefetch(buf); 689 length = req->usb_req.length - req->usb_req.actual; 690 length = min(length, max); 691 692 ret = xudc_eptxrx(ep, req, buf, length); 693 switch (ret) { 694 case 0: 695 req->usb_req.actual += length; 696 if (unlikely(length != max)) { 697 is_last = is_short = 1; 698 } else { 699 if (likely(req->usb_req.length != 700 req->usb_req.actual) || req->usb_req.zero) 701 is_last = 0; 702 else 703 is_last = 1; 704 } 705 dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n", 706 __func__, ep->ep_usb.name, length, is_last ? "/L" : "", 707 is_short ? "/S" : "", 708 req->usb_req.length - req->usb_req.actual, req); 709 /* completion */ 710 if (is_last) { 711 xudc_done(ep, req, 0); 712 retval = 0; 713 } 714 break; 715 case -EAGAIN: 716 dev_dbg(udc->dev, "Send busy\n"); 717 break; 718 case -EINVAL: 719 case -ETIMEDOUT: 720 /* DMA error, dequeue the request */ 721 xudc_done(ep, req, -ECONNRESET); 722 retval = 0; 723 break; 724 } 725 726 return retval; 727 } 728 729 /** 730 * xudc_nuke - Cleans up the data transfer message list. 731 * @ep: pointer to the usb device endpoint structure. 732 * @status: Status of the data transfer. 733 */ 734 static void xudc_nuke(struct xusb_ep *ep, int status) 735 { 736 struct xusb_req *req; 737 738 while (!list_empty(&ep->queue)) { 739 req = list_first_entry(&ep->queue, struct xusb_req, queue); 740 xudc_done(ep, req, status); 741 } 742 } 743 744 /** 745 * xudc_ep_set_halt - Stalls/unstalls the given endpoint. 746 * @_ep: pointer to the usb device endpoint structure. 747 * @value: value to indicate stall/unstall. 748 * 749 * Return: 0 for success and error value on failure 750 */ 751 static int xudc_ep_set_halt(struct usb_ep *_ep, int value) 752 { 753 struct xusb_ep *ep = to_xusb_ep(_ep); 754 struct xusb_udc *udc; 755 unsigned long flags; 756 u32 epcfgreg; 757 758 if (!_ep || (!ep->desc && ep->epnumber)) { 759 pr_debug("%s: bad ep or descriptor\n", __func__); 760 return -EINVAL; 761 } 762 udc = ep->udc; 763 764 if (ep->is_in && (!list_empty(&ep->queue)) && value) { 765 dev_dbg(udc->dev, "requests pending can't halt\n"); 766 return -EAGAIN; 767 } 768 769 if (ep->buffer0ready || ep->buffer1ready) { 770 dev_dbg(udc->dev, "HW buffers busy can't halt\n"); 771 return -EAGAIN; 772 } 773 774 spin_lock_irqsave(&udc->lock, flags); 775 776 if (value) { 777 /* Stall the device.*/ 778 epcfgreg = udc->read_fn(udc->addr + ep->offset); 779 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 780 udc->write_fn(udc->addr, ep->offset, epcfgreg); 781 } else { 782 /* Unstall the device.*/ 783 epcfgreg = udc->read_fn(udc->addr + ep->offset); 784 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 785 udc->write_fn(udc->addr, ep->offset, epcfgreg); 786 if (ep->epnumber) { 787 /* Reset the toggle bit.*/ 788 epcfgreg = udc->read_fn(ep->udc->addr + ep->offset); 789 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 790 udc->write_fn(udc->addr, ep->offset, epcfgreg); 791 } 792 } 793 794 spin_unlock_irqrestore(&udc->lock, flags); 795 return 0; 796 } 797 798 /** 799 * xudc_ep_enable - Enables the given endpoint. 800 * @ep: pointer to the xusb endpoint structure. 801 * @desc: pointer to usb endpoint descriptor. 802 * 803 * Return: 0 for success and error value on failure 804 */ 805 static int __xudc_ep_enable(struct xusb_ep *ep, 806 const struct usb_endpoint_descriptor *desc) 807 { 808 struct xusb_udc *udc = ep->udc; 809 u32 tmp; 810 u32 epcfg; 811 u32 ier; 812 u16 maxpacket; 813 814 ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0); 815 /* Bit 3...0:endpoint number */ 816 ep->epnumber = (desc->bEndpointAddress & 0x0f); 817 ep->desc = desc; 818 ep->ep_usb.desc = desc; 819 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 820 ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize); 821 822 switch (tmp) { 823 case USB_ENDPOINT_XFER_CONTROL: 824 dev_dbg(udc->dev, "only one control endpoint\n"); 825 /* NON- ISO */ 826 ep->is_iso = 0; 827 return -EINVAL; 828 case USB_ENDPOINT_XFER_INT: 829 /* NON- ISO */ 830 ep->is_iso = 0; 831 if (maxpacket > 64) { 832 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 833 return -EINVAL; 834 } 835 break; 836 case USB_ENDPOINT_XFER_BULK: 837 /* NON- ISO */ 838 ep->is_iso = 0; 839 if (!(is_power_of_2(maxpacket) && maxpacket >= 8 && 840 maxpacket <= 512)) { 841 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 842 return -EINVAL; 843 } 844 break; 845 case USB_ENDPOINT_XFER_ISOC: 846 /* ISO */ 847 ep->is_iso = 1; 848 break; 849 } 850 851 ep->buffer0ready = 0; 852 ep->buffer1ready = 0; 853 ep->curbufnum = 0; 854 ep->rambase = rambase[ep->epnumber]; 855 xudc_epconfig(ep, udc); 856 857 dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n", 858 ep->epnumber, maxpacket); 859 860 /* Enable the End point.*/ 861 epcfg = udc->read_fn(udc->addr + ep->offset); 862 epcfg |= XUSB_EP_CFG_VALID_MASK; 863 udc->write_fn(udc->addr, ep->offset, epcfg); 864 if (ep->epnumber) 865 ep->rambase <<= 2; 866 867 /* Enable buffer completion interrupts for endpoint */ 868 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 869 ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber); 870 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 871 872 /* for OUT endpoint set buffers ready to receive */ 873 if (ep->epnumber && !ep->is_in) { 874 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 875 1 << ep->epnumber); 876 ep->buffer0ready = 1; 877 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 878 (1 << (ep->epnumber + 879 XUSB_STATUS_EP_BUFF2_SHIFT))); 880 ep->buffer1ready = 1; 881 } 882 883 return 0; 884 } 885 886 /** 887 * xudc_ep_enable - Enables the given endpoint. 888 * @_ep: pointer to the usb endpoint structure. 889 * @desc: pointer to usb endpoint descriptor. 890 * 891 * Return: 0 for success and error value on failure 892 */ 893 static int xudc_ep_enable(struct usb_ep *_ep, 894 const struct usb_endpoint_descriptor *desc) 895 { 896 struct xusb_ep *ep; 897 struct xusb_udc *udc; 898 unsigned long flags; 899 int ret; 900 901 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 902 pr_debug("%s: bad ep or descriptor\n", __func__); 903 return -EINVAL; 904 } 905 906 ep = to_xusb_ep(_ep); 907 udc = ep->udc; 908 909 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 910 dev_dbg(udc->dev, "bogus device state\n"); 911 return -ESHUTDOWN; 912 } 913 914 spin_lock_irqsave(&udc->lock, flags); 915 ret = __xudc_ep_enable(ep, desc); 916 spin_unlock_irqrestore(&udc->lock, flags); 917 918 return ret; 919 } 920 921 /** 922 * xudc_ep_disable - Disables the given endpoint. 923 * @_ep: pointer to the usb endpoint structure. 924 * 925 * Return: 0 for success and error value on failure 926 */ 927 static int xudc_ep_disable(struct usb_ep *_ep) 928 { 929 struct xusb_ep *ep; 930 unsigned long flags; 931 u32 epcfg; 932 struct xusb_udc *udc; 933 934 if (!_ep) { 935 pr_debug("%s: invalid ep\n", __func__); 936 return -EINVAL; 937 } 938 939 ep = to_xusb_ep(_ep); 940 udc = ep->udc; 941 942 spin_lock_irqsave(&udc->lock, flags); 943 944 xudc_nuke(ep, -ESHUTDOWN); 945 946 /* Restore the endpoint's pristine config */ 947 ep->desc = NULL; 948 ep->ep_usb.desc = NULL; 949 950 dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber); 951 /* Disable the endpoint.*/ 952 epcfg = udc->read_fn(udc->addr + ep->offset); 953 epcfg &= ~XUSB_EP_CFG_VALID_MASK; 954 udc->write_fn(udc->addr, ep->offset, epcfg); 955 956 spin_unlock_irqrestore(&udc->lock, flags); 957 return 0; 958 } 959 960 /** 961 * xudc_ep_alloc_request - Initializes the request queue. 962 * @_ep: pointer to the usb endpoint structure. 963 * @gfp_flags: Flags related to the request call. 964 * 965 * Return: pointer to request structure on success and a NULL on failure. 966 */ 967 static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep, 968 gfp_t gfp_flags) 969 { 970 struct xusb_ep *ep = to_xusb_ep(_ep); 971 struct xusb_udc *udc; 972 struct xusb_req *req; 973 974 udc = ep->udc; 975 req = kzalloc(sizeof(*req), gfp_flags); 976 if (!req) { 977 dev_err(udc->dev, "%s:not enough memory", __func__); 978 return NULL; 979 } 980 981 req->ep = ep; 982 INIT_LIST_HEAD(&req->queue); 983 return &req->usb_req; 984 } 985 986 /** 987 * xudc_free_request - Releases the request from queue. 988 * @_ep: pointer to the usb device endpoint structure. 989 * @_req: pointer to the usb request structure. 990 */ 991 static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req) 992 { 993 struct xusb_req *req = to_xusb_req(_req); 994 995 kfree(req); 996 } 997 998 /** 999 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 1000 * @ep0: pointer to the xusb endpoint 0 structure. 1001 * @req: pointer to the xusb request structure. 1002 * 1003 * Return: 0 for success and error value on failure 1004 */ 1005 static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) 1006 { 1007 struct xusb_udc *udc = ep0->udc; 1008 u32 length; 1009 u8 *corebuf; 1010 1011 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1012 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1013 return -EINVAL; 1014 } 1015 if (!list_empty(&ep0->queue)) { 1016 dev_dbg(udc->dev, "%s:ep0 busy\n", __func__); 1017 return -EBUSY; 1018 } 1019 1020 req->usb_req.status = -EINPROGRESS; 1021 req->usb_req.actual = 0; 1022 1023 list_add_tail(&req->queue, &ep0->queue); 1024 1025 if (udc->setup.bRequestType & USB_DIR_IN) { 1026 prefetch(req->usb_req.buf); 1027 length = req->usb_req.length; 1028 corebuf = (void __force *) ((ep0->rambase << 2) + 1029 udc->addr); 1030 length = req->usb_req.actual = min_t(u32, length, 1031 EP0_MAX_PACKET); 1032 memcpy(corebuf, req->usb_req.buf, length); 1033 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); 1034 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1035 } else { 1036 if (udc->setup.wLength) { 1037 /* Enable EP0 buffer to receive data */ 1038 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1039 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1040 } else { 1041 xudc_wrstatus(udc); 1042 } 1043 } 1044 1045 return 0; 1046 } 1047 1048 /** 1049 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 1050 * @_ep: pointer to the usb endpoint 0 structure. 1051 * @_req: pointer to the usb request structure. 1052 * @gfp_flags: Flags related to the request call. 1053 * 1054 * Return: 0 for success and error value on failure 1055 */ 1056 static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req, 1057 gfp_t gfp_flags) 1058 { 1059 struct xusb_req *req = to_xusb_req(_req); 1060 struct xusb_ep *ep0 = to_xusb_ep(_ep); 1061 struct xusb_udc *udc = ep0->udc; 1062 unsigned long flags; 1063 int ret; 1064 1065 spin_lock_irqsave(&udc->lock, flags); 1066 ret = __xudc_ep0_queue(ep0, req); 1067 spin_unlock_irqrestore(&udc->lock, flags); 1068 1069 return ret; 1070 } 1071 1072 /** 1073 * xudc_ep_queue - Adds the request to endpoint queue. 1074 * @_ep: pointer to the usb endpoint structure. 1075 * @_req: pointer to the usb request structure. 1076 * @gfp_flags: Flags related to the request call. 1077 * 1078 * Return: 0 for success and error value on failure 1079 */ 1080 static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1081 gfp_t gfp_flags) 1082 { 1083 struct xusb_req *req = to_xusb_req(_req); 1084 struct xusb_ep *ep = to_xusb_ep(_ep); 1085 struct xusb_udc *udc = ep->udc; 1086 int ret; 1087 unsigned long flags; 1088 1089 if (!ep->desc) { 1090 dev_dbg(udc->dev, "%s:queing request to disabled %s\n", 1091 __func__, ep->name); 1092 return -ESHUTDOWN; 1093 } 1094 1095 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1096 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1097 return -EINVAL; 1098 } 1099 1100 spin_lock_irqsave(&udc->lock, flags); 1101 1102 _req->status = -EINPROGRESS; 1103 _req->actual = 0; 1104 1105 if (udc->dma_enabled) { 1106 ret = usb_gadget_map_request(&udc->gadget, &req->usb_req, 1107 ep->is_in); 1108 if (ret) { 1109 dev_dbg(udc->dev, "gadget_map failed ep%d\n", 1110 ep->epnumber); 1111 spin_unlock_irqrestore(&udc->lock, flags); 1112 return -EAGAIN; 1113 } 1114 } 1115 1116 if (list_empty(&ep->queue)) { 1117 if (ep->is_in) { 1118 dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n"); 1119 if (!xudc_write_fifo(ep, req)) 1120 req = NULL; 1121 } else { 1122 dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n"); 1123 if (!xudc_read_fifo(ep, req)) 1124 req = NULL; 1125 } 1126 } 1127 1128 if (req != NULL) 1129 list_add_tail(&req->queue, &ep->queue); 1130 1131 spin_unlock_irqrestore(&udc->lock, flags); 1132 return 0; 1133 } 1134 1135 /** 1136 * xudc_ep_dequeue - Removes the request from the queue. 1137 * @_ep: pointer to the usb device endpoint structure. 1138 * @_req: pointer to the usb request structure. 1139 * 1140 * Return: 0 for success and error value on failure 1141 */ 1142 static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1143 { 1144 struct xusb_ep *ep = to_xusb_ep(_ep); 1145 struct xusb_req *req = to_xusb_req(_req); 1146 struct xusb_udc *udc = ep->udc; 1147 unsigned long flags; 1148 1149 spin_lock_irqsave(&udc->lock, flags); 1150 /* Make sure it's actually queued on this endpoint */ 1151 list_for_each_entry(req, &ep->queue, queue) { 1152 if (&req->usb_req == _req) 1153 break; 1154 } 1155 if (&req->usb_req != _req) { 1156 spin_unlock_irqrestore(&ep->udc->lock, flags); 1157 return -EINVAL; 1158 } 1159 xudc_done(ep, req, -ECONNRESET); 1160 spin_unlock_irqrestore(&udc->lock, flags); 1161 1162 return 0; 1163 } 1164 1165 /** 1166 * xudc_ep0_enable - Enables the given endpoint. 1167 * @ep: pointer to the usb endpoint structure. 1168 * @desc: pointer to usb endpoint descriptor. 1169 * 1170 * Return: error always. 1171 * 1172 * endpoint 0 enable should not be called by gadget layer. 1173 */ 1174 static int xudc_ep0_enable(struct usb_ep *ep, 1175 const struct usb_endpoint_descriptor *desc) 1176 { 1177 return -EINVAL; 1178 } 1179 1180 /** 1181 * xudc_ep0_disable - Disables the given endpoint. 1182 * @ep: pointer to the usb endpoint structure. 1183 * 1184 * Return: error always. 1185 * 1186 * endpoint 0 disable should not be called by gadget layer. 1187 */ 1188 static int xudc_ep0_disable(struct usb_ep *ep) 1189 { 1190 return -EINVAL; 1191 } 1192 1193 static const struct usb_ep_ops xusb_ep0_ops = { 1194 .enable = xudc_ep0_enable, 1195 .disable = xudc_ep0_disable, 1196 .alloc_request = xudc_ep_alloc_request, 1197 .free_request = xudc_free_request, 1198 .queue = xudc_ep0_queue, 1199 .dequeue = xudc_ep_dequeue, 1200 .set_halt = xudc_ep_set_halt, 1201 }; 1202 1203 static const struct usb_ep_ops xusb_ep_ops = { 1204 .enable = xudc_ep_enable, 1205 .disable = xudc_ep_disable, 1206 .alloc_request = xudc_ep_alloc_request, 1207 .free_request = xudc_free_request, 1208 .queue = xudc_ep_queue, 1209 .dequeue = xudc_ep_dequeue, 1210 .set_halt = xudc_ep_set_halt, 1211 }; 1212 1213 /** 1214 * xudc_get_frame - Reads the current usb frame number. 1215 * @gadget: pointer to the usb gadget structure. 1216 * 1217 * Return: current frame number for success and error value on failure. 1218 */ 1219 static int xudc_get_frame(struct usb_gadget *gadget) 1220 { 1221 struct xusb_udc *udc; 1222 int frame; 1223 1224 if (!gadget) 1225 return -ENODEV; 1226 1227 udc = to_udc(gadget); 1228 frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET); 1229 return frame; 1230 } 1231 1232 /** 1233 * xudc_wakeup - Send remote wakeup signal to host 1234 * @gadget: pointer to the usb gadget structure. 1235 * 1236 * Return: 0 on success and error on failure 1237 */ 1238 static int xudc_wakeup(struct usb_gadget *gadget) 1239 { 1240 struct xusb_udc *udc = to_udc(gadget); 1241 u32 crtlreg; 1242 int status = -EINVAL; 1243 unsigned long flags; 1244 1245 spin_lock_irqsave(&udc->lock, flags); 1246 1247 /* Remote wake up not enabled by host */ 1248 if (!udc->remote_wkp) 1249 goto done; 1250 1251 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1252 crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK; 1253 /* set remote wake up bit */ 1254 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1255 /* 1256 * wait for a while and reset remote wake up bit since this bit 1257 * is not cleared by HW after sending remote wakeup to host. 1258 */ 1259 mdelay(2); 1260 1261 crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK; 1262 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1263 status = 0; 1264 done: 1265 spin_unlock_irqrestore(&udc->lock, flags); 1266 return status; 1267 } 1268 1269 /** 1270 * xudc_pullup - start/stop USB traffic 1271 * @gadget: pointer to the usb gadget structure. 1272 * @is_on: flag to start or stop 1273 * 1274 * Return: 0 always 1275 * 1276 * This function starts/stops SIE engine of IP based on is_on. 1277 */ 1278 static int xudc_pullup(struct usb_gadget *gadget, int is_on) 1279 { 1280 struct xusb_udc *udc = to_udc(gadget); 1281 unsigned long flags; 1282 u32 crtlreg; 1283 1284 spin_lock_irqsave(&udc->lock, flags); 1285 1286 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1287 if (is_on) 1288 crtlreg |= XUSB_CONTROL_USB_READY_MASK; 1289 else 1290 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK; 1291 1292 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1293 1294 spin_unlock_irqrestore(&udc->lock, flags); 1295 1296 return 0; 1297 } 1298 1299 /** 1300 * xudc_eps_init - initialize endpoints. 1301 * @udc: pointer to the usb device controller structure. 1302 */ 1303 static void xudc_eps_init(struct xusb_udc *udc) 1304 { 1305 u32 ep_number; 1306 1307 INIT_LIST_HEAD(&udc->gadget.ep_list); 1308 1309 for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) { 1310 struct xusb_ep *ep = &udc->ep[ep_number]; 1311 1312 if (ep_number) { 1313 list_add_tail(&ep->ep_usb.ep_list, 1314 &udc->gadget.ep_list); 1315 usb_ep_set_maxpacket_limit(&ep->ep_usb, 1316 (unsigned short) ~0); 1317 snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number); 1318 ep->ep_usb.name = ep->name; 1319 ep->ep_usb.ops = &xusb_ep_ops; 1320 1321 ep->ep_usb.caps.type_iso = true; 1322 ep->ep_usb.caps.type_bulk = true; 1323 ep->ep_usb.caps.type_int = true; 1324 } else { 1325 ep->ep_usb.name = ep0name; 1326 usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET); 1327 ep->ep_usb.ops = &xusb_ep0_ops; 1328 1329 ep->ep_usb.caps.type_control = true; 1330 } 1331 1332 ep->ep_usb.caps.dir_in = true; 1333 ep->ep_usb.caps.dir_out = true; 1334 1335 ep->udc = udc; 1336 ep->epnumber = ep_number; 1337 ep->desc = NULL; 1338 /* 1339 * The configuration register address offset between 1340 * each endpoint is 0x10. 1341 */ 1342 ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10); 1343 ep->is_in = 0; 1344 ep->is_iso = 0; 1345 ep->maxpacket = 0; 1346 xudc_epconfig(ep, udc); 1347 1348 /* Initialize one queue per endpoint */ 1349 INIT_LIST_HEAD(&ep->queue); 1350 } 1351 } 1352 1353 /** 1354 * xudc_stop_activity - Stops any further activity on the device. 1355 * @udc: pointer to the usb device controller structure. 1356 */ 1357 static void xudc_stop_activity(struct xusb_udc *udc) 1358 { 1359 int i; 1360 struct xusb_ep *ep; 1361 1362 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1363 ep = &udc->ep[i]; 1364 xudc_nuke(ep, -ESHUTDOWN); 1365 } 1366 } 1367 1368 /** 1369 * xudc_start - Starts the device. 1370 * @gadget: pointer to the usb gadget structure 1371 * @driver: pointer to gadget driver structure 1372 * 1373 * Return: zero on success and error on failure 1374 */ 1375 static int xudc_start(struct usb_gadget *gadget, 1376 struct usb_gadget_driver *driver) 1377 { 1378 struct xusb_udc *udc = to_udc(gadget); 1379 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1380 const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc; 1381 unsigned long flags; 1382 int ret = 0; 1383 1384 spin_lock_irqsave(&udc->lock, flags); 1385 1386 if (udc->driver) { 1387 dev_err(udc->dev, "%s is already bound to %s\n", 1388 udc->gadget.name, udc->driver->driver.name); 1389 ret = -EBUSY; 1390 goto err; 1391 } 1392 1393 /* hook up the driver */ 1394 udc->driver = driver; 1395 udc->gadget.speed = driver->max_speed; 1396 1397 /* Enable the control endpoint. */ 1398 ret = __xudc_ep_enable(ep0, desc); 1399 1400 /* Set device address and remote wakeup to 0 */ 1401 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1402 udc->remote_wkp = 0; 1403 err: 1404 spin_unlock_irqrestore(&udc->lock, flags); 1405 return ret; 1406 } 1407 1408 /** 1409 * xudc_stop - stops the device. 1410 * @gadget: pointer to the usb gadget structure 1411 * @driver: pointer to usb gadget driver structure 1412 * 1413 * Return: zero always 1414 */ 1415 static int xudc_stop(struct usb_gadget *gadget) 1416 { 1417 struct xusb_udc *udc = to_udc(gadget); 1418 unsigned long flags; 1419 1420 spin_lock_irqsave(&udc->lock, flags); 1421 1422 udc->gadget.speed = USB_SPEED_UNKNOWN; 1423 udc->driver = NULL; 1424 1425 /* Set device address and remote wakeup to 0 */ 1426 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1427 udc->remote_wkp = 0; 1428 1429 xudc_stop_activity(udc); 1430 1431 spin_unlock_irqrestore(&udc->lock, flags); 1432 1433 return 0; 1434 } 1435 1436 static const struct usb_gadget_ops xusb_udc_ops = { 1437 .get_frame = xudc_get_frame, 1438 .wakeup = xudc_wakeup, 1439 .pullup = xudc_pullup, 1440 .udc_start = xudc_start, 1441 .udc_stop = xudc_stop, 1442 }; 1443 1444 /** 1445 * xudc_clear_stall_all_ep - clears stall of every endpoint. 1446 * @udc: pointer to the udc structure. 1447 */ 1448 static void xudc_clear_stall_all_ep(struct xusb_udc *udc) 1449 { 1450 struct xusb_ep *ep; 1451 u32 epcfgreg; 1452 int i; 1453 1454 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1455 ep = &udc->ep[i]; 1456 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1457 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1458 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1459 if (ep->epnumber) { 1460 /* Reset the toggle bit.*/ 1461 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1462 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 1463 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1464 } 1465 } 1466 } 1467 1468 /** 1469 * xudc_startup_handler - The usb device controller interrupt handler. 1470 * @udc: pointer to the udc structure. 1471 * @intrstatus: The mask value containing the interrupt sources. 1472 * 1473 * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts. 1474 */ 1475 static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus) 1476 { 1477 u32 intrreg; 1478 1479 if (intrstatus & XUSB_STATUS_RESET_MASK) { 1480 1481 dev_dbg(udc->dev, "Reset\n"); 1482 1483 if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK) 1484 udc->gadget.speed = USB_SPEED_HIGH; 1485 else 1486 udc->gadget.speed = USB_SPEED_FULL; 1487 1488 xudc_stop_activity(udc); 1489 xudc_clear_stall_all_ep(udc); 1490 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 1491 1492 /* Set device address and remote wakeup to 0 */ 1493 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1494 udc->remote_wkp = 0; 1495 1496 /* Enable the suspend, resume and disconnect */ 1497 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1498 intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK | 1499 XUSB_STATUS_DISCONNECT_MASK; 1500 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1501 } 1502 if (intrstatus & XUSB_STATUS_SUSPEND_MASK) { 1503 1504 dev_dbg(udc->dev, "Suspend\n"); 1505 1506 /* Enable the reset, resume and disconnect */ 1507 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1508 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1509 XUSB_STATUS_DISCONNECT_MASK; 1510 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1511 1512 udc->usb_state = USB_STATE_SUSPENDED; 1513 1514 if (udc->driver->suspend) { 1515 spin_unlock(&udc->lock); 1516 udc->driver->suspend(&udc->gadget); 1517 spin_lock(&udc->lock); 1518 } 1519 } 1520 if (intrstatus & XUSB_STATUS_RESUME_MASK) { 1521 bool condition = (udc->usb_state != USB_STATE_SUSPENDED); 1522 1523 dev_WARN_ONCE(udc->dev, condition, 1524 "Resume IRQ while not suspended\n"); 1525 1526 dev_dbg(udc->dev, "Resume\n"); 1527 1528 /* Enable the reset, suspend and disconnect */ 1529 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1530 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK | 1531 XUSB_STATUS_DISCONNECT_MASK; 1532 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1533 1534 udc->usb_state = 0; 1535 1536 if (udc->driver->resume) { 1537 spin_unlock(&udc->lock); 1538 udc->driver->resume(&udc->gadget); 1539 spin_lock(&udc->lock); 1540 } 1541 } 1542 if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) { 1543 1544 dev_dbg(udc->dev, "Disconnect\n"); 1545 1546 /* Enable the reset, resume and suspend */ 1547 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1548 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1549 XUSB_STATUS_SUSPEND_MASK; 1550 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1551 1552 if (udc->driver && udc->driver->disconnect) { 1553 spin_unlock(&udc->lock); 1554 udc->driver->disconnect(&udc->gadget); 1555 spin_lock(&udc->lock); 1556 } 1557 } 1558 } 1559 1560 /** 1561 * xudc_ep0_stall - Stall endpoint zero. 1562 * @udc: pointer to the udc structure. 1563 * 1564 * This function stalls endpoint zero. 1565 */ 1566 static void xudc_ep0_stall(struct xusb_udc *udc) 1567 { 1568 u32 epcfgreg; 1569 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1570 1571 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1572 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1573 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1574 } 1575 1576 /** 1577 * xudc_setaddress - executes SET_ADDRESS command 1578 * @udc: pointer to the udc structure. 1579 * 1580 * This function executes USB SET_ADDRESS command 1581 */ 1582 static void xudc_setaddress(struct xusb_udc *udc) 1583 { 1584 struct xusb_ep *ep0 = &udc->ep[0]; 1585 struct xusb_req *req = udc->req; 1586 int ret; 1587 1588 req->usb_req.length = 0; 1589 ret = __xudc_ep0_queue(ep0, req); 1590 if (ret == 0) 1591 return; 1592 1593 dev_err(udc->dev, "Can't respond to SET ADDRESS request\n"); 1594 xudc_ep0_stall(udc); 1595 } 1596 1597 /** 1598 * xudc_getstatus - executes GET_STATUS command 1599 * @udc: pointer to the udc structure. 1600 * 1601 * This function executes USB GET_STATUS command 1602 */ 1603 static void xudc_getstatus(struct xusb_udc *udc) 1604 { 1605 struct xusb_ep *ep0 = &udc->ep[0]; 1606 struct xusb_req *req = udc->req; 1607 struct xusb_ep *target_ep; 1608 u16 status = 0; 1609 u32 epcfgreg; 1610 int epnum; 1611 u32 halt; 1612 int ret; 1613 1614 switch (udc->setup.bRequestType & USB_RECIP_MASK) { 1615 case USB_RECIP_DEVICE: 1616 /* Get device status */ 1617 status = 1 << USB_DEVICE_SELF_POWERED; 1618 if (udc->remote_wkp) 1619 status |= (1 << USB_DEVICE_REMOTE_WAKEUP); 1620 break; 1621 case USB_RECIP_INTERFACE: 1622 break; 1623 case USB_RECIP_ENDPOINT: 1624 epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1625 target_ep = &udc->ep[epnum]; 1626 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1627 halt = epcfgreg & XUSB_EP_CFG_STALL_MASK; 1628 if (udc->setup.wIndex & USB_DIR_IN) { 1629 if (!target_ep->is_in) 1630 goto stall; 1631 } else { 1632 if (target_ep->is_in) 1633 goto stall; 1634 } 1635 if (halt) 1636 status = 1 << USB_ENDPOINT_HALT; 1637 break; 1638 default: 1639 goto stall; 1640 } 1641 1642 req->usb_req.length = 2; 1643 *(u16 *)req->usb_req.buf = cpu_to_le16(status); 1644 ret = __xudc_ep0_queue(ep0, req); 1645 if (ret == 0) 1646 return; 1647 stall: 1648 dev_err(udc->dev, "Can't respond to getstatus request\n"); 1649 xudc_ep0_stall(udc); 1650 } 1651 1652 /** 1653 * xudc_set_clear_feature - Executes the set feature and clear feature commands. 1654 * @udc: pointer to the usb device controller structure. 1655 * 1656 * Processes the SET_FEATURE and CLEAR_FEATURE commands. 1657 */ 1658 static void xudc_set_clear_feature(struct xusb_udc *udc) 1659 { 1660 struct xusb_ep *ep0 = &udc->ep[0]; 1661 struct xusb_req *req = udc->req; 1662 struct xusb_ep *target_ep; 1663 u8 endpoint; 1664 u8 outinbit; 1665 u32 epcfgreg; 1666 int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0); 1667 int ret; 1668 1669 switch (udc->setup.bRequestType) { 1670 case USB_RECIP_DEVICE: 1671 switch (udc->setup.wValue) { 1672 case USB_DEVICE_TEST_MODE: 1673 /* 1674 * The Test Mode will be executed 1675 * after the status phase. 1676 */ 1677 break; 1678 case USB_DEVICE_REMOTE_WAKEUP: 1679 if (flag) 1680 udc->remote_wkp = 1; 1681 else 1682 udc->remote_wkp = 0; 1683 break; 1684 default: 1685 xudc_ep0_stall(udc); 1686 break; 1687 } 1688 break; 1689 case USB_RECIP_ENDPOINT: 1690 if (!udc->setup.wValue) { 1691 endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1692 target_ep = &udc->ep[endpoint]; 1693 outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK; 1694 outinbit = outinbit >> 7; 1695 1696 /* Make sure direction matches.*/ 1697 if (outinbit != target_ep->is_in) { 1698 xudc_ep0_stall(udc); 1699 return; 1700 } 1701 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1702 if (!endpoint) { 1703 /* Clear the stall.*/ 1704 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1705 udc->write_fn(udc->addr, 1706 target_ep->offset, epcfgreg); 1707 } else { 1708 if (flag) { 1709 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1710 udc->write_fn(udc->addr, 1711 target_ep->offset, 1712 epcfgreg); 1713 } else { 1714 /* Unstall the endpoint.*/ 1715 epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK | 1716 XUSB_EP_CFG_DATA_TOGGLE_MASK); 1717 udc->write_fn(udc->addr, 1718 target_ep->offset, 1719 epcfgreg); 1720 } 1721 } 1722 } 1723 break; 1724 default: 1725 xudc_ep0_stall(udc); 1726 return; 1727 } 1728 1729 req->usb_req.length = 0; 1730 ret = __xudc_ep0_queue(ep0, req); 1731 if (ret == 0) 1732 return; 1733 1734 dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n"); 1735 xudc_ep0_stall(udc); 1736 } 1737 1738 /** 1739 * xudc_handle_setup - Processes the setup packet. 1740 * @udc: pointer to the usb device controller structure. 1741 * 1742 * Process setup packet and delegate to gadget layer. 1743 */ 1744 static void xudc_handle_setup(struct xusb_udc *udc) 1745 { 1746 struct xusb_ep *ep0 = &udc->ep[0]; 1747 struct usb_ctrlrequest setup; 1748 u32 *ep0rambase; 1749 1750 /* Load up the chapter 9 command buffer.*/ 1751 ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); 1752 memcpy(&setup, ep0rambase, 8); 1753 1754 udc->setup = setup; 1755 udc->setup.wValue = cpu_to_le16(setup.wValue); 1756 udc->setup.wIndex = cpu_to_le16(setup.wIndex); 1757 udc->setup.wLength = cpu_to_le16(setup.wLength); 1758 1759 /* Clear previous requests */ 1760 xudc_nuke(ep0, -ECONNRESET); 1761 1762 if (udc->setup.bRequestType & USB_DIR_IN) { 1763 /* Execute the get command.*/ 1764 udc->setupseqrx = STATUS_PHASE; 1765 udc->setupseqtx = DATA_PHASE; 1766 } else { 1767 /* Execute the put command.*/ 1768 udc->setupseqrx = DATA_PHASE; 1769 udc->setupseqtx = STATUS_PHASE; 1770 } 1771 1772 switch (udc->setup.bRequest) { 1773 case USB_REQ_GET_STATUS: 1774 /* Data+Status phase form udc */ 1775 if ((udc->setup.bRequestType & 1776 (USB_DIR_IN | USB_TYPE_MASK)) != 1777 (USB_DIR_IN | USB_TYPE_STANDARD)) 1778 break; 1779 xudc_getstatus(udc); 1780 return; 1781 case USB_REQ_SET_ADDRESS: 1782 /* Status phase from udc */ 1783 if (udc->setup.bRequestType != (USB_DIR_OUT | 1784 USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1785 break; 1786 xudc_setaddress(udc); 1787 return; 1788 case USB_REQ_CLEAR_FEATURE: 1789 case USB_REQ_SET_FEATURE: 1790 /* Requests with no data phase, status phase from udc */ 1791 if ((udc->setup.bRequestType & USB_TYPE_MASK) 1792 != USB_TYPE_STANDARD) 1793 break; 1794 xudc_set_clear_feature(udc); 1795 return; 1796 default: 1797 break; 1798 } 1799 1800 spin_unlock(&udc->lock); 1801 if (udc->driver->setup(&udc->gadget, &setup) < 0) 1802 xudc_ep0_stall(udc); 1803 spin_lock(&udc->lock); 1804 } 1805 1806 /** 1807 * xudc_ep0_out - Processes the endpoint 0 OUT token. 1808 * @udc: pointer to the usb device controller structure. 1809 */ 1810 static void xudc_ep0_out(struct xusb_udc *udc) 1811 { 1812 struct xusb_ep *ep0 = &udc->ep[0]; 1813 struct xusb_req *req; 1814 u8 *ep0rambase; 1815 unsigned int bytes_to_rx; 1816 void *buffer; 1817 1818 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1819 1820 switch (udc->setupseqrx) { 1821 case STATUS_PHASE: 1822 /* 1823 * This resets both state machines for the next 1824 * Setup packet. 1825 */ 1826 udc->setupseqrx = SETUP_PHASE; 1827 udc->setupseqtx = SETUP_PHASE; 1828 req->usb_req.actual = req->usb_req.length; 1829 xudc_done(ep0, req, 0); 1830 break; 1831 case DATA_PHASE: 1832 bytes_to_rx = udc->read_fn(udc->addr + 1833 XUSB_EP_BUF0COUNT_OFFSET); 1834 /* Copy the data to be received from the DPRAM. */ 1835 ep0rambase = (u8 __force *) (udc->addr + 1836 (ep0->rambase << 2)); 1837 buffer = req->usb_req.buf + req->usb_req.actual; 1838 req->usb_req.actual = req->usb_req.actual + bytes_to_rx; 1839 memcpy(buffer, ep0rambase, bytes_to_rx); 1840 1841 if (req->usb_req.length == req->usb_req.actual) { 1842 /* Data transfer completed get ready for Status stage */ 1843 xudc_wrstatus(udc); 1844 } else { 1845 /* Enable EP0 buffer to receive data */ 1846 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1847 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1848 } 1849 break; 1850 default: 1851 break; 1852 } 1853 } 1854 1855 /** 1856 * xudc_ep0_in - Processes the endpoint 0 IN token. 1857 * @udc: pointer to the usb device controller structure. 1858 */ 1859 static void xudc_ep0_in(struct xusb_udc *udc) 1860 { 1861 struct xusb_ep *ep0 = &udc->ep[0]; 1862 struct xusb_req *req; 1863 unsigned int bytes_to_tx; 1864 void *buffer; 1865 u32 epcfgreg; 1866 u16 count = 0; 1867 u16 length; 1868 u8 *ep0rambase; 1869 u8 test_mode = udc->setup.wIndex >> 8; 1870 1871 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1872 bytes_to_tx = req->usb_req.length - req->usb_req.actual; 1873 1874 switch (udc->setupseqtx) { 1875 case STATUS_PHASE: 1876 switch (udc->setup.bRequest) { 1877 case USB_REQ_SET_ADDRESS: 1878 /* Set the address of the device.*/ 1879 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 1880 udc->setup.wValue); 1881 break; 1882 case USB_REQ_SET_FEATURE: 1883 if (udc->setup.bRequestType == 1884 USB_RECIP_DEVICE) { 1885 if (udc->setup.wValue == 1886 USB_DEVICE_TEST_MODE) 1887 udc->write_fn(udc->addr, 1888 XUSB_TESTMODE_OFFSET, 1889 test_mode); 1890 } 1891 break; 1892 } 1893 req->usb_req.actual = req->usb_req.length; 1894 xudc_done(ep0, req, 0); 1895 break; 1896 case DATA_PHASE: 1897 if (!bytes_to_tx) { 1898 /* 1899 * We're done with data transfer, next 1900 * will be zero length OUT with data toggle of 1901 * 1. Setup data_toggle. 1902 */ 1903 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1904 epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK; 1905 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1906 udc->setupseqtx = STATUS_PHASE; 1907 } else { 1908 length = count = min_t(u32, bytes_to_tx, 1909 EP0_MAX_PACKET); 1910 /* Copy the data to be transmitted into the DPRAM. */ 1911 ep0rambase = (u8 __force *) (udc->addr + 1912 (ep0->rambase << 2)); 1913 buffer = req->usb_req.buf + req->usb_req.actual; 1914 req->usb_req.actual = req->usb_req.actual + length; 1915 memcpy(ep0rambase, buffer, length); 1916 } 1917 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); 1918 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1919 break; 1920 default: 1921 break; 1922 } 1923 } 1924 1925 /** 1926 * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler. 1927 * @udc: pointer to the udc structure. 1928 * @intrstatus: It's the mask value for the interrupt sources on endpoint 0. 1929 * 1930 * Processes the commands received during enumeration phase. 1931 */ 1932 static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus) 1933 { 1934 1935 if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) { 1936 xudc_handle_setup(udc); 1937 } else { 1938 if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK) 1939 xudc_ep0_out(udc); 1940 else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK) 1941 xudc_ep0_in(udc); 1942 } 1943 } 1944 1945 /** 1946 * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler. 1947 * @udc: pointer to the udc structure. 1948 * @epnum: End point number for which the interrupt is to be processed 1949 * @intrstatus: mask value for interrupt sources of endpoints other 1950 * than endpoint 0. 1951 * 1952 * Processes the buffer completion interrupts. 1953 */ 1954 static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum, 1955 u32 intrstatus) 1956 { 1957 1958 struct xusb_req *req; 1959 struct xusb_ep *ep; 1960 1961 ep = &udc->ep[epnum]; 1962 /* Process the End point interrupts.*/ 1963 if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum)) 1964 ep->buffer0ready = 0; 1965 if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum)) 1966 ep->buffer1ready = 0; 1967 1968 if (list_empty(&ep->queue)) 1969 return; 1970 1971 req = list_first_entry(&ep->queue, struct xusb_req, queue); 1972 1973 if (ep->is_in) 1974 xudc_write_fifo(ep, req); 1975 else 1976 xudc_read_fifo(ep, req); 1977 } 1978 1979 /** 1980 * xudc_irq - The main interrupt handler. 1981 * @irq: The interrupt number. 1982 * @_udc: pointer to the usb device controller structure. 1983 * 1984 * Return: IRQ_HANDLED after the interrupt is handled. 1985 */ 1986 static irqreturn_t xudc_irq(int irq, void *_udc) 1987 { 1988 struct xusb_udc *udc = _udc; 1989 u32 intrstatus; 1990 u32 ier; 1991 u8 index; 1992 u32 bufintr; 1993 unsigned long flags; 1994 1995 spin_lock_irqsave(&udc->lock, flags); 1996 1997 /* 1998 * Event interrupts are level sensitive hence first disable 1999 * IER, read ISR and figure out active interrupts. 2000 */ 2001 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2002 ier &= ~XUSB_STATUS_INTR_EVENT_MASK; 2003 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2004 2005 /* Read the Interrupt Status Register.*/ 2006 intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET); 2007 2008 /* Call the handler for the event interrupt.*/ 2009 if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) { 2010 /* 2011 * Check if there is any action to be done for : 2012 * - USB Reset received {XUSB_STATUS_RESET_MASK} 2013 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK} 2014 * - USB Resume received {XUSB_STATUS_RESUME_MASK} 2015 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK} 2016 */ 2017 xudc_startup_handler(udc, intrstatus); 2018 } 2019 2020 /* Check the buffer completion interrupts */ 2021 if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) { 2022 /* Enable Reset, Suspend, Resume and Disconnect */ 2023 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2024 ier |= XUSB_STATUS_INTR_EVENT_MASK; 2025 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2026 2027 if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK) 2028 xudc_ctrl_ep_handler(udc, intrstatus); 2029 2030 for (index = 1; index < 8; index++) { 2031 bufintr = ((intrstatus & 2032 (XUSB_STATUS_EP1_BUFF1_COMP_MASK << 2033 (index - 1))) || (intrstatus & 2034 (XUSB_STATUS_EP1_BUFF2_COMP_MASK << 2035 (index - 1)))); 2036 if (bufintr) { 2037 xudc_nonctrl_ep_handler(udc, index, 2038 intrstatus); 2039 } 2040 } 2041 } 2042 2043 spin_unlock_irqrestore(&udc->lock, flags); 2044 return IRQ_HANDLED; 2045 } 2046 2047 /** 2048 * xudc_probe - The device probe function for driver initialization. 2049 * @pdev: pointer to the platform device structure. 2050 * 2051 * Return: 0 for success and error value on failure 2052 */ 2053 static int xudc_probe(struct platform_device *pdev) 2054 { 2055 struct device_node *np = pdev->dev.of_node; 2056 struct resource *res; 2057 struct xusb_udc *udc; 2058 struct xusb_ep *ep0; 2059 int irq; 2060 int ret; 2061 u32 ier; 2062 u8 *buff; 2063 2064 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2065 if (!udc) 2066 return -ENOMEM; 2067 2068 /* Create a dummy request for GET_STATUS, SET_ADDRESS */ 2069 udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req), 2070 GFP_KERNEL); 2071 if (!udc->req) 2072 return -ENOMEM; 2073 2074 buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL); 2075 if (!buff) 2076 return -ENOMEM; 2077 2078 udc->req->usb_req.buf = buff; 2079 2080 /* Map the registers */ 2081 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2082 udc->addr = devm_ioremap_resource(&pdev->dev, res); 2083 if (IS_ERR(udc->addr)) 2084 return PTR_ERR(udc->addr); 2085 2086 irq = platform_get_irq(pdev, 0); 2087 if (irq < 0) { 2088 dev_err(&pdev->dev, "unable to get irq\n"); 2089 return irq; 2090 } 2091 ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0, 2092 dev_name(&pdev->dev), udc); 2093 if (ret < 0) { 2094 dev_dbg(&pdev->dev, "unable to request irq %d", irq); 2095 goto fail; 2096 } 2097 2098 udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma"); 2099 2100 /* Setup gadget structure */ 2101 udc->gadget.ops = &xusb_udc_ops; 2102 udc->gadget.max_speed = USB_SPEED_HIGH; 2103 udc->gadget.speed = USB_SPEED_UNKNOWN; 2104 udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb; 2105 udc->gadget.name = driver_name; 2106 2107 spin_lock_init(&udc->lock); 2108 2109 /* Check for IP endianness */ 2110 udc->write_fn = xudc_write32_be; 2111 udc->read_fn = xudc_read32_be; 2112 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, TEST_J); 2113 if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET)) 2114 != TEST_J) { 2115 udc->write_fn = xudc_write32; 2116 udc->read_fn = xudc_read32; 2117 } 2118 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 2119 2120 xudc_eps_init(udc); 2121 2122 ep0 = &udc->ep[0]; 2123 2124 /* Set device address to 0.*/ 2125 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 2126 2127 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2128 if (ret) 2129 goto fail; 2130 2131 udc->dev = &udc->gadget.dev; 2132 2133 /* Enable the interrupts.*/ 2134 ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK | 2135 XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK | 2136 XUSB_STATUS_SETUP_PACKET_MASK | 2137 XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK; 2138 2139 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2140 2141 platform_set_drvdata(pdev, udc); 2142 2143 dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n", 2144 driver_name, (u32)res->start, udc->addr, 2145 udc->dma_enabled ? "with DMA" : "without DMA"); 2146 2147 return 0; 2148 fail: 2149 dev_err(&pdev->dev, "probe failed, %d\n", ret); 2150 return ret; 2151 } 2152 2153 /** 2154 * xudc_remove - Releases the resources allocated during the initialization. 2155 * @pdev: pointer to the platform device structure. 2156 * 2157 * Return: 0 always 2158 */ 2159 static int xudc_remove(struct platform_device *pdev) 2160 { 2161 struct xusb_udc *udc = platform_get_drvdata(pdev); 2162 2163 usb_del_gadget_udc(&udc->gadget); 2164 2165 return 0; 2166 } 2167 2168 /* Match table for of_platform binding */ 2169 static const struct of_device_id usb_of_match[] = { 2170 { .compatible = "xlnx,usb2-device-4.00.a", }, 2171 { /* end of list */ }, 2172 }; 2173 MODULE_DEVICE_TABLE(of, usb_of_match); 2174 2175 static struct platform_driver xudc_driver = { 2176 .driver = { 2177 .name = driver_name, 2178 .of_match_table = usb_of_match, 2179 }, 2180 .probe = xudc_probe, 2181 .remove = xudc_remove, 2182 }; 2183 2184 module_platform_driver(xudc_driver); 2185 2186 MODULE_DESCRIPTION("Xilinx udc driver"); 2187 MODULE_AUTHOR("Xilinx, Inc"); 2188 MODULE_LICENSE("GPL"); 2189