1 /* 2 * linux/drivers/usb/gadget/pxa27x_udc.h 3 * Intel PXA27x on-chip full speed USB device controller 4 * 5 * Inspired by original driver by Frank Becker, David Brownell, and others. 6 * Copyright (C) 2008 Robert Jarzmik 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef __LINUX_USB_GADGET_PXA27X_H 15 #define __LINUX_USB_GADGET_PXA27X_H 16 17 #include <linux/types.h> 18 #include <linux/spinlock.h> 19 #include <linux/io.h> 20 #include <linux/usb/otg.h> 21 22 /* 23 * Register definitions 24 */ 25 /* Offsets */ 26 #define UDCCR 0x0000 /* UDC Control Register */ 27 #define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */ 28 #define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */ 29 #define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */ 30 #define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */ 31 #define UDCFNR 0x0014 /* UDC Frame Number Register */ 32 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */ 33 #define UP2OCR 0x0020 /* USB Port 2 Output Control register */ 34 #define UP3OCR 0x0024 /* USB Port 3 Output Control register */ 35 #define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */ 36 #define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */ 37 #define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */ 38 #define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */ 39 40 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ 41 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation 42 Protocol Port Support */ 43 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol 44 Support */ 45 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol 46 Enable */ 47 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ 48 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ 49 #define UDCCR_ACN_S 11 50 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ 51 #define UDCCR_AIN_S 8 52 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface 53 Setting Number */ 54 #define UDCCR_AAISN_S 5 55 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active 56 Configuration */ 57 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration 58 Error */ 59 #define UDCCR_UDR (1 << 2) /* UDC Resume */ 60 #define UDCCR_UDA (1 << 1) /* UDC Active */ 61 #define UDCCR_UDE (1 << 0) /* UDC Enable */ 62 63 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) 64 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ 65 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ 66 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ 67 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ 68 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ 69 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ 70 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ 71 #define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) 72 73 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) 74 #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ 75 #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ 76 #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ 77 #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ 78 #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ 79 #define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) 80 81 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ 82 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt 83 Rising Edge Interrupt Enable */ 84 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt 85 Falling Edge Interrupt Enable */ 86 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge 87 Interrupt Enable */ 88 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge 89 Interrupt Enable */ 90 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge 91 Interrupt Enable */ 92 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge 93 Interrupt Enable */ 94 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge 95 Interrupt Enable */ 96 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge 97 Interrupt Enable */ 98 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising 99 Edge Interrupt Enable */ 100 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling 101 Edge Interrupt Enable */ 102 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge 103 Interrupt Enable */ 104 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge 105 Interrupt Enable */ 106 107 /* Host Port 2 field bits */ 108 #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ 109 #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ 110 /* Transceiver enablers */ 111 #define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */ 112 #define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */ 113 #define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */ 114 #define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */ 115 #define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */ 116 #define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */ 117 #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ 118 #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ 119 #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ 120 #define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */ 121 #define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */ 122 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ 123 124 #define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */ 125 #define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */ 126 #define UDCCSR0_SA (1 << 7) /* Setup Active */ 127 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ 128 #define UDCCSR0_FST (1 << 5) /* Force Stall */ 129 #define UDCCSR0_SST (1 << 4) /* Sent Stall */ 130 #define UDCCSR0_DME (1 << 3) /* DMA Enable */ 131 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ 132 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ 133 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ 134 135 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ 136 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ 137 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ 138 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ 139 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ 140 #define UDCCSR_FST (1 << 5) /* Force STALL */ 141 #define UDCCSR_SST (1 << 4) /* Sent STALL */ 142 #define UDCCSR_DME (1 << 3) /* DMA Enable */ 143 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ 144 #define UDCCSR_PC (1 << 1) /* Packet Complete */ 145 #define UDCCSR_FS (1 << 0) /* FIFO needs service */ 146 147 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ 148 #define UDCCONR_CN_S 25 149 #define UDCCONR_IN (0x07 << 22) /* Interface Number */ 150 #define UDCCONR_IN_S 22 151 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ 152 #define UDCCONR_AISN_S 19 153 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ 154 #define UDCCONR_EN_S 15 155 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ 156 #define UDCCONR_ET_S 13 157 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ 158 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ 159 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ 160 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ 161 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ 162 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ 163 #define UDCCONR_MPS_S 2 164 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ 165 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ 166 167 #define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE) 168 #define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST) 169 #define UDC_FNR_MASK (0x7ff) 170 #define UDC_BCR_MASK (0x3ff) 171 172 /* 173 * UDCCR = UDC Endpoint Configuration Registers 174 * UDCCSR = UDC Control/Status Register for this EP 175 * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo) 176 * UDCDR = UDC Endpoint Data Register (the fifo) 177 */ 178 #define ofs_UDCCR(ep) (UDCCRn(ep->idx)) 179 #define ofs_UDCCSR(ep) (UDCCSRn(ep->idx)) 180 #define ofs_UDCBCR(ep) (UDCBCRn(ep->idx)) 181 #define ofs_UDCDR(ep) (UDCDRn(ep->idx)) 182 183 /* Register access macros */ 184 #define udc_ep_readl(ep, reg) \ 185 __raw_readl((ep)->dev->regs + ofs_##reg(ep)) 186 #define udc_ep_writel(ep, reg, value) \ 187 __raw_writel((value), ep->dev->regs + ofs_##reg(ep)) 188 #define udc_ep_readb(ep, reg) \ 189 __raw_readb((ep)->dev->regs + ofs_##reg(ep)) 190 #define udc_ep_writeb(ep, reg, value) \ 191 __raw_writeb((value), ep->dev->regs + ofs_##reg(ep)) 192 #define udc_readl(dev, reg) \ 193 __raw_readl((dev)->regs + (reg)) 194 #define udc_writel(udc, reg, value) \ 195 __raw_writel((value), (udc)->regs + (reg)) 196 197 #define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME) 198 #define UDCCISR0_EP_MASK ~0 199 #define UDCCISR1_EP_MASK 0xffff 200 #define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE) 201 202 #define EPIDX(ep) (ep->idx) 203 #define EPADDR(ep) (ep->addr) 204 #define EPXFERTYPE(ep) (ep->type) 205 #define EPNAME(ep) (ep->name) 206 #define is_ep0(ep) (!ep->idx) 207 #define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC) 208 209 /* 210 * Endpoint definitions 211 * 212 * Once enabled, pxa endpoint configuration is freezed, and cannot change 213 * unless a reset happens or the udc is disabled. 214 * Therefore, we must define all pxa potential endpoint definitions needed for 215 * all gadget and set them up before the udc is enabled. 216 * 217 * As the architecture chosen is fully static, meaning the pxa endpoint 218 * configurations are set up once and for all, we must provide a way to match 219 * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget 220 * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt) 221 * criteria, while the pxa architecture requires that. 222 * 223 * The solution is to define several pxa endpoints matching one usb_ep. Ex: 224 * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when 225 * the udc talks on (config=3, interface=0, alt=0) 226 * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when 227 * the udc talks on (config=3, interface=0, alt=1) 228 * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when 229 * the udc talks on (config=2, interface=0, alt=0) 230 * 231 * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...) 232 */ 233 234 /* 235 * Endpoint definition helpers 236 */ 237 #define USB_EP_DEF(addr, bname, dir, type, maxpkt, ctype, cdir) \ 238 { .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, \ 239 .caps = USB_EP_CAPS(ctype, cdir), }, \ 240 .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \ 241 .bmAttributes = USB_ENDPOINT_XFER_ ## type, \ 242 .wMaxPacketSize = maxpkt, }, \ 243 .dev = &memory \ 244 } 245 #define USB_EP_BULK(addr, bname, dir, cdir) \ 246 USB_EP_DEF(addr, bname, dir, BULK, BULK_FIFO_SIZE, \ 247 USB_EP_CAPS_TYPE_BULK, cdir) 248 #define USB_EP_ISO(addr, bname, dir, cdir) \ 249 USB_EP_DEF(addr, bname, dir, ISOC, ISO_FIFO_SIZE, \ 250 USB_EP_CAPS_TYPE_ISO, cdir) 251 #define USB_EP_INT(addr, bname, dir, cdir) \ 252 USB_EP_DEF(addr, bname, dir, INT, INT_FIFO_SIZE, \ 253 USB_EP_CAPS_TYPE_INT, cdir) 254 #define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1, \ 255 USB_EP_CAPS_DIR_IN) 256 #define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0, \ 257 USB_EP_CAPS_DIR_OUT) 258 #define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1, \ 259 USB_EP_CAPS_DIR_IN) 260 #define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0, \ 261 USB_EP_CAPS_DIR_OUT) 262 #define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1, \ 263 USB_EP_CAPS_DIR_IN) 264 #define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, CONTROL, EP0_FIFO_SIZE, \ 265 USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL) 266 267 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ 268 { \ 269 .dev = &memory, \ 270 .name = "ep" #_idx, \ 271 .idx = _idx, .enabled = 0, \ 272 .dir_in = dir, .addr = _addr, \ 273 .config = _config, .interface = iface, .alternate = altset, \ 274 .type = _type, .fifo_size = maxpkt, \ 275 } 276 #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ 277 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \ 278 config, iface, alt) 279 #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ 280 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \ 281 config, iface, alt) 282 #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ 283 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \ 284 config, iface, alt) 285 #define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a) 286 #define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a) 287 #define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a) 288 #define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a) 289 #define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a) 290 #define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0) 291 292 struct pxa27x_udc; 293 294 struct stats { 295 unsigned long in_ops; 296 unsigned long out_ops; 297 unsigned long in_bytes; 298 unsigned long out_bytes; 299 unsigned long irqs; 300 }; 301 302 /** 303 * struct udc_usb_ep - container of each usb_ep structure 304 * @usb_ep: usb endpoint 305 * @desc: usb descriptor, especially type and address 306 * @dev: udc managing this endpoint 307 * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call) 308 */ 309 struct udc_usb_ep { 310 struct usb_ep usb_ep; 311 struct usb_endpoint_descriptor desc; 312 struct pxa_udc *dev; 313 struct pxa_ep *pxa_ep; 314 }; 315 316 /** 317 * struct pxa_ep - pxa endpoint 318 * @dev: udc device 319 * @queue: requests queue 320 * @lock: lock to pxa_ep data (queues and stats) 321 * @enabled: true when endpoint enabled (not stopped by gadget layer) 322 * @in_handle_ep: number of recursions of handle_ep() function 323 * Prevents deadlocks or infinite recursions of types : 324 * irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep() 325 * or 326 * pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue() 327 * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX) 328 * @name: endpoint name (for trace/debug purpose) 329 * @dir_in: 1 if IN endpoint, 0 if OUT endpoint 330 * @addr: usb endpoint number 331 * @config: configuration in which this endpoint is active 332 * @interface: interface in which this endpoint is active 333 * @alternate: altsetting in which this endpoitn is active 334 * @fifo_size: max packet size in the endpoint fifo 335 * @type: endpoint type (bulk, iso, int, ...) 336 * @udccsr_value: save register of UDCCSR0 for suspend/resume 337 * @udccr_value: save register of UDCCR for suspend/resume 338 * @stats: endpoint statistics 339 * 340 * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned 341 * (cares about config/interface/altsetting, thus placing needless limits on 342 * device capability) and full of implementation bugs forcing it to be set up 343 * for use more or less like a pxa255. 344 * 345 * As we define the pxa_ep statically, we must guess all needed pxa_ep for all 346 * gadget which may work with this udc driver. 347 */ 348 struct pxa_ep { 349 struct pxa_udc *dev; 350 351 struct list_head queue; 352 spinlock_t lock; /* Protects this structure */ 353 /* (queues, stats) */ 354 unsigned enabled:1; 355 unsigned in_handle_ep:1; 356 357 unsigned idx:5; 358 char *name; 359 360 /* 361 * Specific pxa endpoint data, needed for hardware initialization 362 */ 363 unsigned dir_in:1; 364 unsigned addr:4; 365 unsigned config:2; 366 unsigned interface:3; 367 unsigned alternate:3; 368 unsigned fifo_size; 369 unsigned type; 370 371 #ifdef CONFIG_PM 372 u32 udccsr_value; 373 u32 udccr_value; 374 #endif 375 struct stats stats; 376 }; 377 378 /** 379 * struct pxa27x_request - container of each usb_request structure 380 * @req: usb request 381 * @udc_usb_ep: usb endpoint the request was submitted on 382 * @in_use: sanity check if request already queued on an pxa_ep 383 * @queue: linked list of requests, linked on pxa_ep->queue 384 */ 385 struct pxa27x_request { 386 struct usb_request req; 387 struct udc_usb_ep *udc_usb_ep; 388 unsigned in_use:1; 389 struct list_head queue; 390 }; 391 392 enum ep0_state { 393 WAIT_FOR_SETUP, 394 SETUP_STAGE, 395 IN_DATA_STAGE, 396 OUT_DATA_STAGE, 397 IN_STATUS_STAGE, 398 OUT_STATUS_STAGE, 399 STALL, 400 WAIT_ACK_SET_CONF_INTERF 401 }; 402 403 static char *ep0_state_name[] = { 404 "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE", 405 "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL", 406 "WAIT_ACK_SET_CONF_INTERF" 407 }; 408 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state] 409 410 #define EP0_FIFO_SIZE 16U 411 #define BULK_FIFO_SIZE 64U 412 #define ISO_FIFO_SIZE 256U 413 #define INT_FIFO_SIZE 16U 414 415 struct udc_stats { 416 unsigned long irqs_reset; 417 unsigned long irqs_suspend; 418 unsigned long irqs_resume; 419 unsigned long irqs_reconfig; 420 }; 421 422 #define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */ 423 #define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */ 424 425 /** 426 * struct pxa_udc - udc structure 427 * @regs: mapped IO space 428 * @irq: udc irq 429 * @clk: udc clock 430 * @usb_gadget: udc gadget structure 431 * @driver: bound gadget (zero, g_ether, g_mass_storage, ...) 432 * @dev: device 433 * @udc_command: machine specific function to activate D+ pullup 434 * @gpiod: gpio descriptor of gpio for D+ pullup (or NULL if none) 435 * @transceiver: external transceiver to handle vbus sense and D+ pullup 436 * @ep0state: control endpoint state machine state 437 * @stats: statistics on udc usage 438 * @udc_usb_ep: array of usb endpoints offered by the gadget 439 * @pxa_ep: array of pxa available endpoints 440 * @enabled: UDC was enabled by a previous udc_enable() 441 * @pullup_on: if pullup resistor connected to D+ pin 442 * @pullup_resume: if pullup resistor should be connected to D+ pin on resume 443 * @config: UDC active configuration 444 * @last_interface: UDC interface of the last SET_INTERFACE host request 445 * @last_alternate: UDC altsetting of the last SET_INTERFACE host request 446 * @udccsr0: save of udccsr0 in case of suspend 447 * @debugfs_root: root entry of debug filesystem 448 * @debugfs_state: debugfs entry for "udcstate" 449 * @debugfs_queues: debugfs entry for "queues" 450 * @debugfs_eps: debugfs entry for "epstate" 451 */ 452 struct pxa_udc { 453 void __iomem *regs; 454 int irq; 455 struct clk *clk; 456 457 struct usb_gadget gadget; 458 struct usb_gadget_driver *driver; 459 struct device *dev; 460 void (*udc_command)(int); 461 struct gpio_desc *gpiod; 462 struct usb_phy *transceiver; 463 464 enum ep0_state ep0state; 465 struct udc_stats stats; 466 467 struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS]; 468 struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS]; 469 470 unsigned enabled:1; 471 unsigned pullup_on:1; 472 unsigned pullup_resume:1; 473 unsigned vbus_sensed:1; 474 unsigned config:2; 475 unsigned last_interface:3; 476 unsigned last_alternate:3; 477 478 #ifdef CONFIG_PM 479 unsigned udccsr0; 480 #endif 481 #ifdef CONFIG_USB_GADGET_DEBUG_FS 482 struct dentry *debugfs_root; 483 struct dentry *debugfs_state; 484 struct dentry *debugfs_queues; 485 struct dentry *debugfs_eps; 486 #endif 487 }; 488 #define to_pxa(g) (container_of((g), struct pxa_udc, gadget)) 489 490 static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) 491 { 492 return container_of(gadget, struct pxa_udc, gadget); 493 } 494 495 /* 496 * Debugging/message support 497 */ 498 #define ep_dbg(ep, fmt, arg...) \ 499 dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) 500 #define ep_vdbg(ep, fmt, arg...) \ 501 dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) 502 #define ep_err(ep, fmt, arg...) \ 503 dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) 504 #define ep_info(ep, fmt, arg...) \ 505 dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) 506 #define ep_warn(ep, fmt, arg...) \ 507 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) 508 509 #endif /* __LINUX_USB_GADGET_PXA27X_H */ 510