1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * omap_udc.c -- for OMAP full speed udc; most chips support OTG. 4 * 5 * Copyright (C) 2004 Texas Instruments, Inc. 6 * Copyright (C) 2004-2005 David Brownell 7 * 8 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com> 9 */ 10 11 #undef DEBUG 12 #undef VERBOSE 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/ioport.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/string_choices.h> 22 #include <linux/timer.h> 23 #include <linux/list.h> 24 #include <linux/interrupt.h> 25 #include <linux/proc_fs.h> 26 #include <linux/mm.h> 27 #include <linux/moduleparam.h> 28 #include <linux/platform_device.h> 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/otg.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/prefetch.h> 36 #include <linux/io.h> 37 38 #include <asm/byteorder.h> 39 #include <asm/irq.h> 40 #include <linux/unaligned.h> 41 #include <asm/mach-types.h> 42 43 #include <linux/omap-dma.h> 44 #include <linux/platform_data/usb-omap1.h> 45 46 #include <linux/soc/ti/omap1-usb.h> 47 #include <linux/soc/ti/omap1-soc.h> 48 #include <linux/soc/ti/omap1-io.h> 49 50 #include "omap_udc.h" 51 52 #undef USB_TRACE 53 54 /* bulk DMA seems to be behaving for both IN and OUT */ 55 #define USE_DMA 56 57 /* ISO too */ 58 #define USE_ISO 59 60 #define DRIVER_VERSION "4 October 2004" 61 62 #define OMAP_DMA_USB_W2FC_TX0 29 63 #define OMAP_DMA_USB_W2FC_RX0 26 64 65 /* 66 * The OMAP UDC needs _very_ early endpoint setup: before enabling the 67 * D+ pullup to allow enumeration. That's too early for the gadget 68 * framework to use from usb_endpoint_enable(), which happens after 69 * enumeration as part of activating an interface. (But if we add an 70 * optional new "UDC not yet running" state to the gadget driver model, 71 * even just during driver binding, the endpoint autoconfig logic is the 72 * natural spot to manufacture new endpoints.) 73 * 74 * So instead of using endpoint enable calls to control the hardware setup, 75 * this driver defines a "fifo mode" parameter. It's used during driver 76 * initialization to choose among a set of pre-defined endpoint configs. 77 * See omap_udc_setup() for available modes, or to add others. That code 78 * lives in an init section, so use this driver as a module if you need 79 * to change the fifo mode after the kernel boots. 80 * 81 * Gadget drivers normally ignore endpoints they don't care about, and 82 * won't include them in configuration descriptors. That means only 83 * misbehaving hosts would even notice they exist. 84 */ 85 #ifdef USE_ISO 86 static unsigned fifo_mode = 3; 87 #else 88 static unsigned fifo_mode; 89 #endif 90 91 /* "modprobe omap_udc fifo_mode=42", or else as a kernel 92 * boot parameter "omap_udc:fifo_mode=42" 93 */ 94 module_param(fifo_mode, uint, 0); 95 MODULE_PARM_DESC(fifo_mode, "endpoint configuration"); 96 97 #ifdef USE_DMA 98 static bool use_dma = 1; 99 100 /* "modprobe omap_udc use_dma=y", or else as a kernel 101 * boot parameter "omap_udc:use_dma=y" 102 */ 103 module_param(use_dma, bool, 0); 104 MODULE_PARM_DESC(use_dma, "enable/disable DMA"); 105 #else /* !USE_DMA */ 106 107 /* save a bit of code */ 108 #define use_dma 0 109 #endif /* !USE_DMA */ 110 111 112 static const char driver_name[] = "omap_udc"; 113 114 /*-------------------------------------------------------------------------*/ 115 116 /* there's a notion of "current endpoint" for modifying endpoint 117 * state, and PIO access to its FIFO. 118 */ 119 120 static void use_ep(struct omap_ep *ep, u16 select) 121 { 122 u16 num = ep->bEndpointAddress & 0x0f; 123 124 if (ep->bEndpointAddress & USB_DIR_IN) 125 num |= UDC_EP_DIR; 126 omap_writew(num | select, UDC_EP_NUM); 127 /* when select, MUST deselect later !! */ 128 } 129 130 static inline void deselect_ep(void) 131 { 132 u16 w; 133 134 w = omap_readw(UDC_EP_NUM); 135 w &= ~UDC_EP_SEL; 136 omap_writew(w, UDC_EP_NUM); 137 /* 6 wait states before TX will happen */ 138 } 139 140 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred); 141 142 /*-------------------------------------------------------------------------*/ 143 144 static int omap_ep_enable(struct usb_ep *_ep, 145 const struct usb_endpoint_descriptor *desc) 146 { 147 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 148 struct omap_udc *udc; 149 unsigned long flags; 150 u16 maxp; 151 152 /* catch various bogus parameters */ 153 if (!_ep || !desc 154 || desc->bDescriptorType != USB_DT_ENDPOINT 155 || ep->bEndpointAddress != desc->bEndpointAddress 156 || ep->maxpacket < usb_endpoint_maxp(desc)) { 157 DBG("%s, bad ep or descriptor\n", __func__); 158 return -EINVAL; 159 } 160 maxp = usb_endpoint_maxp(desc); 161 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 162 && maxp != ep->maxpacket) 163 || usb_endpoint_maxp(desc) > ep->maxpacket 164 || !desc->wMaxPacketSize) { 165 DBG("%s, bad %s maxpacket\n", __func__, _ep->name); 166 return -ERANGE; 167 } 168 169 #ifdef USE_ISO 170 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC 171 && desc->bInterval != 1)) { 172 /* hardware wants period = 1; USB allows 2^(Interval-1) */ 173 DBG("%s, unsupported ISO period %dms\n", _ep->name, 174 1 << (desc->bInterval - 1)); 175 return -EDOM; 176 } 177 #else 178 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 179 DBG("%s, ISO nyet\n", _ep->name); 180 return -EDOM; 181 } 182 #endif 183 184 /* xfer types must match, except that interrupt ~= bulk */ 185 if (ep->bmAttributes != desc->bmAttributes 186 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 187 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 188 DBG("%s, %s type mismatch\n", __func__, _ep->name); 189 return -EINVAL; 190 } 191 192 udc = ep->udc; 193 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 194 DBG("%s, bogus device state\n", __func__); 195 return -ESHUTDOWN; 196 } 197 198 spin_lock_irqsave(&udc->lock, flags); 199 200 ep->ep.desc = desc; 201 ep->irqs = 0; 202 ep->stopped = 0; 203 ep->ep.maxpacket = maxp; 204 205 /* set endpoint to initial state */ 206 ep->dma_channel = 0; 207 ep->has_dma = 0; 208 ep->lch = -1; 209 use_ep(ep, UDC_EP_SEL); 210 omap_writew(udc->clr_halt, UDC_CTRL); 211 ep->ackwait = 0; 212 deselect_ep(); 213 214 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 215 list_add(&ep->iso, &udc->iso); 216 217 /* maybe assign a DMA channel to this endpoint */ 218 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK) 219 /* FIXME ISO can dma, but prefers first channel */ 220 dma_channel_claim(ep, 0); 221 222 /* PIO OUT may RX packets */ 223 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC 224 && !ep->has_dma 225 && !(ep->bEndpointAddress & USB_DIR_IN)) { 226 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 227 ep->ackwait = 1 + ep->double_buf; 228 } 229 230 spin_unlock_irqrestore(&udc->lock, flags); 231 VDBG("%s enabled\n", _ep->name); 232 return 0; 233 } 234 235 static void nuke(struct omap_ep *, int status); 236 237 static int omap_ep_disable(struct usb_ep *_ep) 238 { 239 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 240 unsigned long flags; 241 242 if (!_ep || !ep->ep.desc) { 243 DBG("%s, %s not enabled\n", __func__, 244 _ep ? ep->ep.name : NULL); 245 return -EINVAL; 246 } 247 248 spin_lock_irqsave(&ep->udc->lock, flags); 249 ep->ep.desc = NULL; 250 nuke(ep, -ESHUTDOWN); 251 ep->ep.maxpacket = ep->maxpacket; 252 ep->has_dma = 0; 253 omap_writew(UDC_SET_HALT, UDC_CTRL); 254 list_del_init(&ep->iso); 255 timer_delete(&ep->timer); 256 257 spin_unlock_irqrestore(&ep->udc->lock, flags); 258 259 VDBG("%s disabled\n", _ep->name); 260 return 0; 261 } 262 263 /*-------------------------------------------------------------------------*/ 264 265 static struct usb_request * 266 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 267 { 268 struct omap_req *req; 269 270 req = kzalloc_obj(*req, gfp_flags); 271 if (!req) 272 return NULL; 273 274 INIT_LIST_HEAD(&req->queue); 275 276 return &req->req; 277 } 278 279 static void 280 omap_free_request(struct usb_ep *ep, struct usb_request *_req) 281 { 282 struct omap_req *req = container_of(_req, struct omap_req, req); 283 284 kfree(req); 285 } 286 287 /*-------------------------------------------------------------------------*/ 288 289 static void 290 done(struct omap_ep *ep, struct omap_req *req, int status) 291 { 292 struct omap_udc *udc = ep->udc; 293 unsigned stopped = ep->stopped; 294 295 list_del_init(&req->queue); 296 297 if (req->req.status == -EINPROGRESS) 298 req->req.status = status; 299 else 300 status = req->req.status; 301 302 if (use_dma && ep->has_dma) 303 usb_gadget_unmap_request(&udc->gadget, &req->req, 304 (ep->bEndpointAddress & USB_DIR_IN)); 305 306 #ifndef USB_TRACE 307 if (status && status != -ESHUTDOWN) 308 #endif 309 VDBG("complete %s req %p stat %d len %u/%u\n", 310 ep->ep.name, &req->req, status, 311 req->req.actual, req->req.length); 312 313 /* don't modify queue heads during completion callback */ 314 ep->stopped = 1; 315 spin_unlock(&ep->udc->lock); 316 usb_gadget_giveback_request(&ep->ep, &req->req); 317 spin_lock(&ep->udc->lock); 318 ep->stopped = stopped; 319 } 320 321 /*-------------------------------------------------------------------------*/ 322 323 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) 324 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL) 325 326 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) 327 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) 328 329 static inline int 330 write_packet(u8 *buf, struct omap_req *req, unsigned max) 331 { 332 unsigned len; 333 u16 *wp; 334 335 len = min(req->req.length - req->req.actual, max); 336 req->req.actual += len; 337 338 max = len; 339 if (likely((((int)buf) & 1) == 0)) { 340 wp = (u16 *)buf; 341 while (max >= 2) { 342 omap_writew(*wp++, UDC_DATA); 343 max -= 2; 344 } 345 buf = (u8 *)wp; 346 } 347 while (max--) 348 omap_writeb(*buf++, UDC_DATA); 349 return len; 350 } 351 352 /* FIXME change r/w fifo calling convention */ 353 354 355 /* return: 0 = still running, 1 = completed, negative = errno */ 356 static int write_fifo(struct omap_ep *ep, struct omap_req *req) 357 { 358 u8 *buf; 359 unsigned count; 360 int is_last; 361 u16 ep_stat; 362 363 buf = req->req.buf + req->req.actual; 364 prefetch(buf); 365 366 /* PIO-IN isn't double buffered except for iso */ 367 ep_stat = omap_readw(UDC_STAT_FLG); 368 if (ep_stat & UDC_FIFO_UNWRITABLE) 369 return 0; 370 371 count = ep->ep.maxpacket; 372 count = write_packet(buf, req, count); 373 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 374 ep->ackwait = 1; 375 376 /* last packet is often short (sometimes a zlp) */ 377 if (count != ep->ep.maxpacket) 378 is_last = 1; 379 else if (req->req.length == req->req.actual 380 && !req->req.zero) 381 is_last = 1; 382 else 383 is_last = 0; 384 385 /* NOTE: requests complete when all IN data is in a 386 * FIFO (or sometimes later, if a zlp was needed). 387 * Use usb_ep_fifo_status() where needed. 388 */ 389 if (is_last) 390 done(ep, req, 0); 391 return is_last; 392 } 393 394 static inline int 395 read_packet(u8 *buf, struct omap_req *req, unsigned avail) 396 { 397 unsigned len; 398 u16 *wp; 399 400 len = min(req->req.length - req->req.actual, avail); 401 req->req.actual += len; 402 avail = len; 403 404 if (likely((((int)buf) & 1) == 0)) { 405 wp = (u16 *)buf; 406 while (avail >= 2) { 407 *wp++ = omap_readw(UDC_DATA); 408 avail -= 2; 409 } 410 buf = (u8 *)wp; 411 } 412 while (avail--) 413 *buf++ = omap_readb(UDC_DATA); 414 return len; 415 } 416 417 /* return: 0 = still running, 1 = queue empty, negative = errno */ 418 static int read_fifo(struct omap_ep *ep, struct omap_req *req) 419 { 420 u8 *buf; 421 unsigned count, avail; 422 int is_last; 423 424 buf = req->req.buf + req->req.actual; 425 prefetchw(buf); 426 427 for (;;) { 428 u16 ep_stat = omap_readw(UDC_STAT_FLG); 429 430 is_last = 0; 431 if (ep_stat & FIFO_EMPTY) { 432 if (!ep->double_buf) 433 break; 434 ep->fnf = 1; 435 } 436 if (ep_stat & UDC_EP_HALTED) 437 break; 438 439 if (ep_stat & UDC_FIFO_FULL) 440 avail = ep->ep.maxpacket; 441 else { 442 avail = omap_readw(UDC_RXFSTAT); 443 ep->fnf = ep->double_buf; 444 } 445 count = read_packet(buf, req, avail); 446 447 /* partial packet reads may not be errors */ 448 if (count < ep->ep.maxpacket) { 449 is_last = 1; 450 /* overflowed this request? flush extra data */ 451 if (count != avail) { 452 req->req.status = -EOVERFLOW; 453 avail -= count; 454 while (avail--) 455 omap_readw(UDC_DATA); 456 } 457 } else if (req->req.length == req->req.actual) 458 is_last = 1; 459 else 460 is_last = 0; 461 462 if (!ep->bEndpointAddress) 463 break; 464 if (is_last) 465 done(ep, req, 0); 466 break; 467 } 468 return is_last; 469 } 470 471 /*-------------------------------------------------------------------------*/ 472 473 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 474 { 475 dma_addr_t end; 476 477 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports 478 * the last transfer's bytecount by more than a FIFO's worth. 479 */ 480 if (cpu_is_omap15xx()) 481 return 0; 482 483 end = omap_get_dma_src_pos(ep->lch); 484 if (end == ep->dma_counter) 485 return 0; 486 487 end |= start & (0xffff << 16); 488 if (end < start) 489 end += 0x10000; 490 return end - start; 491 } 492 493 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) 494 { 495 dma_addr_t end; 496 497 end = omap_get_dma_dst_pos(ep->lch); 498 if (end == ep->dma_counter) 499 return 0; 500 501 end |= start & (0xffff << 16); 502 if (cpu_is_omap15xx()) 503 end++; 504 if (end < start) 505 end += 0x10000; 506 return end - start; 507 } 508 509 510 /* Each USB transfer request using DMA maps to one or more DMA transfers. 511 * When DMA completion isn't request completion, the UDC continues with 512 * the next DMA transfer for that USB transfer. 513 */ 514 515 static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 516 { 517 u16 txdma_ctrl, w; 518 unsigned length = req->req.length - req->req.actual; 519 const int sync_mode = cpu_is_omap15xx() 520 ? OMAP_DMA_SYNC_FRAME 521 : OMAP_DMA_SYNC_ELEMENT; 522 int dma_trigger = 0; 523 524 /* measure length in either bytes or packets */ 525 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC) 526 || (cpu_is_omap15xx() && length < ep->maxpacket)) { 527 txdma_ctrl = UDC_TXN_EOT | length; 528 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 529 length, 1, sync_mode, dma_trigger, 0); 530 } else { 531 length = min(length / ep->maxpacket, 532 (unsigned) UDC_TXN_TSC + 1); 533 txdma_ctrl = length; 534 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 535 ep->ep.maxpacket >> 1, length, sync_mode, 536 dma_trigger, 0); 537 length *= ep->maxpacket; 538 } 539 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, 540 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 541 0, 0); 542 543 omap_start_dma(ep->lch); 544 ep->dma_counter = omap_get_dma_src_pos(ep->lch); 545 w = omap_readw(UDC_DMA_IRQ_EN); 546 w |= UDC_TX_DONE_IE(ep->dma_channel); 547 omap_writew(w, UDC_DMA_IRQ_EN); 548 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); 549 req->dma_bytes = length; 550 } 551 552 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) 553 { 554 u16 w; 555 556 if (status == 0) { 557 req->req.actual += req->dma_bytes; 558 559 /* return if this request needs to send data or zlp */ 560 if (req->req.actual < req->req.length) 561 return; 562 if (req->req.zero 563 && req->dma_bytes != 0 564 && (req->req.actual % ep->maxpacket) == 0) 565 return; 566 } else 567 req->req.actual += dma_src_len(ep, req->req.dma 568 + req->req.actual); 569 570 /* tx completion */ 571 omap_stop_dma(ep->lch); 572 w = omap_readw(UDC_DMA_IRQ_EN); 573 w &= ~UDC_TX_DONE_IE(ep->dma_channel); 574 omap_writew(w, UDC_DMA_IRQ_EN); 575 done(ep, req, status); 576 } 577 578 static void next_out_dma(struct omap_ep *ep, struct omap_req *req) 579 { 580 unsigned int packets = req->req.length - req->req.actual; 581 int dma_trigger = 0; 582 u16 w; 583 584 /* set up this DMA transfer, enable the fifo, start */ 585 packets /= ep->ep.maxpacket; 586 packets = min_t(unsigned int, packets, UDC_RXN_TC + 1); 587 req->dma_bytes = packets * ep->ep.maxpacket; 588 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 589 ep->ep.maxpacket >> 1, packets, 590 OMAP_DMA_SYNC_ELEMENT, 591 dma_trigger, 0); 592 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, 593 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 594 0, 0); 595 ep->dma_counter = omap_get_dma_dst_pos(ep->lch); 596 597 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); 598 w = omap_readw(UDC_DMA_IRQ_EN); 599 w |= UDC_RX_EOT_IE(ep->dma_channel); 600 omap_writew(w, UDC_DMA_IRQ_EN); 601 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); 602 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 603 604 omap_start_dma(ep->lch); 605 } 606 607 static void 608 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) 609 { 610 u16 count, w; 611 612 if (status == 0) 613 ep->dma_counter = (u16) (req->req.dma + req->req.actual); 614 count = dma_dest_len(ep, req->req.dma + req->req.actual); 615 count += req->req.actual; 616 if (one) 617 count--; 618 if (count <= req->req.length) 619 req->req.actual = count; 620 621 if (count != req->dma_bytes || status) 622 omap_stop_dma(ep->lch); 623 624 /* if this wasn't short, request may need another transfer */ 625 else if (req->req.actual < req->req.length) 626 return; 627 628 /* rx completion */ 629 w = omap_readw(UDC_DMA_IRQ_EN); 630 w &= ~UDC_RX_EOT_IE(ep->dma_channel); 631 omap_writew(w, UDC_DMA_IRQ_EN); 632 done(ep, req, status); 633 } 634 635 static void dma_irq(struct omap_udc *udc, u16 irq_src) 636 { 637 u16 dman_stat = omap_readw(UDC_DMAN_STAT); 638 struct omap_ep *ep; 639 struct omap_req *req; 640 641 /* IN dma: tx to host */ 642 if (irq_src & UDC_TXN_DONE) { 643 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)]; 644 ep->irqs++; 645 /* can see TXN_DONE after dma abort */ 646 if (!list_empty(&ep->queue)) { 647 req = container_of(ep->queue.next, 648 struct omap_req, queue); 649 finish_in_dma(ep, req, 0); 650 } 651 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); 652 653 if (!list_empty(&ep->queue)) { 654 req = container_of(ep->queue.next, 655 struct omap_req, queue); 656 next_in_dma(ep, req); 657 } 658 } 659 660 /* OUT dma: rx from host */ 661 if (irq_src & UDC_RXN_EOT) { 662 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 663 ep->irqs++; 664 /* can see RXN_EOT after dma abort */ 665 if (!list_empty(&ep->queue)) { 666 req = container_of(ep->queue.next, 667 struct omap_req, queue); 668 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); 669 } 670 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); 671 672 if (!list_empty(&ep->queue)) { 673 req = container_of(ep->queue.next, 674 struct omap_req, queue); 675 next_out_dma(ep, req); 676 } 677 } 678 679 if (irq_src & UDC_RXN_CNT) { 680 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 681 ep->irqs++; 682 /* omap15xx does this unasked... */ 683 VDBG("%s, RX_CNT irq?\n", ep->ep.name); 684 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); 685 } 686 } 687 688 static void dma_error(int lch, u16 ch_status, void *data) 689 { 690 struct omap_ep *ep = data; 691 692 /* if ch_status & OMAP_DMA_DROP_IRQ ... */ 693 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */ 694 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); 695 696 /* complete current transfer ... */ 697 } 698 699 static void dma_channel_claim(struct omap_ep *ep, unsigned channel) 700 { 701 u16 reg; 702 int status, restart, is_in; 703 int dma_channel; 704 705 is_in = ep->bEndpointAddress & USB_DIR_IN; 706 if (is_in) 707 reg = omap_readw(UDC_TXDMA_CFG); 708 else 709 reg = omap_readw(UDC_RXDMA_CFG); 710 reg |= UDC_DMA_REQ; /* "pulse" activated */ 711 712 ep->dma_channel = 0; 713 ep->lch = -1; 714 if (channel == 0 || channel > 3) { 715 if ((reg & 0x0f00) == 0) 716 channel = 3; 717 else if ((reg & 0x00f0) == 0) 718 channel = 2; 719 else if ((reg & 0x000f) == 0) /* preferred for ISO */ 720 channel = 1; 721 else { 722 status = -EMLINK; 723 goto just_restart; 724 } 725 } 726 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); 727 ep->dma_channel = channel; 728 729 if (is_in) { 730 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel; 731 status = omap_request_dma(dma_channel, 732 ep->ep.name, dma_error, ep, &ep->lch); 733 if (status == 0) { 734 omap_writew(reg, UDC_TXDMA_CFG); 735 /* EMIFF or SDRC */ 736 omap_set_dma_src_data_pack(ep->lch, 1); 737 /* TIPB */ 738 omap_set_dma_dest_params(ep->lch, 739 OMAP_DMA_PORT_TIPB, 740 OMAP_DMA_AMODE_CONSTANT, 741 UDC_DATA_DMA, 742 0, 0); 743 } 744 } else { 745 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel; 746 status = omap_request_dma(dma_channel, 747 ep->ep.name, dma_error, ep, &ep->lch); 748 if (status == 0) { 749 omap_writew(reg, UDC_RXDMA_CFG); 750 /* TIPB */ 751 omap_set_dma_src_params(ep->lch, 752 OMAP_DMA_PORT_TIPB, 753 OMAP_DMA_AMODE_CONSTANT, 754 UDC_DATA_DMA, 755 0, 0); 756 /* EMIFF or SDRC */ 757 omap_set_dma_dest_data_pack(ep->lch, 1); 758 } 759 } 760 if (status) 761 ep->dma_channel = 0; 762 else { 763 ep->has_dma = 1; 764 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ); 765 766 /* channel type P: hw synch (fifo) */ 767 if (!cpu_is_omap15xx()) 768 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P); 769 } 770 771 just_restart: 772 /* restart any queue, even if the claim failed */ 773 restart = !ep->stopped && !list_empty(&ep->queue); 774 775 if (status) 776 DBG("%s no dma channel: %d%s\n", ep->ep.name, status, 777 restart ? " (restart)" : ""); 778 else 779 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name, 780 is_in ? 't' : 'r', 781 ep->dma_channel - 1, ep->lch, 782 restart ? " (restart)" : ""); 783 784 if (restart) { 785 struct omap_req *req; 786 req = container_of(ep->queue.next, struct omap_req, queue); 787 if (ep->has_dma) 788 (is_in ? next_in_dma : next_out_dma)(ep, req); 789 else { 790 use_ep(ep, UDC_EP_SEL); 791 (is_in ? write_fifo : read_fifo)(ep, req); 792 deselect_ep(); 793 if (!is_in) { 794 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 795 ep->ackwait = 1 + ep->double_buf; 796 } 797 /* IN: 6 wait states before it'll tx */ 798 } 799 } 800 } 801 802 static void dma_channel_release(struct omap_ep *ep) 803 { 804 int shift = 4 * (ep->dma_channel - 1); 805 u16 mask = 0x0f << shift; 806 struct omap_req *req; 807 int active; 808 809 /* abort any active usb transfer request */ 810 if (!list_empty(&ep->queue)) 811 req = container_of(ep->queue.next, struct omap_req, queue); 812 else 813 req = NULL; 814 815 active = omap_get_dma_active_status(ep->lch); 816 817 DBG("%s release %s %cxdma%d %p\n", ep->ep.name, 818 active ? "active" : "idle", 819 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 820 ep->dma_channel - 1, req); 821 822 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before 823 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them. 824 */ 825 826 /* wait till current packet DMA finishes, and fifo empties */ 827 if (ep->bEndpointAddress & USB_DIR_IN) { 828 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, 829 UDC_TXDMA_CFG); 830 831 if (req) { 832 finish_in_dma(ep, req, -ECONNRESET); 833 834 /* clear FIFO; hosts probably won't empty it */ 835 use_ep(ep, UDC_EP_SEL); 836 omap_writew(UDC_CLR_EP, UDC_CTRL); 837 deselect_ep(); 838 } 839 while (omap_readw(UDC_TXDMA_CFG) & mask) 840 udelay(10); 841 } else { 842 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, 843 UDC_RXDMA_CFG); 844 845 /* dma empties the fifo */ 846 while (omap_readw(UDC_RXDMA_CFG) & mask) 847 udelay(10); 848 if (req) 849 finish_out_dma(ep, req, -ECONNRESET, 0); 850 } 851 omap_free_dma(ep->lch); 852 ep->dma_channel = 0; 853 ep->lch = -1; 854 /* has_dma still set, till endpoint is fully quiesced */ 855 } 856 857 858 /*-------------------------------------------------------------------------*/ 859 860 static int 861 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 862 { 863 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 864 struct omap_req *req = container_of(_req, struct omap_req, req); 865 struct omap_udc *udc; 866 unsigned long flags; 867 int is_iso = 0; 868 869 /* catch various bogus parameters */ 870 if (!_req || !req->req.complete || !req->req.buf 871 || !list_empty(&req->queue)) { 872 DBG("%s, bad params\n", __func__); 873 return -EINVAL; 874 } 875 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) { 876 DBG("%s, bad ep\n", __func__); 877 return -EINVAL; 878 } 879 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 880 if (req->req.length > ep->ep.maxpacket) 881 return -EMSGSIZE; 882 is_iso = 1; 883 } 884 885 /* this isn't bogus, but OMAP DMA isn't the only hardware to 886 * have a hard time with partial packet reads... reject it. 887 */ 888 if (use_dma 889 && ep->has_dma 890 && ep->bEndpointAddress != 0 891 && (ep->bEndpointAddress & USB_DIR_IN) == 0 892 && (req->req.length % ep->ep.maxpacket) != 0) { 893 DBG("%s, no partial packet OUT reads\n", __func__); 894 return -EMSGSIZE; 895 } 896 897 udc = ep->udc; 898 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 899 return -ESHUTDOWN; 900 901 if (use_dma && ep->has_dma) 902 usb_gadget_map_request(&udc->gadget, &req->req, 903 (ep->bEndpointAddress & USB_DIR_IN)); 904 905 VDBG("%s queue req %p, len %d buf %p\n", 906 ep->ep.name, _req, _req->length, _req->buf); 907 908 spin_lock_irqsave(&udc->lock, flags); 909 910 req->req.status = -EINPROGRESS; 911 req->req.actual = 0; 912 913 /* maybe kickstart non-iso i/o queues */ 914 if (is_iso) { 915 u16 w; 916 917 w = omap_readw(UDC_IRQ_EN); 918 w |= UDC_SOF_IE; 919 omap_writew(w, UDC_IRQ_EN); 920 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { 921 int is_in; 922 923 if (ep->bEndpointAddress == 0) { 924 if (!udc->ep0_pending || !list_empty(&ep->queue)) { 925 spin_unlock_irqrestore(&udc->lock, flags); 926 return -EL2HLT; 927 } 928 929 /* empty DATA stage? */ 930 is_in = udc->ep0_in; 931 if (!req->req.length) { 932 933 /* chip became CONFIGURED or ADDRESSED 934 * earlier; drivers may already have queued 935 * requests to non-control endpoints 936 */ 937 if (udc->ep0_set_config) { 938 u16 irq_en = omap_readw(UDC_IRQ_EN); 939 940 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; 941 if (!udc->ep0_reset_config) 942 irq_en |= UDC_EPN_RX_IE 943 | UDC_EPN_TX_IE; 944 omap_writew(irq_en, UDC_IRQ_EN); 945 } 946 947 /* STATUS for zero length DATA stages is 948 * always an IN ... even for IN transfers, 949 * a weird case which seem to stall OMAP. 950 */ 951 omap_writew(UDC_EP_SEL | UDC_EP_DIR, 952 UDC_EP_NUM); 953 omap_writew(UDC_CLR_EP, UDC_CTRL); 954 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 955 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 956 957 /* cleanup */ 958 udc->ep0_pending = 0; 959 done(ep, req, 0); 960 req = NULL; 961 962 /* non-empty DATA stage */ 963 } else if (is_in) { 964 omap_writew(UDC_EP_SEL | UDC_EP_DIR, 965 UDC_EP_NUM); 966 } else { 967 if (udc->ep0_setup) 968 goto irq_wait; 969 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 970 } 971 } else { 972 is_in = ep->bEndpointAddress & USB_DIR_IN; 973 if (!ep->has_dma) 974 use_ep(ep, UDC_EP_SEL); 975 /* if ISO: SOF IRQs must be enabled/disabled! */ 976 } 977 978 if (ep->has_dma) 979 (is_in ? next_in_dma : next_out_dma)(ep, req); 980 else if (req) { 981 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) 982 req = NULL; 983 deselect_ep(); 984 if (!is_in) { 985 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 986 ep->ackwait = 1 + ep->double_buf; 987 } 988 /* IN: 6 wait states before it'll tx */ 989 } 990 } 991 992 irq_wait: 993 /* irq handler advances the queue */ 994 if (req != NULL) 995 list_add_tail(&req->queue, &ep->queue); 996 spin_unlock_irqrestore(&udc->lock, flags); 997 998 return 0; 999 } 1000 1001 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1002 { 1003 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1004 struct omap_req *req = NULL, *iter; 1005 unsigned long flags; 1006 1007 if (!_ep || !_req) 1008 return -EINVAL; 1009 1010 spin_lock_irqsave(&ep->udc->lock, flags); 1011 1012 /* make sure it's actually queued on this endpoint */ 1013 list_for_each_entry(iter, &ep->queue, queue) { 1014 if (&iter->req != _req) 1015 continue; 1016 req = iter; 1017 break; 1018 } 1019 if (!req) { 1020 spin_unlock_irqrestore(&ep->udc->lock, flags); 1021 return -EINVAL; 1022 } 1023 1024 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) { 1025 int channel = ep->dma_channel; 1026 1027 /* releasing the channel cancels the request, 1028 * reclaiming the channel restarts the queue 1029 */ 1030 dma_channel_release(ep); 1031 dma_channel_claim(ep, channel); 1032 } else 1033 done(ep, req, -ECONNRESET); 1034 spin_unlock_irqrestore(&ep->udc->lock, flags); 1035 return 0; 1036 } 1037 1038 /*-------------------------------------------------------------------------*/ 1039 1040 static int omap_ep_set_halt(struct usb_ep *_ep, int value) 1041 { 1042 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1043 unsigned long flags; 1044 int status = -EOPNOTSUPP; 1045 1046 spin_lock_irqsave(&ep->udc->lock, flags); 1047 1048 /* just use protocol stalls for ep0; real halts are annoying */ 1049 if (ep->bEndpointAddress == 0) { 1050 if (!ep->udc->ep0_pending) 1051 status = -EINVAL; 1052 else if (value) { 1053 if (ep->udc->ep0_set_config) { 1054 WARNING("error changing config?\n"); 1055 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1056 } 1057 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1058 ep->udc->ep0_pending = 0; 1059 status = 0; 1060 } else /* NOP */ 1061 status = 0; 1062 1063 /* otherwise, all active non-ISO endpoints can halt */ 1064 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) { 1065 1066 /* IN endpoints must already be idle */ 1067 if ((ep->bEndpointAddress & USB_DIR_IN) 1068 && !list_empty(&ep->queue)) { 1069 status = -EAGAIN; 1070 goto done; 1071 } 1072 1073 if (value) { 1074 int channel; 1075 1076 if (use_dma && ep->dma_channel 1077 && !list_empty(&ep->queue)) { 1078 channel = ep->dma_channel; 1079 dma_channel_release(ep); 1080 } else 1081 channel = 0; 1082 1083 use_ep(ep, UDC_EP_SEL); 1084 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { 1085 omap_writew(UDC_SET_HALT, UDC_CTRL); 1086 status = 0; 1087 } else 1088 status = -EAGAIN; 1089 deselect_ep(); 1090 1091 if (channel) 1092 dma_channel_claim(ep, channel); 1093 } else { 1094 use_ep(ep, 0); 1095 omap_writew(ep->udc->clr_halt, UDC_CTRL); 1096 ep->ackwait = 0; 1097 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1098 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1099 ep->ackwait = 1 + ep->double_buf; 1100 } 1101 } 1102 } 1103 done: 1104 VDBG("%s %s halt stat %d\n", ep->ep.name, 1105 value ? "set" : "clear", status); 1106 1107 spin_unlock_irqrestore(&ep->udc->lock, flags); 1108 return status; 1109 } 1110 1111 static const struct usb_ep_ops omap_ep_ops = { 1112 .enable = omap_ep_enable, 1113 .disable = omap_ep_disable, 1114 1115 .alloc_request = omap_alloc_request, 1116 .free_request = omap_free_request, 1117 1118 .queue = omap_ep_queue, 1119 .dequeue = omap_ep_dequeue, 1120 1121 .set_halt = omap_ep_set_halt, 1122 /* fifo_status ... report bytes in fifo */ 1123 /* fifo_flush ... flush fifo */ 1124 }; 1125 1126 /*-------------------------------------------------------------------------*/ 1127 1128 static int omap_get_frame(struct usb_gadget *gadget) 1129 { 1130 u16 sof = omap_readw(UDC_SOF); 1131 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; 1132 } 1133 1134 static int omap_wakeup(struct usb_gadget *gadget) 1135 { 1136 struct omap_udc *udc; 1137 unsigned long flags; 1138 int retval = -EHOSTUNREACH; 1139 1140 udc = container_of(gadget, struct omap_udc, gadget); 1141 1142 spin_lock_irqsave(&udc->lock, flags); 1143 if (udc->devstat & UDC_SUS) { 1144 /* NOTE: OTG spec erratum says that OTG devices may 1145 * issue wakeups without host enable. 1146 */ 1147 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { 1148 DBG("remote wakeup...\n"); 1149 omap_writew(UDC_RMT_WKP, UDC_SYSCON2); 1150 retval = 0; 1151 } 1152 1153 /* NOTE: non-OTG systems may use SRP TOO... */ 1154 } else if (!(udc->devstat & UDC_ATT)) { 1155 if (!IS_ERR_OR_NULL(udc->transceiver)) 1156 retval = otg_start_srp(udc->transceiver->otg); 1157 } 1158 spin_unlock_irqrestore(&udc->lock, flags); 1159 1160 return retval; 1161 } 1162 1163 static int 1164 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) 1165 { 1166 struct omap_udc *udc; 1167 unsigned long flags; 1168 u16 syscon1; 1169 1170 gadget->is_selfpowered = (is_selfpowered != 0); 1171 udc = container_of(gadget, struct omap_udc, gadget); 1172 spin_lock_irqsave(&udc->lock, flags); 1173 syscon1 = omap_readw(UDC_SYSCON1); 1174 if (is_selfpowered) 1175 syscon1 |= UDC_SELF_PWR; 1176 else 1177 syscon1 &= ~UDC_SELF_PWR; 1178 omap_writew(syscon1, UDC_SYSCON1); 1179 spin_unlock_irqrestore(&udc->lock, flags); 1180 1181 return 0; 1182 } 1183 1184 static int can_pullup(struct omap_udc *udc) 1185 { 1186 return udc->driver && udc->softconnect && udc->vbus_active; 1187 } 1188 1189 static void pullup_enable(struct omap_udc *udc) 1190 { 1191 u16 w; 1192 1193 w = omap_readw(UDC_SYSCON1); 1194 w |= UDC_PULLUP_EN; 1195 omap_writew(w, UDC_SYSCON1); 1196 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { 1197 u32 l; 1198 1199 l = omap_readl(OTG_CTRL); 1200 l |= OTG_BSESSVLD; 1201 omap_writel(l, OTG_CTRL); 1202 } 1203 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); 1204 } 1205 1206 static void pullup_disable(struct omap_udc *udc) 1207 { 1208 u16 w; 1209 1210 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { 1211 u32 l; 1212 1213 l = omap_readl(OTG_CTRL); 1214 l &= ~OTG_BSESSVLD; 1215 omap_writel(l, OTG_CTRL); 1216 } 1217 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); 1218 w = omap_readw(UDC_SYSCON1); 1219 w &= ~UDC_PULLUP_EN; 1220 omap_writew(w, UDC_SYSCON1); 1221 } 1222 1223 static struct omap_udc *udc; 1224 1225 static void omap_udc_enable_clock(int enable) 1226 { 1227 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL) 1228 return; 1229 1230 if (enable) { 1231 clk_enable(udc->dc_clk); 1232 clk_enable(udc->hhc_clk); 1233 udelay(100); 1234 } else { 1235 clk_disable(udc->hhc_clk); 1236 clk_disable(udc->dc_clk); 1237 } 1238 } 1239 1240 /* 1241 * Called by whatever detects VBUS sessions: external transceiver 1242 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock. 1243 */ 1244 static int omap_vbus_session(struct usb_gadget *gadget, int is_active) 1245 { 1246 struct omap_udc *udc; 1247 unsigned long flags; 1248 u32 l; 1249 1250 udc = container_of(gadget, struct omap_udc, gadget); 1251 spin_lock_irqsave(&udc->lock, flags); 1252 VDBG("VBUS %s\n", str_on_off(is_active)); 1253 udc->vbus_active = (is_active != 0); 1254 if (cpu_is_omap15xx()) { 1255 /* "software" detect, ignored if !VBUS_MODE_1510 */ 1256 l = omap_readl(FUNC_MUX_CTRL_0); 1257 if (is_active) 1258 l |= VBUS_CTRL_1510; 1259 else 1260 l &= ~VBUS_CTRL_1510; 1261 omap_writel(l, FUNC_MUX_CTRL_0); 1262 } 1263 if (udc->dc_clk != NULL && is_active) { 1264 if (!udc->clk_requested) { 1265 omap_udc_enable_clock(1); 1266 udc->clk_requested = 1; 1267 } 1268 } 1269 if (can_pullup(udc)) 1270 pullup_enable(udc); 1271 else 1272 pullup_disable(udc); 1273 if (udc->dc_clk != NULL && !is_active) { 1274 if (udc->clk_requested) { 1275 omap_udc_enable_clock(0); 1276 udc->clk_requested = 0; 1277 } 1278 } 1279 spin_unlock_irqrestore(&udc->lock, flags); 1280 return 0; 1281 } 1282 1283 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1284 { 1285 struct omap_udc *udc; 1286 1287 udc = container_of(gadget, struct omap_udc, gadget); 1288 if (!IS_ERR_OR_NULL(udc->transceiver)) 1289 return usb_phy_set_power(udc->transceiver, mA); 1290 return -EOPNOTSUPP; 1291 } 1292 1293 static int omap_pullup(struct usb_gadget *gadget, int is_on) 1294 { 1295 struct omap_udc *udc; 1296 unsigned long flags; 1297 1298 udc = container_of(gadget, struct omap_udc, gadget); 1299 spin_lock_irqsave(&udc->lock, flags); 1300 udc->softconnect = (is_on != 0); 1301 if (can_pullup(udc)) 1302 pullup_enable(udc); 1303 else 1304 pullup_disable(udc); 1305 spin_unlock_irqrestore(&udc->lock, flags); 1306 return 0; 1307 } 1308 1309 static int omap_udc_start(struct usb_gadget *g, 1310 struct usb_gadget_driver *driver); 1311 static int omap_udc_stop(struct usb_gadget *g); 1312 1313 static const struct usb_gadget_ops omap_gadget_ops = { 1314 .get_frame = omap_get_frame, 1315 .wakeup = omap_wakeup, 1316 .set_selfpowered = omap_set_selfpowered, 1317 .vbus_session = omap_vbus_session, 1318 .vbus_draw = omap_vbus_draw, 1319 .pullup = omap_pullup, 1320 .udc_start = omap_udc_start, 1321 .udc_stop = omap_udc_stop, 1322 }; 1323 1324 /*-------------------------------------------------------------------------*/ 1325 1326 /* dequeue ALL requests; caller holds udc->lock */ 1327 static void nuke(struct omap_ep *ep, int status) 1328 { 1329 struct omap_req *req; 1330 1331 ep->stopped = 1; 1332 1333 if (use_dma && ep->dma_channel) 1334 dma_channel_release(ep); 1335 1336 use_ep(ep, 0); 1337 omap_writew(UDC_CLR_EP, UDC_CTRL); 1338 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) 1339 omap_writew(UDC_SET_HALT, UDC_CTRL); 1340 1341 while (!list_empty(&ep->queue)) { 1342 req = list_entry(ep->queue.next, struct omap_req, queue); 1343 done(ep, req, status); 1344 } 1345 } 1346 1347 /* caller holds udc->lock */ 1348 static void udc_quiesce(struct omap_udc *udc) 1349 { 1350 struct omap_ep *ep; 1351 1352 udc->gadget.speed = USB_SPEED_UNKNOWN; 1353 nuke(&udc->ep[0], -ESHUTDOWN); 1354 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) 1355 nuke(ep, -ESHUTDOWN); 1356 } 1357 1358 /*-------------------------------------------------------------------------*/ 1359 1360 static void update_otg(struct omap_udc *udc) 1361 { 1362 u16 devstat; 1363 1364 if (!gadget_is_otg(&udc->gadget)) 1365 return; 1366 1367 if (omap_readl(OTG_CTRL) & OTG_ID) 1368 devstat = omap_readw(UDC_DEVSTAT); 1369 else 1370 devstat = 0; 1371 1372 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE); 1373 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT); 1374 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT); 1375 1376 /* Enable HNP early, avoiding races on suspend irq path. 1377 * ASSUMES OTG state machine B_BUS_REQ input is true. 1378 */ 1379 if (udc->gadget.b_hnp_enable) { 1380 u32 l; 1381 1382 l = omap_readl(OTG_CTRL); 1383 l |= OTG_B_HNPEN | OTG_B_BUSREQ; 1384 l &= ~OTG_PULLUP; 1385 omap_writel(l, OTG_CTRL); 1386 } 1387 } 1388 1389 static void ep0_irq(struct omap_udc *udc, u16 irq_src) 1390 { 1391 struct omap_ep *ep0 = &udc->ep[0]; 1392 struct omap_req *req = NULL; 1393 1394 ep0->irqs++; 1395 1396 /* Clear any pending requests and then scrub any rx/tx state 1397 * before starting to handle the SETUP request. 1398 */ 1399 if (irq_src & UDC_SETUP) { 1400 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX); 1401 1402 nuke(ep0, 0); 1403 if (ack) { 1404 omap_writew(ack, UDC_IRQ_SRC); 1405 irq_src = UDC_SETUP; 1406 } 1407 } 1408 1409 /* IN/OUT packets mean we're in the DATA or STATUS stage. 1410 * This driver uses only uses protocol stalls (ep0 never halts), 1411 * and if we got this far the gadget driver already had a 1412 * chance to stall. Tries to be forgiving of host oddities. 1413 * 1414 * NOTE: the last chance gadget drivers have to stall control 1415 * requests is during their request completion callback. 1416 */ 1417 if (!list_empty(&ep0->queue)) 1418 req = container_of(ep0->queue.next, struct omap_req, queue); 1419 1420 /* IN == TX to host */ 1421 if (irq_src & UDC_EP0_TX) { 1422 int stat; 1423 1424 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); 1425 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1426 stat = omap_readw(UDC_STAT_FLG); 1427 if (stat & UDC_ACK) { 1428 if (udc->ep0_in) { 1429 /* write next IN packet from response, 1430 * or set up the status stage. 1431 */ 1432 if (req) 1433 stat = write_fifo(ep0, req); 1434 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1435 if (!req && udc->ep0_pending) { 1436 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 1437 omap_writew(UDC_CLR_EP, UDC_CTRL); 1438 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1439 omap_writew(0, UDC_EP_NUM); 1440 udc->ep0_pending = 0; 1441 } /* else: 6 wait states before it'll tx */ 1442 } else { 1443 /* ack status stage of OUT transfer */ 1444 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1445 if (req) 1446 done(ep0, req, 0); 1447 } 1448 req = NULL; 1449 } else if (stat & UDC_STALL) { 1450 omap_writew(UDC_CLR_HALT, UDC_CTRL); 1451 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1452 } else { 1453 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1454 } 1455 } 1456 1457 /* OUT == RX from host */ 1458 if (irq_src & UDC_EP0_RX) { 1459 int stat; 1460 1461 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); 1462 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 1463 stat = omap_readw(UDC_STAT_FLG); 1464 if (stat & UDC_ACK) { 1465 if (!udc->ep0_in) { 1466 stat = 0; 1467 /* read next OUT packet of request, maybe 1468 * reactivating the fifo; stall on errors. 1469 */ 1470 stat = read_fifo(ep0, req); 1471 if (!req || stat < 0) { 1472 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1473 udc->ep0_pending = 0; 1474 stat = 0; 1475 } else if (stat == 0) 1476 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1477 omap_writew(0, UDC_EP_NUM); 1478 1479 /* activate status stage */ 1480 if (stat == 1) { 1481 done(ep0, req, 0); 1482 /* that may have STALLed ep0... */ 1483 omap_writew(UDC_EP_SEL | UDC_EP_DIR, 1484 UDC_EP_NUM); 1485 omap_writew(UDC_CLR_EP, UDC_CTRL); 1486 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1487 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1488 udc->ep0_pending = 0; 1489 } 1490 } else { 1491 /* ack status stage of IN transfer */ 1492 omap_writew(0, UDC_EP_NUM); 1493 if (req) 1494 done(ep0, req, 0); 1495 } 1496 } else if (stat & UDC_STALL) { 1497 omap_writew(UDC_CLR_HALT, UDC_CTRL); 1498 omap_writew(0, UDC_EP_NUM); 1499 } else { 1500 omap_writew(0, UDC_EP_NUM); 1501 } 1502 } 1503 1504 /* SETUP starts all control transfers */ 1505 if (irq_src & UDC_SETUP) { 1506 union u { 1507 u16 word[4]; 1508 struct usb_ctrlrequest r; 1509 } u; 1510 int status = -EINVAL; 1511 struct omap_ep *ep; 1512 1513 /* read the (latest) SETUP message */ 1514 do { 1515 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); 1516 /* two bytes at a time */ 1517 u.word[0] = omap_readw(UDC_DATA); 1518 u.word[1] = omap_readw(UDC_DATA); 1519 u.word[2] = omap_readw(UDC_DATA); 1520 u.word[3] = omap_readw(UDC_DATA); 1521 omap_writew(0, UDC_EP_NUM); 1522 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); 1523 1524 #define w_value le16_to_cpu(u.r.wValue) 1525 #define w_index le16_to_cpu(u.r.wIndex) 1526 #define w_length le16_to_cpu(u.r.wLength) 1527 1528 /* Delegate almost all control requests to the gadget driver, 1529 * except for a handful of ch9 status/feature requests that 1530 * hardware doesn't autodecode _and_ the gadget API hides. 1531 */ 1532 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0; 1533 udc->ep0_set_config = 0; 1534 udc->ep0_pending = 1; 1535 ep0->stopped = 0; 1536 ep0->ackwait = 0; 1537 switch (u.r.bRequest) { 1538 case USB_REQ_SET_CONFIGURATION: 1539 /* udc needs to know when ep != 0 is valid */ 1540 if (u.r.bRequestType != USB_RECIP_DEVICE) 1541 goto delegate; 1542 if (w_length != 0) 1543 goto do_stall; 1544 udc->ep0_set_config = 1; 1545 udc->ep0_reset_config = (w_value == 0); 1546 VDBG("set config %d\n", w_value); 1547 1548 /* update udc NOW since gadget driver may start 1549 * queueing requests immediately; clear config 1550 * later if it fails the request. 1551 */ 1552 if (udc->ep0_reset_config) 1553 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1554 else 1555 omap_writew(UDC_DEV_CFG, UDC_SYSCON2); 1556 update_otg(udc); 1557 goto delegate; 1558 case USB_REQ_CLEAR_FEATURE: 1559 /* clear endpoint halt */ 1560 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1561 goto delegate; 1562 if (w_value != USB_ENDPOINT_HALT 1563 || w_length != 0) 1564 goto do_stall; 1565 ep = &udc->ep[w_index & 0xf]; 1566 if (ep != ep0) { 1567 if (w_index & USB_DIR_IN) 1568 ep += 16; 1569 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1570 || !ep->ep.desc) 1571 goto do_stall; 1572 use_ep(ep, 0); 1573 omap_writew(udc->clr_halt, UDC_CTRL); 1574 ep->ackwait = 0; 1575 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1576 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1577 ep->ackwait = 1 + ep->double_buf; 1578 } 1579 /* NOTE: assumes the host behaves sanely, 1580 * only clearing real halts. Else we may 1581 * need to kill pending transfers and then 1582 * restart the queue... very messy for DMA! 1583 */ 1584 } 1585 VDBG("%s halt cleared by host\n", ep->name); 1586 goto ep0out_status_stage; 1587 case USB_REQ_SET_FEATURE: 1588 /* set endpoint halt */ 1589 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1590 goto delegate; 1591 if (w_value != USB_ENDPOINT_HALT 1592 || w_length != 0) 1593 goto do_stall; 1594 ep = &udc->ep[w_index & 0xf]; 1595 if (w_index & USB_DIR_IN) 1596 ep += 16; 1597 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1598 || ep == ep0 || !ep->ep.desc) 1599 goto do_stall; 1600 if (use_dma && ep->has_dma) { 1601 /* this has rude side-effects (aborts) and 1602 * can't really work if DMA-IN is active 1603 */ 1604 DBG("%s host set_halt, NYET\n", ep->name); 1605 goto do_stall; 1606 } 1607 use_ep(ep, 0); 1608 /* can't halt if fifo isn't empty... */ 1609 omap_writew(UDC_CLR_EP, UDC_CTRL); 1610 omap_writew(UDC_SET_HALT, UDC_CTRL); 1611 VDBG("%s halted by host\n", ep->name); 1612 ep0out_status_stage: 1613 status = 0; 1614 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1615 omap_writew(UDC_CLR_EP, UDC_CTRL); 1616 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1617 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1618 udc->ep0_pending = 0; 1619 break; 1620 case USB_REQ_GET_STATUS: 1621 /* USB_ENDPOINT_HALT status? */ 1622 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT)) 1623 goto intf_status; 1624 1625 /* ep0 never stalls */ 1626 if (!(w_index & 0xf)) 1627 goto zero_status; 1628 1629 /* only active endpoints count */ 1630 ep = &udc->ep[w_index & 0xf]; 1631 if (w_index & USB_DIR_IN) 1632 ep += 16; 1633 if (!ep->ep.desc) 1634 goto do_stall; 1635 1636 /* iso never stalls */ 1637 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 1638 goto zero_status; 1639 1640 /* FIXME don't assume non-halted endpoints!! */ 1641 ERR("%s status, can't report\n", ep->ep.name); 1642 goto do_stall; 1643 1644 intf_status: 1645 /* return interface status. if we were pedantic, 1646 * we'd detect non-existent interfaces, and stall. 1647 */ 1648 if (u.r.bRequestType 1649 != (USB_DIR_IN|USB_RECIP_INTERFACE)) 1650 goto delegate; 1651 1652 zero_status: 1653 /* return two zero bytes */ 1654 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1655 omap_writew(0, UDC_DATA); 1656 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1657 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1658 status = 0; 1659 VDBG("GET_STATUS, interface %d\n", w_index); 1660 /* next, status stage */ 1661 break; 1662 default: 1663 delegate: 1664 /* activate the ep0out fifo right away */ 1665 if (!udc->ep0_in && w_length) { 1666 omap_writew(0, UDC_EP_NUM); 1667 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1668 } 1669 1670 /* gadget drivers see class/vendor specific requests, 1671 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, 1672 * and more 1673 */ 1674 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", 1675 u.r.bRequestType, u.r.bRequest, 1676 w_value, w_index, w_length); 1677 1678 #undef w_value 1679 #undef w_index 1680 #undef w_length 1681 1682 /* The gadget driver may return an error here, 1683 * causing an immediate protocol stall. 1684 * 1685 * Else it must issue a response, either queueing a 1686 * response buffer for the DATA stage, or halting ep0 1687 * (causing a protocol stall, not a real halt). A 1688 * zero length buffer means no DATA stage. 1689 * 1690 * It's fine to issue that response after the setup() 1691 * call returns, and this IRQ was handled. 1692 */ 1693 udc->ep0_setup = 1; 1694 spin_unlock(&udc->lock); 1695 status = udc->driver->setup(&udc->gadget, &u.r); 1696 spin_lock(&udc->lock); 1697 udc->ep0_setup = 0; 1698 } 1699 1700 if (status < 0) { 1701 do_stall: 1702 VDBG("req %02x.%02x protocol STALL; stat %d\n", 1703 u.r.bRequestType, u.r.bRequest, status); 1704 if (udc->ep0_set_config) { 1705 if (udc->ep0_reset_config) 1706 WARNING("error resetting config?\n"); 1707 else 1708 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1709 } 1710 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1711 udc->ep0_pending = 0; 1712 } 1713 } 1714 } 1715 1716 /*-------------------------------------------------------------------------*/ 1717 1718 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT) 1719 1720 static void devstate_irq(struct omap_udc *udc, u16 irq_src) 1721 { 1722 u16 devstat, change; 1723 1724 devstat = omap_readw(UDC_DEVSTAT); 1725 change = devstat ^ udc->devstat; 1726 udc->devstat = devstat; 1727 1728 if (change & (UDC_USB_RESET|UDC_ATT)) { 1729 udc_quiesce(udc); 1730 1731 if (change & UDC_ATT) { 1732 /* driver for any external transceiver will 1733 * have called omap_vbus_session() already 1734 */ 1735 if (devstat & UDC_ATT) { 1736 udc->gadget.speed = USB_SPEED_FULL; 1737 VDBG("connect\n"); 1738 if (IS_ERR_OR_NULL(udc->transceiver)) 1739 pullup_enable(udc); 1740 /* if (driver->connect) call it */ 1741 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1742 udc->gadget.speed = USB_SPEED_UNKNOWN; 1743 if (IS_ERR_OR_NULL(udc->transceiver)) 1744 pullup_disable(udc); 1745 DBG("disconnect, gadget %s\n", 1746 udc->driver->driver.name); 1747 if (udc->driver->disconnect) { 1748 spin_unlock(&udc->lock); 1749 udc->driver->disconnect(&udc->gadget); 1750 spin_lock(&udc->lock); 1751 } 1752 } 1753 change &= ~UDC_ATT; 1754 } 1755 1756 if (change & UDC_USB_RESET) { 1757 if (devstat & UDC_USB_RESET) { 1758 VDBG("RESET=1\n"); 1759 } else { 1760 udc->gadget.speed = USB_SPEED_FULL; 1761 INFO("USB reset done, gadget %s\n", 1762 udc->driver->driver.name); 1763 /* ep0 traffic is legal from now on */ 1764 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, 1765 UDC_IRQ_EN); 1766 } 1767 change &= ~UDC_USB_RESET; 1768 } 1769 } 1770 if (change & UDC_SUS) { 1771 if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1772 /* FIXME tell isp1301 to suspend/resume (?) */ 1773 if (devstat & UDC_SUS) { 1774 VDBG("suspend\n"); 1775 update_otg(udc); 1776 /* HNP could be under way already */ 1777 if (udc->gadget.speed == USB_SPEED_FULL 1778 && udc->driver->suspend) { 1779 spin_unlock(&udc->lock); 1780 udc->driver->suspend(&udc->gadget); 1781 spin_lock(&udc->lock); 1782 } 1783 if (!IS_ERR_OR_NULL(udc->transceiver)) 1784 usb_phy_set_suspend( 1785 udc->transceiver, 1); 1786 } else { 1787 VDBG("resume\n"); 1788 if (!IS_ERR_OR_NULL(udc->transceiver)) 1789 usb_phy_set_suspend( 1790 udc->transceiver, 0); 1791 if (udc->gadget.speed == USB_SPEED_FULL 1792 && udc->driver->resume) { 1793 spin_unlock(&udc->lock); 1794 udc->driver->resume(&udc->gadget); 1795 spin_lock(&udc->lock); 1796 } 1797 } 1798 } 1799 change &= ~UDC_SUS; 1800 } 1801 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) { 1802 update_otg(udc); 1803 change &= ~OTG_FLAGS; 1804 } 1805 1806 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD); 1807 if (change) 1808 VDBG("devstat %03x, ignore change %03x\n", 1809 devstat, change); 1810 1811 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); 1812 } 1813 1814 static irqreturn_t omap_udc_irq(int irq, void *_udc) 1815 { 1816 struct omap_udc *udc = _udc; 1817 u16 irq_src; 1818 irqreturn_t status = IRQ_NONE; 1819 unsigned long flags; 1820 1821 spin_lock_irqsave(&udc->lock, flags); 1822 irq_src = omap_readw(UDC_IRQ_SRC); 1823 1824 /* Device state change (usb ch9 stuff) */ 1825 if (irq_src & UDC_DS_CHG) { 1826 devstate_irq(_udc, irq_src); 1827 status = IRQ_HANDLED; 1828 irq_src &= ~UDC_DS_CHG; 1829 } 1830 1831 /* EP0 control transfers */ 1832 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) { 1833 ep0_irq(_udc, irq_src); 1834 status = IRQ_HANDLED; 1835 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX); 1836 } 1837 1838 /* DMA transfer completion */ 1839 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) { 1840 dma_irq(_udc, irq_src); 1841 status = IRQ_HANDLED; 1842 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); 1843 } 1844 1845 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); 1846 if (irq_src) 1847 DBG("udc_irq, unhandled %03x\n", irq_src); 1848 spin_unlock_irqrestore(&udc->lock, flags); 1849 1850 return status; 1851 } 1852 1853 /* workaround for seemingly-lost IRQs for RX ACKs... */ 1854 #define PIO_OUT_TIMEOUT (jiffies + HZ/3) 1855 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY))) 1856 1857 static void pio_out_timer(struct timer_list *t) 1858 { 1859 struct omap_ep *ep = timer_container_of(ep, t, timer); 1860 unsigned long flags; 1861 u16 stat_flg; 1862 1863 spin_lock_irqsave(&ep->udc->lock, flags); 1864 if (!list_empty(&ep->queue) && ep->ackwait) { 1865 use_ep(ep, UDC_EP_SEL); 1866 stat_flg = omap_readw(UDC_STAT_FLG); 1867 1868 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) 1869 || (ep->double_buf && HALF_FULL(stat_flg)))) { 1870 struct omap_req *req; 1871 1872 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg); 1873 req = container_of(ep->queue.next, 1874 struct omap_req, queue); 1875 (void) read_fifo(ep, req); 1876 omap_writew(ep->bEndpointAddress, UDC_EP_NUM); 1877 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1878 ep->ackwait = 1 + ep->double_buf; 1879 } else 1880 deselect_ep(); 1881 } 1882 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1883 spin_unlock_irqrestore(&ep->udc->lock, flags); 1884 } 1885 1886 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) 1887 { 1888 u16 epn_stat, irq_src; 1889 irqreturn_t status = IRQ_NONE; 1890 struct omap_ep *ep; 1891 int epnum; 1892 struct omap_udc *udc = _dev; 1893 struct omap_req *req; 1894 unsigned long flags; 1895 1896 spin_lock_irqsave(&udc->lock, flags); 1897 epn_stat = omap_readw(UDC_EPN_STAT); 1898 irq_src = omap_readw(UDC_IRQ_SRC); 1899 1900 /* handle OUT first, to avoid some wasteful NAKs */ 1901 if (irq_src & UDC_EPN_RX) { 1902 epnum = (epn_stat >> 8) & 0x0f; 1903 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); 1904 status = IRQ_HANDLED; 1905 ep = &udc->ep[epnum]; 1906 ep->irqs++; 1907 1908 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); 1909 ep->fnf = 0; 1910 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { 1911 ep->ackwait--; 1912 if (!list_empty(&ep->queue)) { 1913 int stat; 1914 req = container_of(ep->queue.next, 1915 struct omap_req, queue); 1916 stat = read_fifo(ep, req); 1917 if (!ep->double_buf) 1918 ep->fnf = 1; 1919 } 1920 } 1921 /* min 6 clock delay before clearing EP_SEL ... */ 1922 epn_stat = omap_readw(UDC_EPN_STAT); 1923 epn_stat = omap_readw(UDC_EPN_STAT); 1924 omap_writew(epnum, UDC_EP_NUM); 1925 1926 /* enabling fifo _after_ clearing ACK, contrary to docs, 1927 * reduces lossage; timer still needed though (sigh). 1928 */ 1929 if (ep->fnf) { 1930 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1931 ep->ackwait = 1 + ep->double_buf; 1932 } 1933 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1934 } 1935 1936 /* then IN transfers */ 1937 else if (irq_src & UDC_EPN_TX) { 1938 epnum = epn_stat & 0x0f; 1939 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); 1940 status = IRQ_HANDLED; 1941 ep = &udc->ep[16 + epnum]; 1942 ep->irqs++; 1943 1944 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); 1945 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { 1946 ep->ackwait = 0; 1947 if (!list_empty(&ep->queue)) { 1948 req = container_of(ep->queue.next, 1949 struct omap_req, queue); 1950 (void) write_fifo(ep, req); 1951 } 1952 } 1953 /* min 6 clock delay before clearing EP_SEL ... */ 1954 epn_stat = omap_readw(UDC_EPN_STAT); 1955 epn_stat = omap_readw(UDC_EPN_STAT); 1956 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); 1957 /* then 6 clocks before it'd tx */ 1958 } 1959 1960 spin_unlock_irqrestore(&udc->lock, flags); 1961 return status; 1962 } 1963 1964 #ifdef USE_ISO 1965 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) 1966 { 1967 struct omap_udc *udc = _dev; 1968 struct omap_ep *ep; 1969 int pending = 0; 1970 unsigned long flags; 1971 1972 spin_lock_irqsave(&udc->lock, flags); 1973 1974 /* handle all non-DMA ISO transfers */ 1975 list_for_each_entry(ep, &udc->iso, iso) { 1976 u16 stat; 1977 struct omap_req *req; 1978 1979 if (ep->has_dma || list_empty(&ep->queue)) 1980 continue; 1981 req = list_entry(ep->queue.next, struct omap_req, queue); 1982 1983 use_ep(ep, UDC_EP_SEL); 1984 stat = omap_readw(UDC_STAT_FLG); 1985 1986 /* NOTE: like the other controller drivers, this isn't 1987 * currently reporting lost or damaged frames. 1988 */ 1989 if (ep->bEndpointAddress & USB_DIR_IN) { 1990 if (stat & UDC_MISS_IN) 1991 /* done(ep, req, -EPROTO) */; 1992 else 1993 write_fifo(ep, req); 1994 } else { 1995 int status = 0; 1996 1997 if (stat & UDC_NO_RXPACKET) 1998 status = -EREMOTEIO; 1999 else if (stat & UDC_ISO_ERR) 2000 status = -EILSEQ; 2001 else if (stat & UDC_DATA_FLUSH) 2002 status = -ENOSR; 2003 2004 if (status) 2005 /* done(ep, req, status) */; 2006 else 2007 read_fifo(ep, req); 2008 } 2009 deselect_ep(); 2010 /* 6 wait states before next EP */ 2011 2012 ep->irqs++; 2013 if (!list_empty(&ep->queue)) 2014 pending = 1; 2015 } 2016 if (!pending) { 2017 u16 w; 2018 2019 w = omap_readw(UDC_IRQ_EN); 2020 w &= ~UDC_SOF_IE; 2021 omap_writew(w, UDC_IRQ_EN); 2022 } 2023 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); 2024 2025 spin_unlock_irqrestore(&udc->lock, flags); 2026 return IRQ_HANDLED; 2027 } 2028 #endif 2029 2030 /*-------------------------------------------------------------------------*/ 2031 2032 static inline int machine_without_vbus_sense(void) 2033 { 2034 return machine_is_omap_osk() || machine_is_omap_palmte() || 2035 machine_is_sx1(); 2036 } 2037 2038 static int omap_udc_start(struct usb_gadget *g, 2039 struct usb_gadget_driver *driver) 2040 { 2041 int status; 2042 struct omap_ep *ep; 2043 unsigned long flags; 2044 2045 2046 spin_lock_irqsave(&udc->lock, flags); 2047 /* reset state */ 2048 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2049 ep->irqs = 0; 2050 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 2051 continue; 2052 use_ep(ep, 0); 2053 omap_writew(UDC_SET_HALT, UDC_CTRL); 2054 } 2055 udc->ep0_pending = 0; 2056 udc->ep[0].irqs = 0; 2057 udc->softconnect = 1; 2058 2059 /* hook up the driver */ 2060 udc->driver = driver; 2061 spin_unlock_irqrestore(&udc->lock, flags); 2062 2063 if (udc->dc_clk != NULL) 2064 omap_udc_enable_clock(1); 2065 2066 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); 2067 2068 /* connect to bus through transceiver */ 2069 if (!IS_ERR_OR_NULL(udc->transceiver)) { 2070 status = otg_set_peripheral(udc->transceiver->otg, 2071 &udc->gadget); 2072 if (status < 0) { 2073 ERR("can't bind to transceiver\n"); 2074 udc->driver = NULL; 2075 goto done; 2076 } 2077 } else { 2078 status = 0; 2079 if (can_pullup(udc)) 2080 pullup_enable(udc); 2081 else 2082 pullup_disable(udc); 2083 } 2084 2085 /* boards that don't have VBUS sensing can't autogate 48MHz; 2086 * can't enter deep sleep while a gadget driver is active. 2087 */ 2088 if (machine_without_vbus_sense()) 2089 omap_vbus_session(&udc->gadget, 1); 2090 2091 done: 2092 if (udc->dc_clk != NULL) 2093 omap_udc_enable_clock(0); 2094 2095 return status; 2096 } 2097 2098 static int omap_udc_stop(struct usb_gadget *g) 2099 { 2100 unsigned long flags; 2101 2102 if (udc->dc_clk != NULL) 2103 omap_udc_enable_clock(1); 2104 2105 if (machine_without_vbus_sense()) 2106 omap_vbus_session(&udc->gadget, 0); 2107 2108 if (!IS_ERR_OR_NULL(udc->transceiver)) 2109 (void) otg_set_peripheral(udc->transceiver->otg, NULL); 2110 else 2111 pullup_disable(udc); 2112 2113 spin_lock_irqsave(&udc->lock, flags); 2114 udc_quiesce(udc); 2115 spin_unlock_irqrestore(&udc->lock, flags); 2116 2117 udc->driver = NULL; 2118 2119 if (udc->dc_clk != NULL) 2120 omap_udc_enable_clock(0); 2121 2122 return 0; 2123 } 2124 2125 /*-------------------------------------------------------------------------*/ 2126 2127 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2128 2129 #include <linux/seq_file.h> 2130 2131 static const char proc_filename[] = "driver/udc"; 2132 2133 #define FOURBITS "%s%s%s%s" 2134 #define EIGHTBITS "%s%s%s%s%s%s%s%s" 2135 2136 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) 2137 { 2138 u16 stat_flg; 2139 struct omap_req *req; 2140 char buf[20]; 2141 2142 use_ep(ep, 0); 2143 2144 if (use_dma && ep->has_dma) 2145 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ", 2146 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 2147 ep->dma_channel - 1, ep->lch); 2148 else 2149 buf[0] = 0; 2150 2151 stat_flg = omap_readw(UDC_STAT_FLG); 2152 seq_printf(s, 2153 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", 2154 ep->name, buf, 2155 ep->double_buf ? "dbuf " : "", 2156 ({ char *s; 2157 switch (ep->ackwait) { 2158 case 0: 2159 s = ""; 2160 break; 2161 case 1: 2162 s = "(ackw) "; 2163 break; 2164 case 2: 2165 s = "(ackw2) "; 2166 break; 2167 default: 2168 s = "(?) "; 2169 break; 2170 } s; }), 2171 ep->irqs, stat_flg, 2172 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "", 2173 (stat_flg & UDC_MISS_IN) ? "miss_in " : "", 2174 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "", 2175 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "", 2176 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "", 2177 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "", 2178 (stat_flg & UDC_EP_HALTED) ? "HALT " : "", 2179 (stat_flg & UDC_STALL) ? "STALL " : "", 2180 (stat_flg & UDC_NAK) ? "NAK " : "", 2181 (stat_flg & UDC_ACK) ? "ACK " : "", 2182 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "", 2183 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "", 2184 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : ""); 2185 2186 if (list_empty(&ep->queue)) 2187 seq_printf(s, "\t(queue empty)\n"); 2188 else 2189 list_for_each_entry(req, &ep->queue, queue) { 2190 unsigned length = req->req.actual; 2191 2192 if (use_dma && buf[0]) { 2193 length += ((ep->bEndpointAddress & USB_DIR_IN) 2194 ? dma_src_len : dma_dest_len) 2195 (ep, req->req.dma + length); 2196 buf[0] = 0; 2197 } 2198 seq_printf(s, "\treq %p len %d/%d buf %p\n", 2199 &req->req, length, 2200 req->req.length, req->req.buf); 2201 } 2202 } 2203 2204 static char *trx_mode(unsigned m, int enabled) 2205 { 2206 switch (m) { 2207 case 0: 2208 return enabled ? "*6wire" : "unused"; 2209 case 1: 2210 return "4wire"; 2211 case 2: 2212 return "3wire"; 2213 case 3: 2214 return "6wire"; 2215 default: 2216 return "unknown"; 2217 } 2218 } 2219 2220 static int proc_otg_show(struct seq_file *s) 2221 { 2222 u32 tmp; 2223 u32 trans = 0; 2224 char *ctrl_name = "(UNKNOWN)"; 2225 2226 tmp = omap_readl(OTG_REV); 2227 ctrl_name = "transceiver_ctrl"; 2228 trans = omap_readw(USB_TRANSCEIVER_CTRL); 2229 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", 2230 tmp >> 4, tmp & 0xf, ctrl_name, trans); 2231 tmp = omap_readw(OTG_SYSCON_1); 2232 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," 2233 FOURBITS "\n", tmp, 2234 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), 2235 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), 2236 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710()) 2237 ? "internal" 2238 : trx_mode(USB0_TRX_MODE(tmp), 1), 2239 (tmp & OTG_IDLE_EN) ? " !otg" : "", 2240 (tmp & HST_IDLE_EN) ? " !host" : "", 2241 (tmp & DEV_IDLE_EN) ? " !dev" : "", 2242 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); 2243 tmp = omap_readl(OTG_SYSCON_2); 2244 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS 2245 " b_ase_brst=%d hmc=%d\n", tmp, 2246 (tmp & OTG_EN) ? " otg_en" : "", 2247 (tmp & USBX_SYNCHRO) ? " synchro" : "", 2248 /* much more SRP stuff */ 2249 (tmp & SRP_DATA) ? " srp_data" : "", 2250 (tmp & SRP_VBUS) ? " srp_vbus" : "", 2251 (tmp & OTG_PADEN) ? " otg_paden" : "", 2252 (tmp & HMC_PADEN) ? " hmc_paden" : "", 2253 (tmp & UHOST_EN) ? " uhost_en" : "", 2254 (tmp & HMC_TLLSPEED) ? " tllspeed" : "", 2255 (tmp & HMC_TLLATTACH) ? " tllattach" : "", 2256 B_ASE_BRST(tmp), 2257 OTG_HMC(tmp)); 2258 tmp = omap_readl(OTG_CTRL); 2259 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, 2260 (tmp & OTG_ASESSVLD) ? " asess" : "", 2261 (tmp & OTG_BSESSEND) ? " bsess_end" : "", 2262 (tmp & OTG_BSESSVLD) ? " bsess" : "", 2263 (tmp & OTG_VBUSVLD) ? " vbus" : "", 2264 (tmp & OTG_ID) ? " id" : "", 2265 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST", 2266 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "", 2267 (tmp & OTG_A_BUSREQ) ? " a_bus" : "", 2268 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "", 2269 (tmp & OTG_B_BUSREQ) ? " b_bus" : "", 2270 (tmp & OTG_BUSDROP) ? " busdrop" : "", 2271 (tmp & OTG_PULLDOWN) ? " down" : "", 2272 (tmp & OTG_PULLUP) ? " up" : "", 2273 (tmp & OTG_DRV_VBUS) ? " drv" : "", 2274 (tmp & OTG_PD_VBUS) ? " pd_vb" : "", 2275 (tmp & OTG_PU_VBUS) ? " pu_vb" : "", 2276 (tmp & OTG_PU_ID) ? " pu_id" : "" 2277 ); 2278 tmp = omap_readw(OTG_IRQ_EN); 2279 seq_printf(s, "otg_irq_en %04x" "\n", tmp); 2280 tmp = omap_readw(OTG_IRQ_SRC); 2281 seq_printf(s, "otg_irq_src %04x" "\n", tmp); 2282 tmp = omap_readw(OTG_OUTCTRL); 2283 seq_printf(s, "otg_outctrl %04x" "\n", tmp); 2284 tmp = omap_readw(OTG_TEST); 2285 seq_printf(s, "otg_test %04x" "\n", tmp); 2286 return 0; 2287 } 2288 2289 static int proc_udc_show(struct seq_file *s, void *_) 2290 { 2291 u32 tmp; 2292 struct omap_ep *ep; 2293 unsigned long flags; 2294 2295 spin_lock_irqsave(&udc->lock, flags); 2296 2297 seq_printf(s, "OMAP UDC driver, version: " DRIVER_VERSION 2298 #ifdef USE_ISO 2299 " (iso)" 2300 #endif 2301 "%s\n", use_dma ? " (dma)" : ""); 2302 2303 tmp = omap_readw(UDC_REV) & 0xff; 2304 seq_printf(s, 2305 "UDC rev %d.%d, fifo mode %d, gadget %s\n" 2306 "hmc %d, transceiver %s\n", 2307 tmp >> 4, tmp & 0xf, 2308 fifo_mode, 2309 udc->driver ? udc->driver->driver.name : "(none)", 2310 HMC, 2311 udc->transceiver 2312 ? udc->transceiver->label 2313 : (cpu_is_omap1710() 2314 ? "external" : "(none)")); 2315 seq_printf(s, "ULPD control %04x req %04x status %04x\n", 2316 omap_readw(ULPD_CLOCK_CTRL), 2317 omap_readw(ULPD_SOFT_REQ), 2318 omap_readw(ULPD_STATUS_REQ)); 2319 2320 /* OTG controller registers */ 2321 if (!cpu_is_omap15xx()) 2322 proc_otg_show(s); 2323 2324 tmp = omap_readw(UDC_SYSCON1); 2325 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, 2326 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", 2327 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", 2328 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "", 2329 (tmp & UDC_NAK_EN) ? " nak" : "", 2330 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "", 2331 (tmp & UDC_SELF_PWR) ? " self_pwr" : "", 2332 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "", 2333 (tmp & UDC_PULLUP_EN) ? " PULLUP" : ""); 2334 /* syscon2 is write-only */ 2335 2336 /* UDC controller registers */ 2337 if (!(tmp & UDC_PULLUP_EN)) { 2338 seq_printf(s, "(suspended)\n"); 2339 spin_unlock_irqrestore(&udc->lock, flags); 2340 return 0; 2341 } 2342 2343 tmp = omap_readw(UDC_DEVSTAT); 2344 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, 2345 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", 2346 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", 2347 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "", 2348 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "", 2349 (tmp & UDC_USB_RESET) ? " usb_reset" : "", 2350 (tmp & UDC_SUS) ? " SUS" : "", 2351 (tmp & UDC_CFG) ? " CFG" : "", 2352 (tmp & UDC_ADD) ? " ADD" : "", 2353 (tmp & UDC_DEF) ? " DEF" : "", 2354 (tmp & UDC_ATT) ? " ATT" : ""); 2355 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); 2356 tmp = omap_readw(UDC_IRQ_EN); 2357 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, 2358 (tmp & UDC_SOF_IE) ? " sof" : "", 2359 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", 2360 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", 2361 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", 2362 (tmp & UDC_EP0_IE) ? " ep0" : ""); 2363 tmp = omap_readw(UDC_IRQ_SRC); 2364 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, 2365 (tmp & UDC_TXN_DONE) ? " txn_done" : "", 2366 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", 2367 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", 2368 (tmp & UDC_IRQ_SOF) ? " sof" : "", 2369 (tmp & UDC_EPN_RX) ? " epn_rx" : "", 2370 (tmp & UDC_EPN_TX) ? " epn_tx" : "", 2371 (tmp & UDC_DS_CHG) ? " ds_chg" : "", 2372 (tmp & UDC_SETUP) ? " setup" : "", 2373 (tmp & UDC_EP0_RX) ? " ep0out" : "", 2374 (tmp & UDC_EP0_TX) ? " ep0in" : ""); 2375 if (use_dma) { 2376 unsigned i; 2377 2378 tmp = omap_readw(UDC_DMA_IRQ_EN); 2379 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, 2380 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", 2381 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", 2382 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "", 2383 2384 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "", 2385 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "", 2386 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "", 2387 2388 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "", 2389 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", 2390 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); 2391 2392 tmp = omap_readw(UDC_RXDMA_CFG); 2393 seq_printf(s, "rxdma_cfg %04x\n", tmp); 2394 if (tmp) { 2395 for (i = 0; i < 3; i++) { 2396 if ((tmp & (0x0f << (i * 4))) == 0) 2397 continue; 2398 seq_printf(s, "rxdma[%d] %04x\n", i, 2399 omap_readw(UDC_RXDMA(i + 1))); 2400 } 2401 } 2402 tmp = omap_readw(UDC_TXDMA_CFG); 2403 seq_printf(s, "txdma_cfg %04x\n", tmp); 2404 if (tmp) { 2405 for (i = 0; i < 3; i++) { 2406 if (!(tmp & (0x0f << (i * 4)))) 2407 continue; 2408 seq_printf(s, "txdma[%d] %04x\n", i, 2409 omap_readw(UDC_TXDMA(i + 1))); 2410 } 2411 } 2412 } 2413 2414 tmp = omap_readw(UDC_DEVSTAT); 2415 if (tmp & UDC_ATT) { 2416 proc_ep_show(s, &udc->ep[0]); 2417 if (tmp & UDC_ADD) { 2418 list_for_each_entry(ep, &udc->gadget.ep_list, 2419 ep.ep_list) { 2420 if (ep->ep.desc) 2421 proc_ep_show(s, ep); 2422 } 2423 } 2424 } 2425 spin_unlock_irqrestore(&udc->lock, flags); 2426 return 0; 2427 } 2428 2429 static void create_proc_file(void) 2430 { 2431 proc_create_single(proc_filename, 0, NULL, proc_udc_show); 2432 } 2433 2434 static void remove_proc_file(void) 2435 { 2436 remove_proc_entry(proc_filename, NULL); 2437 } 2438 2439 #else 2440 2441 static inline void create_proc_file(void) {} 2442 static inline void remove_proc_file(void) {} 2443 2444 #endif 2445 2446 /*-------------------------------------------------------------------------*/ 2447 2448 /* Before this controller can enumerate, we need to pick an endpoint 2449 * configuration, or "fifo_mode" That involves allocating 2KB of packet 2450 * buffer space among the endpoints we'll be operating. 2451 * 2452 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when 2453 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that 2454 * capability yet though. 2455 */ 2456 static unsigned 2457 omap_ep_setup(char *name, u8 addr, u8 type, 2458 unsigned buf, unsigned maxp, int dbuf) 2459 { 2460 struct omap_ep *ep; 2461 u16 epn_rxtx = 0; 2462 2463 /* OUT endpoints first, then IN */ 2464 ep = &udc->ep[addr & 0xf]; 2465 if (addr & USB_DIR_IN) 2466 ep += 16; 2467 2468 /* in case of ep init table bugs */ 2469 BUG_ON(ep->name[0]); 2470 2471 /* chip setup ... bit values are same for IN, OUT */ 2472 if (type == USB_ENDPOINT_XFER_ISOC) { 2473 switch (maxp) { 2474 case 8: 2475 epn_rxtx = 0 << 12; 2476 break; 2477 case 16: 2478 epn_rxtx = 1 << 12; 2479 break; 2480 case 32: 2481 epn_rxtx = 2 << 12; 2482 break; 2483 case 64: 2484 epn_rxtx = 3 << 12; 2485 break; 2486 case 128: 2487 epn_rxtx = 4 << 12; 2488 break; 2489 case 256: 2490 epn_rxtx = 5 << 12; 2491 break; 2492 case 512: 2493 epn_rxtx = 6 << 12; 2494 break; 2495 default: 2496 BUG(); 2497 } 2498 epn_rxtx |= UDC_EPN_RX_ISO; 2499 dbuf = 1; 2500 } else { 2501 /* double-buffering "not supported" on 15xx, 2502 * and ignored for PIO-IN on newer chips 2503 * (for more reliable behavior) 2504 */ 2505 if (!use_dma || cpu_is_omap15xx()) 2506 dbuf = 0; 2507 2508 switch (maxp) { 2509 case 8: 2510 epn_rxtx = 0 << 12; 2511 break; 2512 case 16: 2513 epn_rxtx = 1 << 12; 2514 break; 2515 case 32: 2516 epn_rxtx = 2 << 12; 2517 break; 2518 case 64: 2519 epn_rxtx = 3 << 12; 2520 break; 2521 default: 2522 BUG(); 2523 } 2524 if (dbuf && addr) 2525 epn_rxtx |= UDC_EPN_RX_DB; 2526 timer_setup(&ep->timer, pio_out_timer, 0); 2527 } 2528 if (addr) 2529 epn_rxtx |= UDC_EPN_RX_VALID; 2530 BUG_ON(buf & 0x07); 2531 epn_rxtx |= buf >> 3; 2532 2533 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n", 2534 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); 2535 2536 if (addr & USB_DIR_IN) 2537 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); 2538 else 2539 omap_writew(epn_rxtx, UDC_EP_RX(addr)); 2540 2541 /* next endpoint's buffer starts after this one's */ 2542 buf += maxp; 2543 if (dbuf) 2544 buf += maxp; 2545 BUG_ON(buf > 2048); 2546 2547 /* set up driver data structures */ 2548 BUG_ON(strlen(name) >= sizeof ep->name); 2549 strscpy(ep->name, name, sizeof(ep->name)); 2550 INIT_LIST_HEAD(&ep->queue); 2551 INIT_LIST_HEAD(&ep->iso); 2552 ep->bEndpointAddress = addr; 2553 ep->bmAttributes = type; 2554 ep->double_buf = dbuf; 2555 ep->udc = udc; 2556 2557 switch (type) { 2558 case USB_ENDPOINT_XFER_CONTROL: 2559 ep->ep.caps.type_control = true; 2560 ep->ep.caps.dir_in = true; 2561 ep->ep.caps.dir_out = true; 2562 break; 2563 case USB_ENDPOINT_XFER_ISOC: 2564 ep->ep.caps.type_iso = true; 2565 break; 2566 case USB_ENDPOINT_XFER_BULK: 2567 ep->ep.caps.type_bulk = true; 2568 break; 2569 case USB_ENDPOINT_XFER_INT: 2570 ep->ep.caps.type_int = true; 2571 break; 2572 } 2573 2574 if (addr & USB_DIR_IN) 2575 ep->ep.caps.dir_in = true; 2576 else 2577 ep->ep.caps.dir_out = true; 2578 2579 ep->ep.name = ep->name; 2580 ep->ep.ops = &omap_ep_ops; 2581 ep->maxpacket = maxp; 2582 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); 2583 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 2584 2585 return buf; 2586 } 2587 2588 static void omap_udc_release(struct device *dev) 2589 { 2590 pullup_disable(udc); 2591 if (!IS_ERR_OR_NULL(udc->transceiver)) { 2592 usb_put_phy(udc->transceiver); 2593 udc->transceiver = NULL; 2594 } 2595 omap_writew(0, UDC_SYSCON1); 2596 remove_proc_file(); 2597 if (udc->dc_clk) { 2598 if (udc->clk_requested) 2599 omap_udc_enable_clock(0); 2600 clk_unprepare(udc->hhc_clk); 2601 clk_unprepare(udc->dc_clk); 2602 clk_put(udc->hhc_clk); 2603 clk_put(udc->dc_clk); 2604 } 2605 if (udc->done) 2606 complete(udc->done); 2607 kfree(udc); 2608 } 2609 2610 static int 2611 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv) 2612 { 2613 unsigned tmp, buf; 2614 2615 /* abolish any previous hardware state */ 2616 omap_writew(0, UDC_SYSCON1); 2617 omap_writew(0, UDC_IRQ_EN); 2618 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); 2619 omap_writew(0, UDC_DMA_IRQ_EN); 2620 omap_writew(0, UDC_RXDMA_CFG); 2621 omap_writew(0, UDC_TXDMA_CFG); 2622 2623 /* UDC_PULLUP_EN gates the chip clock */ 2624 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */ 2625 2626 udc = kzalloc_obj(*udc); 2627 if (!udc) 2628 return -ENOMEM; 2629 2630 spin_lock_init(&udc->lock); 2631 2632 udc->gadget.ops = &omap_gadget_ops; 2633 udc->gadget.ep0 = &udc->ep[0].ep; 2634 INIT_LIST_HEAD(&udc->gadget.ep_list); 2635 INIT_LIST_HEAD(&udc->iso); 2636 udc->gadget.speed = USB_SPEED_UNKNOWN; 2637 udc->gadget.max_speed = USB_SPEED_FULL; 2638 udc->gadget.name = driver_name; 2639 udc->gadget.quirk_ep_out_aligned_size = 1; 2640 udc->transceiver = xceiv; 2641 2642 /* ep0 is special; put it right after the SETUP buffer */ 2643 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL, 2644 8 /* after SETUP */, 64 /* maxpacket */, 0); 2645 list_del_init(&udc->ep[0].ep.ep_list); 2646 2647 /* initially disable all non-ep0 endpoints */ 2648 for (tmp = 1; tmp < 15; tmp++) { 2649 omap_writew(0, UDC_EP_RX(tmp)); 2650 omap_writew(0, UDC_EP_TX(tmp)); 2651 } 2652 2653 #define OMAP_BULK_EP(name, addr) \ 2654 buf = omap_ep_setup(name "-bulk", addr, \ 2655 USB_ENDPOINT_XFER_BULK, buf, 64, 1); 2656 #define OMAP_INT_EP(name, addr, maxp) \ 2657 buf = omap_ep_setup(name "-int", addr, \ 2658 USB_ENDPOINT_XFER_INT, buf, maxp, 0); 2659 #define OMAP_ISO_EP(name, addr, maxp) \ 2660 buf = omap_ep_setup(name "-iso", addr, \ 2661 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1); 2662 2663 switch (fifo_mode) { 2664 case 0: 2665 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2666 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2667 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2668 break; 2669 case 1: 2670 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2671 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2672 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2673 2674 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); 2675 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); 2676 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16); 2677 2678 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); 2679 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2680 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16); 2681 2682 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2683 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); 2684 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16); 2685 2686 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); 2687 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2688 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16); 2689 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16); 2690 2691 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); 2692 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); 2693 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16); 2694 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16); 2695 2696 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15); 2697 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15); 2698 2699 break; 2700 2701 #ifdef USE_ISO 2702 case 2: /* mixed iso/bulk */ 2703 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256); 2704 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256); 2705 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128); 2706 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128); 2707 2708 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16); 2709 2710 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2711 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2712 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16); 2713 break; 2714 case 3: /* mixed bulk/iso */ 2715 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2716 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2717 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2718 2719 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4); 2720 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2721 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16); 2722 2723 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256); 2724 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256); 2725 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2726 break; 2727 #endif 2728 2729 /* add more modes as needed */ 2730 2731 default: 2732 ERR("unsupported fifo_mode #%d\n", fifo_mode); 2733 return -ENODEV; 2734 } 2735 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); 2736 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); 2737 return 0; 2738 } 2739 2740 static int omap_udc_probe(struct platform_device *pdev) 2741 { 2742 int status = -ENODEV; 2743 int hmc; 2744 struct usb_phy *xceiv = NULL; 2745 const char *type = NULL; 2746 struct omap_usb_config *config = dev_get_platdata(&pdev->dev); 2747 struct clk *dc_clk = NULL; 2748 struct clk *hhc_clk = NULL; 2749 2750 /* NOTE: "knows" the order of the resources! */ 2751 if (!request_mem_region(pdev->resource[0].start, 2752 resource_size(&pdev->resource[0]), 2753 driver_name)) { 2754 DBG("request_mem_region failed\n"); 2755 return -EBUSY; 2756 } 2757 2758 if (cpu_is_omap16xx()) { 2759 dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); 2760 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck"); 2761 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2762 /* can't use omap_udc_enable_clock yet */ 2763 clk_prepare_enable(dc_clk); 2764 clk_prepare_enable(hhc_clk); 2765 udelay(100); 2766 } 2767 2768 INFO("OMAP UDC rev %d.%d%s\n", 2769 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, 2770 config->otg ? ", Mini-AB" : ""); 2771 2772 /* use the mode given to us by board init code */ 2773 if (cpu_is_omap15xx()) { 2774 hmc = HMC_1510; 2775 type = "(unknown)"; 2776 2777 if (machine_without_vbus_sense()) { 2778 /* just set up software VBUS detect, and then 2779 * later rig it so we always report VBUS. 2780 * FIXME without really sensing VBUS, we can't 2781 * know when to turn PULLUP_EN on/off; and that 2782 * means we always "need" the 48MHz clock. 2783 */ 2784 u32 tmp = omap_readl(FUNC_MUX_CTRL_0); 2785 tmp &= ~VBUS_CTRL_1510; 2786 omap_writel(tmp, FUNC_MUX_CTRL_0); 2787 tmp |= VBUS_MODE_1510; 2788 tmp &= ~VBUS_CTRL_1510; 2789 omap_writel(tmp, FUNC_MUX_CTRL_0); 2790 } 2791 } else { 2792 /* The transceiver may package some GPIO logic or handle 2793 * loopback and/or transceiverless setup; if we find one, 2794 * use it. Except for OTG, we don't _need_ to talk to one; 2795 * but not having one probably means no VBUS detection. 2796 */ 2797 xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 2798 if (!IS_ERR_OR_NULL(xceiv)) 2799 type = xceiv->label; 2800 else if (config->otg) { 2801 DBG("OTG requires external transceiver!\n"); 2802 goto cleanup0; 2803 } 2804 2805 hmc = HMC_1610; 2806 2807 switch (hmc) { 2808 case 0: /* POWERUP DEFAULT == 0 */ 2809 case 4: 2810 case 12: 2811 case 20: 2812 if (!cpu_is_omap1710()) { 2813 type = "integrated"; 2814 break; 2815 } 2816 fallthrough; 2817 case 3: 2818 case 11: 2819 case 16: 2820 case 19: 2821 case 25: 2822 if (IS_ERR_OR_NULL(xceiv)) { 2823 DBG("external transceiver not registered!\n"); 2824 type = "unknown"; 2825 } 2826 break; 2827 case 21: /* internal loopback */ 2828 type = "loopback"; 2829 break; 2830 case 14: /* transceiverless */ 2831 if (cpu_is_omap1710()) 2832 goto bad_on_1710; 2833 fallthrough; 2834 case 13: 2835 case 15: 2836 type = "no"; 2837 break; 2838 2839 default: 2840 bad_on_1710: 2841 ERR("unrecognized UDC HMC mode %d\n", hmc); 2842 goto cleanup0; 2843 } 2844 } 2845 2846 INFO("hmc mode %d, %s transceiver\n", hmc, type); 2847 2848 /* a "gadget" abstracts/virtualizes the controller */ 2849 status = omap_udc_setup(pdev, xceiv); 2850 if (status) 2851 goto cleanup0; 2852 2853 xceiv = NULL; 2854 /* "udc" is now valid */ 2855 pullup_disable(udc); 2856 #if IS_ENABLED(CONFIG_USB_OHCI_HCD) 2857 udc->gadget.is_otg = (config->otg != 0); 2858 #endif 2859 2860 /* starting with omap1710 es2.0, clear toggle is a separate bit */ 2861 if (omap_readw(UDC_REV) >= 0x61) 2862 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; 2863 else 2864 udc->clr_halt = UDC_RESET_EP; 2865 2866 /* USB general purpose IRQ: ep0, state changes, dma, etc */ 2867 status = devm_request_irq(&pdev->dev, pdev->resource[1].start, 2868 omap_udc_irq, 0, driver_name, udc); 2869 if (status != 0) { 2870 ERR("can't get irq %d, err %d\n", 2871 (int) pdev->resource[1].start, status); 2872 goto cleanup1; 2873 } 2874 2875 /* USB "non-iso" IRQ (PIO for all but ep0) */ 2876 status = devm_request_irq(&pdev->dev, pdev->resource[2].start, 2877 omap_udc_pio_irq, 0, "omap_udc pio", udc); 2878 if (status != 0) { 2879 ERR("can't get irq %d, err %d\n", 2880 (int) pdev->resource[2].start, status); 2881 goto cleanup1; 2882 } 2883 #ifdef USE_ISO 2884 status = devm_request_irq(&pdev->dev, pdev->resource[3].start, 2885 omap_udc_iso_irq, 0, "omap_udc iso", udc); 2886 if (status != 0) { 2887 ERR("can't get irq %d, err %d\n", 2888 (int) pdev->resource[3].start, status); 2889 goto cleanup1; 2890 } 2891 #endif 2892 if (cpu_is_omap16xx()) { 2893 udc->dc_clk = dc_clk; 2894 udc->hhc_clk = hhc_clk; 2895 clk_disable(hhc_clk); 2896 clk_disable(dc_clk); 2897 } 2898 2899 create_proc_file(); 2900 return usb_add_gadget_udc_release(&pdev->dev, &udc->gadget, 2901 omap_udc_release); 2902 2903 cleanup1: 2904 kfree(udc); 2905 udc = NULL; 2906 2907 cleanup0: 2908 if (!IS_ERR_OR_NULL(xceiv)) 2909 usb_put_phy(xceiv); 2910 2911 if (cpu_is_omap16xx()) { 2912 clk_disable_unprepare(hhc_clk); 2913 clk_disable_unprepare(dc_clk); 2914 clk_put(hhc_clk); 2915 clk_put(dc_clk); 2916 } 2917 2918 release_mem_region(pdev->resource[0].start, 2919 resource_size(&pdev->resource[0])); 2920 2921 return status; 2922 } 2923 2924 static void omap_udc_remove(struct platform_device *pdev) 2925 { 2926 DECLARE_COMPLETION_ONSTACK(done); 2927 2928 udc->done = &done; 2929 2930 usb_del_gadget_udc(&udc->gadget); 2931 2932 wait_for_completion(&done); 2933 2934 release_mem_region(pdev->resource[0].start, 2935 resource_size(&pdev->resource[0])); 2936 } 2937 2938 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the 2939 * system is forced into deep sleep 2940 * 2941 * REVISIT we should probably reject suspend requests when there's a host 2942 * session active, rather than disconnecting, at least on boards that can 2943 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to 2944 * make host resumes and VBUS detection trigger OMAP wakeup events; that 2945 * may involve talking to an external transceiver (e.g. isp1301). 2946 */ 2947 2948 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) 2949 { 2950 u32 devstat; 2951 2952 devstat = omap_readw(UDC_DEVSTAT); 2953 2954 /* we're requesting 48 MHz clock if the pullup is enabled 2955 * (== we're attached to the host) and we're not suspended, 2956 * which would prevent entry to deep sleep... 2957 */ 2958 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) { 2959 WARNING("session active; suspend requires disconnect\n"); 2960 omap_pullup(&udc->gadget, 0); 2961 } 2962 2963 return 0; 2964 } 2965 2966 static int omap_udc_resume(struct platform_device *dev) 2967 { 2968 DBG("resume + wakeup/SRP\n"); 2969 omap_pullup(&udc->gadget, 1); 2970 2971 /* maybe the host would enumerate us if we nudged it */ 2972 msleep(100); 2973 return omap_wakeup(&udc->gadget); 2974 } 2975 2976 /*-------------------------------------------------------------------------*/ 2977 2978 static struct platform_driver udc_driver = { 2979 .probe = omap_udc_probe, 2980 .remove = omap_udc_remove, 2981 .suspend = omap_udc_suspend, 2982 .resume = omap_udc_resume, 2983 .driver = { 2984 .name = driver_name, 2985 }, 2986 }; 2987 2988 module_platform_driver(udc_driver); 2989 2990 MODULE_DESCRIPTION("OMAP UDC driver"); 2991 MODULE_LICENSE("GPL"); 2992 MODULE_ALIAS("platform:omap_udc"); 2993