1 /* 2 * USB Gadget driver for LPC32xx 3 * 4 * Authors: 5 * Kevin Wells <kevin.wells@nxp.com> 6 * Mike James 7 * Roland Stigge <stigge@antcom.de> 8 * 9 * Copyright (C) 2006 Philips Semiconductors 10 * Copyright (C) 2009 NXP Semiconductors 11 * Copyright (C) 2012 Roland Stigge 12 * 13 * Note: This driver is based on original work done by Mike James for 14 * the LPC3180. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 */ 30 31 #include <linux/clk.h> 32 #include <linux/delay.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/dmapool.h> 35 #include <linux/i2c.h> 36 #include <linux/interrupt.h> 37 #include <linux/module.h> 38 #include <linux/of.h> 39 #include <linux/platform_device.h> 40 #include <linux/proc_fs.h> 41 #include <linux/slab.h> 42 #include <linux/usb/ch9.h> 43 #include <linux/usb/gadget.h> 44 #include <linux/usb/isp1301.h> 45 46 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 47 #include <linux/debugfs.h> 48 #include <linux/seq_file.h> 49 #endif 50 51 #include <mach/hardware.h> 52 #include <mach/platform.h> 53 54 /* 55 * USB device configuration structure 56 */ 57 typedef void (*usc_chg_event)(int); 58 struct lpc32xx_usbd_cfg { 59 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ 60 usc_chg_event conn_chgb; /* Connection change event (optional) */ 61 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ 62 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ 63 }; 64 65 /* 66 * controller driver data structures 67 */ 68 69 /* 16 endpoints (not to be confused with 32 hardware endpoints) */ 70 #define NUM_ENDPOINTS 16 71 72 /* 73 * IRQ indices make reading the code a little easier 74 */ 75 #define IRQ_USB_LP 0 76 #define IRQ_USB_HP 1 77 #define IRQ_USB_DEVDMA 2 78 #define IRQ_USB_ATX 3 79 80 #define EP_OUT 0 /* RX (from host) */ 81 #define EP_IN 1 /* TX (to host) */ 82 83 /* Returns the interrupt mask for the selected hardware endpoint */ 84 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) 85 86 #define EP_INT_TYPE 0 87 #define EP_ISO_TYPE 1 88 #define EP_BLK_TYPE 2 89 #define EP_CTL_TYPE 3 90 91 /* EP0 states */ 92 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */ 93 #define DATA_IN 1 /* Expect dev->host transfer */ 94 #define DATA_OUT 2 /* Expect host->dev transfer */ 95 96 /* DD (DMA Descriptor) structure, requires word alignment, this is already 97 * defined in the LPC32XX USB device header file, but this version is slightly 98 * modified to tag some work data with each DMA descriptor. */ 99 struct lpc32xx_usbd_dd_gad { 100 u32 dd_next_phy; 101 u32 dd_setup; 102 u32 dd_buffer_addr; 103 u32 dd_status; 104 u32 dd_iso_ps_mem_addr; 105 u32 this_dma; 106 u32 iso_status[6]; /* 5 spare */ 107 u32 dd_next_v; 108 }; 109 110 /* 111 * Logical endpoint structure 112 */ 113 struct lpc32xx_ep { 114 struct usb_ep ep; 115 struct list_head queue; 116 struct lpc32xx_udc *udc; 117 118 u32 hwep_num_base; /* Physical hardware EP */ 119 u32 hwep_num; /* Maps to hardware endpoint */ 120 u32 maxpacket; 121 u32 lep; 122 123 bool is_in; 124 bool req_pending; 125 u32 eptype; 126 127 u32 totalints; 128 129 bool wedge; 130 }; 131 132 /* 133 * Common UDC structure 134 */ 135 struct lpc32xx_udc { 136 struct usb_gadget gadget; 137 struct usb_gadget_driver *driver; 138 struct platform_device *pdev; 139 struct device *dev; 140 struct dentry *pde; 141 spinlock_t lock; 142 struct i2c_client *isp1301_i2c_client; 143 144 /* Board and device specific */ 145 struct lpc32xx_usbd_cfg *board; 146 u32 io_p_start; 147 u32 io_p_size; 148 void __iomem *udp_baseaddr; 149 int udp_irq[4]; 150 struct clk *usb_pll_clk; 151 struct clk *usb_slv_clk; 152 struct clk *usb_otg_clk; 153 154 /* DMA support */ 155 u32 *udca_v_base; 156 u32 udca_p_base; 157 struct dma_pool *dd_cache; 158 159 /* Common EP and control data */ 160 u32 enabled_devints; 161 u32 enabled_hwepints; 162 u32 dev_status; 163 u32 realized_eps; 164 165 /* VBUS detection, pullup, and power flags */ 166 u8 vbus; 167 u8 last_vbus; 168 int pullup; 169 int poweron; 170 171 /* Work queues related to I2C support */ 172 struct work_struct pullup_job; 173 struct work_struct vbus_job; 174 struct work_struct power_job; 175 176 /* USB device peripheral - various */ 177 struct lpc32xx_ep ep[NUM_ENDPOINTS]; 178 bool enabled; 179 bool clocked; 180 bool suspended; 181 int ep0state; 182 atomic_t enabled_ep_cnt; 183 wait_queue_head_t ep_disable_wait_queue; 184 }; 185 186 /* 187 * Endpoint request 188 */ 189 struct lpc32xx_request { 190 struct usb_request req; 191 struct list_head queue; 192 struct lpc32xx_usbd_dd_gad *dd_desc_ptr; 193 bool mapped; 194 bool send_zlp; 195 }; 196 197 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) 198 { 199 return container_of(g, struct lpc32xx_udc, gadget); 200 } 201 202 #define ep_dbg(epp, fmt, arg...) \ 203 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) 204 #define ep_err(epp, fmt, arg...) \ 205 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) 206 #define ep_info(epp, fmt, arg...) \ 207 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) 208 #define ep_warn(epp, fmt, arg...) \ 209 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) 210 211 #define UDCA_BUFF_SIZE (128) 212 213 /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will 214 * be replaced with an inremap()ed pointer 215 * */ 216 #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64) 217 218 /* USB_CTRL bit defines */ 219 #define USB_SLAVE_HCLK_EN (1 << 24) 220 #define USB_HOST_NEED_CLK_EN (1 << 21) 221 #define USB_DEV_NEED_CLK_EN (1 << 22) 222 223 /********************************************************************** 224 * USB device controller register offsets 225 **********************************************************************/ 226 227 #define USBD_DEVINTST(x) ((x) + 0x200) 228 #define USBD_DEVINTEN(x) ((x) + 0x204) 229 #define USBD_DEVINTCLR(x) ((x) + 0x208) 230 #define USBD_DEVINTSET(x) ((x) + 0x20C) 231 #define USBD_CMDCODE(x) ((x) + 0x210) 232 #define USBD_CMDDATA(x) ((x) + 0x214) 233 #define USBD_RXDATA(x) ((x) + 0x218) 234 #define USBD_TXDATA(x) ((x) + 0x21C) 235 #define USBD_RXPLEN(x) ((x) + 0x220) 236 #define USBD_TXPLEN(x) ((x) + 0x224) 237 #define USBD_CTRL(x) ((x) + 0x228) 238 #define USBD_DEVINTPRI(x) ((x) + 0x22C) 239 #define USBD_EPINTST(x) ((x) + 0x230) 240 #define USBD_EPINTEN(x) ((x) + 0x234) 241 #define USBD_EPINTCLR(x) ((x) + 0x238) 242 #define USBD_EPINTSET(x) ((x) + 0x23C) 243 #define USBD_EPINTPRI(x) ((x) + 0x240) 244 #define USBD_REEP(x) ((x) + 0x244) 245 #define USBD_EPIND(x) ((x) + 0x248) 246 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C) 247 /* DMA support registers only below */ 248 /* Set, clear, or get enabled state of the DMA request status. If 249 * enabled, an IN or OUT token will start a DMA transfer for the EP */ 250 #define USBD_DMARST(x) ((x) + 0x250) 251 #define USBD_DMARCLR(x) ((x) + 0x254) 252 #define USBD_DMARSET(x) ((x) + 0x258) 253 /* DMA UDCA head pointer */ 254 #define USBD_UDCAH(x) ((x) + 0x280) 255 /* EP DMA status, enable, and disable. This is used to specifically 256 * enabled or disable DMA for a specific EP */ 257 #define USBD_EPDMAST(x) ((x) + 0x284) 258 #define USBD_EPDMAEN(x) ((x) + 0x288) 259 #define USBD_EPDMADIS(x) ((x) + 0x28C) 260 /* DMA master interrupts enable and pending interrupts */ 261 #define USBD_DMAINTST(x) ((x) + 0x290) 262 #define USBD_DMAINTEN(x) ((x) + 0x294) 263 /* DMA end of transfer interrupt enable, disable, status */ 264 #define USBD_EOTINTST(x) ((x) + 0x2A0) 265 #define USBD_EOTINTCLR(x) ((x) + 0x2A4) 266 #define USBD_EOTINTSET(x) ((x) + 0x2A8) 267 /* New DD request interrupt enable, disable, status */ 268 #define USBD_NDDRTINTST(x) ((x) + 0x2AC) 269 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) 270 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4) 271 /* DMA error interrupt enable, disable, status */ 272 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8) 273 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) 274 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) 275 276 /********************************************************************** 277 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ 278 * USBD_DEVINTPRI register definitions 279 **********************************************************************/ 280 #define USBD_ERR_INT (1 << 9) 281 #define USBD_EP_RLZED (1 << 8) 282 #define USBD_TXENDPKT (1 << 7) 283 #define USBD_RXENDPKT (1 << 6) 284 #define USBD_CDFULL (1 << 5) 285 #define USBD_CCEMPTY (1 << 4) 286 #define USBD_DEV_STAT (1 << 3) 287 #define USBD_EP_SLOW (1 << 2) 288 #define USBD_EP_FAST (1 << 1) 289 #define USBD_FRAME (1 << 0) 290 291 /********************************************************************** 292 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ 293 * USBD_EPINTPRI register definitions 294 **********************************************************************/ 295 /* End point selection macro (RX) */ 296 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) 297 298 /* End point selection macro (TX) */ 299 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) 300 301 /********************************************************************** 302 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ 303 * USBD_EPDMAEN/USBD_EPDMADIS/ 304 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ 305 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ 306 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET 307 * register definitions 308 **********************************************************************/ 309 /* Endpoint selection macro */ 310 #define USBD_EP_SEL(e) (1 << (e)) 311 312 /********************************************************************** 313 * SBD_DMAINTST/USBD_DMAINTEN 314 **********************************************************************/ 315 #define USBD_SYS_ERR_INT (1 << 2) 316 #define USBD_NEW_DD_INT (1 << 1) 317 #define USBD_EOT_INT (1 << 0) 318 319 /********************************************************************** 320 * USBD_RXPLEN register definitions 321 **********************************************************************/ 322 #define USBD_PKT_RDY (1 << 11) 323 #define USBD_DV (1 << 10) 324 #define USBD_PK_LEN_MASK 0x3FF 325 326 /********************************************************************** 327 * USBD_CTRL register definitions 328 **********************************************************************/ 329 #define USBD_LOG_ENDPOINT(e) ((e) << 2) 330 #define USBD_WR_EN (1 << 1) 331 #define USBD_RD_EN (1 << 0) 332 333 /********************************************************************** 334 * USBD_CMDCODE register definitions 335 **********************************************************************/ 336 #define USBD_CMD_CODE(c) ((c) << 16) 337 #define USBD_CMD_PHASE(p) ((p) << 8) 338 339 /********************************************************************** 340 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions 341 **********************************************************************/ 342 #define USBD_DMAEP(e) (1 << (e)) 343 344 /* DD (DMA Descriptor) structure, requires word alignment */ 345 struct lpc32xx_usbd_dd { 346 u32 *dd_next; 347 u32 dd_setup; 348 u32 dd_buffer_addr; 349 u32 dd_status; 350 u32 dd_iso_ps_mem_addr; 351 }; 352 353 /* dd_setup bit defines */ 354 #define DD_SETUP_ATLE_DMA_MODE 0x01 355 #define DD_SETUP_NEXT_DD_VALID 0x04 356 #define DD_SETUP_ISO_EP 0x10 357 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) 358 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) 359 360 /* dd_status bit defines */ 361 #define DD_STATUS_DD_RETIRED 0x01 362 #define DD_STATUS_STS_MASK 0x1E 363 #define DD_STATUS_STS_NS 0x00 /* Not serviced */ 364 #define DD_STATUS_STS_BS 0x02 /* Being serviced */ 365 #define DD_STATUS_STS_NC 0x04 /* Normal completion */ 366 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ 367 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */ 368 #define DD_STATUS_STS_SE 0x12 /* System error */ 369 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ 370 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ 371 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ 372 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) 373 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) 374 375 /* 376 * 377 * Protocol engine bits below 378 * 379 */ 380 /* Device Interrupt Bit Definitions */ 381 #define FRAME_INT 0x00000001 382 #define EP_FAST_INT 0x00000002 383 #define EP_SLOW_INT 0x00000004 384 #define DEV_STAT_INT 0x00000008 385 #define CCEMTY_INT 0x00000010 386 #define CDFULL_INT 0x00000020 387 #define RxENDPKT_INT 0x00000040 388 #define TxENDPKT_INT 0x00000080 389 #define EP_RLZED_INT 0x00000100 390 #define ERR_INT 0x00000200 391 392 /* Rx & Tx Packet Length Definitions */ 393 #define PKT_LNGTH_MASK 0x000003FF 394 #define PKT_DV 0x00000400 395 #define PKT_RDY 0x00000800 396 397 /* USB Control Definitions */ 398 #define CTRL_RD_EN 0x00000001 399 #define CTRL_WR_EN 0x00000002 400 401 /* Command Codes */ 402 #define CMD_SET_ADDR 0x00D00500 403 #define CMD_CFG_DEV 0x00D80500 404 #define CMD_SET_MODE 0x00F30500 405 #define CMD_RD_FRAME 0x00F50500 406 #define DAT_RD_FRAME 0x00F50200 407 #define CMD_RD_TEST 0x00FD0500 408 #define DAT_RD_TEST 0x00FD0200 409 #define CMD_SET_DEV_STAT 0x00FE0500 410 #define CMD_GET_DEV_STAT 0x00FE0500 411 #define DAT_GET_DEV_STAT 0x00FE0200 412 #define CMD_GET_ERR_CODE 0x00FF0500 413 #define DAT_GET_ERR_CODE 0x00FF0200 414 #define CMD_RD_ERR_STAT 0x00FB0500 415 #define DAT_RD_ERR_STAT 0x00FB0200 416 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) 417 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) 418 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) 419 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) 420 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) 421 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) 422 #define CMD_CLR_BUF 0x00F20500 423 #define DAT_CLR_BUF 0x00F20200 424 #define CMD_VALID_BUF 0x00FA0500 425 426 /* Device Address Register Definitions */ 427 #define DEV_ADDR_MASK 0x7F 428 #define DEV_EN 0x80 429 430 /* Device Configure Register Definitions */ 431 #define CONF_DVICE 0x01 432 433 /* Device Mode Register Definitions */ 434 #define AP_CLK 0x01 435 #define INAK_CI 0x02 436 #define INAK_CO 0x04 437 #define INAK_II 0x08 438 #define INAK_IO 0x10 439 #define INAK_BI 0x20 440 #define INAK_BO 0x40 441 442 /* Device Status Register Definitions */ 443 #define DEV_CON 0x01 444 #define DEV_CON_CH 0x02 445 #define DEV_SUS 0x04 446 #define DEV_SUS_CH 0x08 447 #define DEV_RST 0x10 448 449 /* Error Code Register Definitions */ 450 #define ERR_EC_MASK 0x0F 451 #define ERR_EA 0x10 452 453 /* Error Status Register Definitions */ 454 #define ERR_PID 0x01 455 #define ERR_UEPKT 0x02 456 #define ERR_DCRC 0x04 457 #define ERR_TIMOUT 0x08 458 #define ERR_EOP 0x10 459 #define ERR_B_OVRN 0x20 460 #define ERR_BTSTF 0x40 461 #define ERR_TGL 0x80 462 463 /* Endpoint Select Register Definitions */ 464 #define EP_SEL_F 0x01 465 #define EP_SEL_ST 0x02 466 #define EP_SEL_STP 0x04 467 #define EP_SEL_PO 0x08 468 #define EP_SEL_EPN 0x10 469 #define EP_SEL_B_1_FULL 0x20 470 #define EP_SEL_B_2_FULL 0x40 471 472 /* Endpoint Status Register Definitions */ 473 #define EP_STAT_ST 0x01 474 #define EP_STAT_DA 0x20 475 #define EP_STAT_RF_MO 0x40 476 #define EP_STAT_CND_ST 0x80 477 478 /* Clear Buffer Register Definitions */ 479 #define CLR_BUF_PO 0x01 480 481 /* DMA Interrupt Bit Definitions */ 482 #define EOT_INT 0x01 483 #define NDD_REQ_INT 0x02 484 #define SYS_ERR_INT 0x04 485 486 #define DRIVER_VERSION "1.03" 487 static const char driver_name[] = "lpc32xx_udc"; 488 489 /* 490 * 491 * proc interface support 492 * 493 */ 494 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 495 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; 496 static const char debug_filename[] = "driver/udc"; 497 498 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) 499 { 500 struct lpc32xx_request *req; 501 502 seq_printf(s, "\n"); 503 seq_printf(s, "%12s, maxpacket %4d %3s", 504 ep->ep.name, ep->ep.maxpacket, 505 ep->is_in ? "in" : "out"); 506 seq_printf(s, " type %4s", epnames[ep->eptype]); 507 seq_printf(s, " ints: %12d", ep->totalints); 508 509 if (list_empty(&ep->queue)) 510 seq_printf(s, "\t(queue empty)\n"); 511 else { 512 list_for_each_entry(req, &ep->queue, queue) { 513 u32 length = req->req.actual; 514 515 seq_printf(s, "\treq %p len %d/%d buf %p\n", 516 &req->req, length, 517 req->req.length, req->req.buf); 518 } 519 } 520 } 521 522 static int proc_udc_show(struct seq_file *s, void *unused) 523 { 524 struct lpc32xx_udc *udc = s->private; 525 struct lpc32xx_ep *ep; 526 unsigned long flags; 527 528 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); 529 530 spin_lock_irqsave(&udc->lock, flags); 531 532 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", 533 udc->vbus ? "present" : "off", 534 udc->enabled ? (udc->vbus ? "active" : "enabled") : 535 "disabled", 536 udc->gadget.is_selfpowered ? "self" : "VBUS", 537 udc->suspended ? ", suspended" : "", 538 udc->driver ? udc->driver->driver.name : "(none)"); 539 540 if (udc->enabled && udc->vbus) { 541 proc_ep_show(s, &udc->ep[0]); 542 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) 543 proc_ep_show(s, ep); 544 } 545 546 spin_unlock_irqrestore(&udc->lock, flags); 547 548 return 0; 549 } 550 551 static int proc_udc_open(struct inode *inode, struct file *file) 552 { 553 return single_open(file, proc_udc_show, PDE_DATA(inode)); 554 } 555 556 static const struct file_operations proc_ops = { 557 .owner = THIS_MODULE, 558 .open = proc_udc_open, 559 .read = seq_read, 560 .llseek = seq_lseek, 561 .release = single_release, 562 }; 563 564 static void create_debug_file(struct lpc32xx_udc *udc) 565 { 566 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops); 567 } 568 569 static void remove_debug_file(struct lpc32xx_udc *udc) 570 { 571 debugfs_remove(udc->pde); 572 } 573 574 #else 575 static inline void create_debug_file(struct lpc32xx_udc *udc) {} 576 static inline void remove_debug_file(struct lpc32xx_udc *udc) {} 577 #endif 578 579 /* Primary initialization sequence for the ISP1301 transceiver */ 580 static void isp1301_udc_configure(struct lpc32xx_udc *udc) 581 { 582 /* LPC32XX only supports DAT_SE0 USB mode */ 583 /* This sequence is important */ 584 585 /* Disable transparent UART mode first */ 586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 587 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 588 MC1_UART_EN); 589 590 /* Set full speed and SE0 mode */ 591 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 592 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 594 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); 595 596 /* 597 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide 598 */ 599 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 600 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 601 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 602 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL)); 603 604 /* Driver VBUS_DRV high or low depending on board setup */ 605 if (udc->board->vbus_drv_pol != 0) 606 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 607 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); 608 else 609 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 610 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 611 OTG1_VBUS_DRV); 612 613 /* Bi-directional mode with suspend control 614 * Enable both pulldowns for now - the pullup will be enable when VBUS 615 * is detected */ 616 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 617 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 618 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 619 ISP1301_I2C_OTG_CONTROL_1, 620 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 621 622 /* Discharge VBUS (just in case) */ 623 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 624 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 625 msleep(1); 626 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 627 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 628 OTG1_VBUS_DISCHRG); 629 630 /* Clear and enable VBUS high edge interrupt */ 631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 632 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 633 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 634 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 635 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 636 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD); 637 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 638 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 639 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 640 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD); 641 642 /* Enable usb_need_clk clock after transceiver is initialized */ 643 writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL); 644 645 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", 646 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00)); 647 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", 648 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02)); 649 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", 650 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); 651 } 652 653 /* Enables or disables the USB device pullup via the ISP1301 transceiver */ 654 static void isp1301_pullup_set(struct lpc32xx_udc *udc) 655 { 656 if (udc->pullup) 657 /* Enable pullup for bus signalling */ 658 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 659 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); 660 else 661 /* Enable pullup for bus signalling */ 662 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 663 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 664 OTG1_DP_PULLUP); 665 } 666 667 static void pullup_work(struct work_struct *work) 668 { 669 struct lpc32xx_udc *udc = 670 container_of(work, struct lpc32xx_udc, pullup_job); 671 672 isp1301_pullup_set(udc); 673 } 674 675 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, 676 int block) 677 { 678 if (en_pullup == udc->pullup) 679 return; 680 681 udc->pullup = en_pullup; 682 if (block) 683 isp1301_pullup_set(udc); 684 else 685 /* defer slow i2c pull up setting */ 686 schedule_work(&udc->pullup_job); 687 } 688 689 #ifdef CONFIG_PM 690 /* Powers up or down the ISP1301 transceiver */ 691 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) 692 { 693 if (enable != 0) 694 /* Power up ISP1301 - this ISP1301 will automatically wakeup 695 when VBUS is detected */ 696 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 697 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, 698 MC2_GLOBAL_PWR_DN); 699 else 700 /* Power down ISP1301 */ 701 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 702 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); 703 } 704 705 static void power_work(struct work_struct *work) 706 { 707 struct lpc32xx_udc *udc = 708 container_of(work, struct lpc32xx_udc, power_job); 709 710 isp1301_set_powerstate(udc, udc->poweron); 711 } 712 #endif 713 714 /* 715 * 716 * USB protocol engine command/data read/write helper functions 717 * 718 */ 719 /* Issues a single command to the USB device state machine */ 720 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) 721 { 722 u32 pass = 0; 723 int to; 724 725 /* EP may lock on CLRI if this read isn't done */ 726 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 727 (void) tmp; 728 729 while (pass == 0) { 730 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); 731 732 /* Write command code */ 733 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); 734 to = 10000; 735 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & 736 USBD_CCEMPTY) == 0) && (to > 0)) { 737 to--; 738 } 739 740 if (to > 0) 741 pass = 1; 742 743 cpu_relax(); 744 } 745 } 746 747 /* Issues 2 commands (or command and data) to the USB device state machine */ 748 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, 749 u32 data) 750 { 751 udc_protocol_cmd_w(udc, cmd); 752 udc_protocol_cmd_w(udc, data); 753 } 754 755 /* Issues a single command to the USB device state machine and reads 756 * response data */ 757 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) 758 { 759 u32 tmp; 760 int to = 1000; 761 762 /* Write a command and read data from the protocol engine */ 763 writel((USBD_CDFULL | USBD_CCEMPTY), 764 USBD_DEVINTCLR(udc->udp_baseaddr)); 765 766 /* Write command code */ 767 udc_protocol_cmd_w(udc, cmd); 768 769 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 770 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) 771 && (to > 0)) 772 to--; 773 if (!to) 774 dev_dbg(udc->dev, 775 "Protocol engine didn't receive response (CDFULL)\n"); 776 777 return readl(USBD_CMDDATA(udc->udp_baseaddr)); 778 } 779 780 /* 781 * 782 * USB device interrupt mask support functions 783 * 784 */ 785 /* Enable one or more USB device interrupts */ 786 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) 787 { 788 udc->enabled_devints |= devmask; 789 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 790 } 791 792 /* Disable one or more USB device interrupts */ 793 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) 794 { 795 udc->enabled_devints &= ~mask; 796 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 797 } 798 799 /* Clear one or more USB device interrupts */ 800 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) 801 { 802 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); 803 } 804 805 /* 806 * 807 * Endpoint interrupt disable/enable functions 808 * 809 */ 810 /* Enable one or more USB endpoint interrupts */ 811 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 812 { 813 udc->enabled_hwepints |= (1 << hwep); 814 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 815 } 816 817 /* Disable one or more USB endpoint interrupts */ 818 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 819 { 820 udc->enabled_hwepints &= ~(1 << hwep); 821 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 822 } 823 824 /* Clear one or more USB endpoint interrupts */ 825 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) 826 { 827 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); 828 } 829 830 /* Enable DMA for the HW channel */ 831 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) 832 { 833 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); 834 } 835 836 /* Disable DMA for the HW channel */ 837 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) 838 { 839 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); 840 } 841 842 /* 843 * 844 * Endpoint realize/unrealize functions 845 * 846 */ 847 /* Before an endpoint can be used, it needs to be realized 848 * in the USB protocol engine - this realizes the endpoint. 849 * The interrupt (FIFO or DMA) is not enabled with this function */ 850 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, 851 u32 maxpacket) 852 { 853 int to = 1000; 854 855 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 856 writel(hwep, USBD_EPIND(udc->udp_baseaddr)); 857 udc->realized_eps |= (1 << hwep); 858 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 859 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); 860 861 /* Wait until endpoint is realized in hardware */ 862 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & 863 USBD_EP_RLZED)) && (to > 0)) 864 to--; 865 if (!to) 866 dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); 867 868 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 869 } 870 871 /* Unrealize an EP */ 872 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) 873 { 874 udc->realized_eps &= ~(1 << hwep); 875 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 876 } 877 878 /* 879 * 880 * Endpoint support functions 881 * 882 */ 883 /* Select and clear endpoint interrupt */ 884 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) 885 { 886 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); 887 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); 888 } 889 890 /* Disables the endpoint in the USB protocol engine */ 891 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) 892 { 893 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 894 DAT_WR_BYTE(EP_STAT_DA)); 895 } 896 897 /* Stalls the endpoint - endpoint will return STALL */ 898 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) 899 { 900 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 901 DAT_WR_BYTE(EP_STAT_ST)); 902 } 903 904 /* Clear stall or reset endpoint */ 905 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) 906 { 907 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 908 DAT_WR_BYTE(0)); 909 } 910 911 /* Select an endpoint for endpoint status, clear, validate */ 912 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) 913 { 914 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); 915 } 916 917 /* 918 * 919 * Endpoint buffer management functions 920 * 921 */ 922 /* Clear the current endpoint's buffer */ 923 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 924 { 925 udc_select_hwep(udc, hwep); 926 udc_protocol_cmd_w(udc, CMD_CLR_BUF); 927 } 928 929 /* Validate the current endpoint's buffer */ 930 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 931 { 932 udc_select_hwep(udc, hwep); 933 udc_protocol_cmd_w(udc, CMD_VALID_BUF); 934 } 935 936 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) 937 { 938 /* Clear EP interrupt */ 939 uda_clear_hwepint(udc, hwep); 940 return udc_selep_clrint(udc, hwep); 941 } 942 943 /* 944 * 945 * USB EP DMA support 946 * 947 */ 948 /* Allocate a DMA Descriptor */ 949 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) 950 { 951 dma_addr_t dma; 952 struct lpc32xx_usbd_dd_gad *dd; 953 954 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc( 955 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma); 956 if (dd) 957 dd->this_dma = dma; 958 959 return dd; 960 } 961 962 /* Free a DMA Descriptor */ 963 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) 964 { 965 dma_pool_free(udc->dd_cache, dd, dd->this_dma); 966 } 967 968 /* 969 * 970 * USB setup and shutdown functions 971 * 972 */ 973 /* Enables or disables most of the USB system clocks when low power mode is 974 * needed. Clocks are typically started on a connection event, and disabled 975 * when a cable is disconnected */ 976 static void udc_clk_set(struct lpc32xx_udc *udc, int enable) 977 { 978 if (enable != 0) { 979 if (udc->clocked) 980 return; 981 982 udc->clocked = 1; 983 984 /* 48MHz PLL up */ 985 clk_enable(udc->usb_pll_clk); 986 987 /* Enable the USB device clock */ 988 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, 989 USB_CTRL); 990 991 clk_enable(udc->usb_otg_clk); 992 } else { 993 if (!udc->clocked) 994 return; 995 996 udc->clocked = 0; 997 998 /* Never disable the USB_HCLK during normal operation */ 999 1000 /* 48MHz PLL dpwn */ 1001 clk_disable(udc->usb_pll_clk); 1002 1003 /* Disable the USB device clock */ 1004 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN, 1005 USB_CTRL); 1006 1007 clk_disable(udc->usb_otg_clk); 1008 } 1009 } 1010 1011 /* Set/reset USB device address */ 1012 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) 1013 { 1014 /* Address will be latched at the end of the status phase, or 1015 latched immediately if function is called twice */ 1016 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, 1017 DAT_WR_BYTE(DEV_EN | addr)); 1018 } 1019 1020 /* Setup up a IN request for DMA transfer - this consists of determining the 1021 * list of DMA addresses for the transfer, allocating DMA Descriptors, 1022 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 1023 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1024 { 1025 struct lpc32xx_request *req; 1026 u32 hwep = ep->hwep_num; 1027 1028 ep->req_pending = 1; 1029 1030 /* There will always be a request waiting here */ 1031 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1032 1033 /* Place the DD Descriptor into the UDCA */ 1034 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1035 1036 /* Enable DMA and interrupt for the HW EP */ 1037 udc_ep_dma_enable(udc, hwep); 1038 1039 /* Clear ZLP if last packet is not of MAXP size */ 1040 if (req->req.length % ep->ep.maxpacket) 1041 req->send_zlp = 0; 1042 1043 return 0; 1044 } 1045 1046 /* Setup up a OUT request for DMA transfer - this consists of determining the 1047 * list of DMA addresses for the transfer, allocating DMA Descriptors, 1048 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 1049 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1050 { 1051 struct lpc32xx_request *req; 1052 u32 hwep = ep->hwep_num; 1053 1054 ep->req_pending = 1; 1055 1056 /* There will always be a request waiting here */ 1057 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1058 1059 /* Place the DD Descriptor into the UDCA */ 1060 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1061 1062 /* Enable DMA and interrupt for the HW EP */ 1063 udc_ep_dma_enable(udc, hwep); 1064 return 0; 1065 } 1066 1067 static void udc_disable(struct lpc32xx_udc *udc) 1068 { 1069 u32 i; 1070 1071 /* Disable device */ 1072 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1073 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); 1074 1075 /* Disable all device interrupts (including EP0) */ 1076 uda_disable_devint(udc, 0x3FF); 1077 1078 /* Disable and reset all endpoint interrupts */ 1079 for (i = 0; i < 32; i++) { 1080 uda_disable_hwepint(udc, i); 1081 uda_clear_hwepint(udc, i); 1082 udc_disable_hwep(udc, i); 1083 udc_unrealize_hwep(udc, i); 1084 udc->udca_v_base[i] = 0; 1085 1086 /* Disable and clear all interrupts and DMA */ 1087 udc_ep_dma_disable(udc, i); 1088 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); 1089 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1090 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1091 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); 1092 } 1093 1094 /* Disable DMA interrupts */ 1095 writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); 1096 1097 writel(0, USBD_UDCAH(udc->udp_baseaddr)); 1098 } 1099 1100 static void udc_enable(struct lpc32xx_udc *udc) 1101 { 1102 u32 i; 1103 struct lpc32xx_ep *ep = &udc->ep[0]; 1104 1105 /* Start with known state */ 1106 udc_disable(udc); 1107 1108 /* Enable device */ 1109 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); 1110 1111 /* EP interrupts on high priority, FRAME interrupt on low priority */ 1112 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); 1113 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); 1114 1115 /* Clear any pending device interrupts */ 1116 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); 1117 1118 /* Setup UDCA - not yet used (DMA) */ 1119 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); 1120 1121 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ 1122 for (i = 0; i <= 1; i++) { 1123 udc_realize_hwep(udc, i, ep->ep.maxpacket); 1124 uda_enable_hwepint(udc, i); 1125 udc_select_hwep(udc, i); 1126 udc_clrstall_hwep(udc, i); 1127 udc_clr_buffer_hwep(udc, i); 1128 } 1129 1130 /* Device interrupt setup */ 1131 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1132 USBD_EP_FAST)); 1133 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1134 USBD_EP_FAST)); 1135 1136 /* Set device address to 0 - called twice to force a latch in the USB 1137 engine without the need of a setup packet status closure */ 1138 udc_set_address(udc, 0); 1139 udc_set_address(udc, 0); 1140 1141 /* Enable master DMA interrupts */ 1142 writel((USBD_SYS_ERR_INT | USBD_EOT_INT), 1143 USBD_DMAINTEN(udc->udp_baseaddr)); 1144 1145 udc->dev_status = 0; 1146 } 1147 1148 /* 1149 * 1150 * USB device board specific events handled via callbacks 1151 * 1152 */ 1153 /* Connection change event - notify board function of change */ 1154 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) 1155 { 1156 /* Just notify of a connection change event (optional) */ 1157 if (udc->board->conn_chgb != NULL) 1158 udc->board->conn_chgb(conn); 1159 } 1160 1161 /* Suspend/resume event - notify board function of change */ 1162 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) 1163 { 1164 /* Just notify of a Suspend/resume change event (optional) */ 1165 if (udc->board->susp_chgb != NULL) 1166 udc->board->susp_chgb(conn); 1167 1168 if (conn) 1169 udc->suspended = 0; 1170 else 1171 udc->suspended = 1; 1172 } 1173 1174 /* Remote wakeup enable/disable - notify board function of change */ 1175 static void uda_remwkp_cgh(struct lpc32xx_udc *udc) 1176 { 1177 if (udc->board->rmwk_chgb != NULL) 1178 udc->board->rmwk_chgb(udc->dev_status & 1179 (1 << USB_DEVICE_REMOTE_WAKEUP)); 1180 } 1181 1182 /* Reads data from FIFO, adjusts for alignment and data size */ 1183 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1184 { 1185 int n, i, bl; 1186 u16 *p16; 1187 u32 *p32, tmp, cbytes; 1188 1189 /* Use optimal data transfer method based on source address and size */ 1190 switch (((u32) data) & 0x3) { 1191 case 0: /* 32-bit aligned */ 1192 p32 = (u32 *) data; 1193 cbytes = (bytes & ~0x3); 1194 1195 /* Copy 32-bit aligned data first */ 1196 for (n = 0; n < cbytes; n += 4) 1197 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); 1198 1199 /* Handle any remaining bytes */ 1200 bl = bytes - cbytes; 1201 if (bl) { 1202 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1203 for (n = 0; n < bl; n++) 1204 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1205 1206 } 1207 break; 1208 1209 case 1: /* 8-bit aligned */ 1210 case 3: 1211 /* Each byte has to be handled independently */ 1212 for (n = 0; n < bytes; n += 4) { 1213 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1214 1215 bl = bytes - n; 1216 if (bl > 3) 1217 bl = 3; 1218 1219 for (i = 0; i < bl; i++) 1220 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF); 1221 } 1222 break; 1223 1224 case 2: /* 16-bit aligned */ 1225 p16 = (u16 *) data; 1226 cbytes = (bytes & ~0x3); 1227 1228 /* Copy 32-bit sized objects first with 16-bit alignment */ 1229 for (n = 0; n < cbytes; n += 4) { 1230 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1231 *p16++ = (u16)(tmp & 0xFFFF); 1232 *p16++ = (u16)((tmp >> 16) & 0xFFFF); 1233 } 1234 1235 /* Handle any remaining bytes */ 1236 bl = bytes - cbytes; 1237 if (bl) { 1238 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1239 for (n = 0; n < bl; n++) 1240 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1241 } 1242 break; 1243 } 1244 } 1245 1246 /* Read data from the FIFO for an endpoint. This function is for endpoints (such 1247 * as EP0) that don't use DMA. This function should only be called if a packet 1248 * is known to be ready to read for the endpoint. Note that the endpoint must 1249 * be selected in the protocol engine prior to this call. */ 1250 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1251 u32 bytes) 1252 { 1253 u32 tmpv; 1254 int to = 1000; 1255 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; 1256 1257 /* Setup read of endpoint */ 1258 writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); 1259 1260 /* Wait until packet is ready */ 1261 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & 1262 PKT_RDY) == 0) && (to > 0)) 1263 to--; 1264 if (!to) 1265 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); 1266 1267 /* Mask out count */ 1268 tmp = tmpv & PKT_LNGTH_MASK; 1269 if (bytes < tmp) 1270 tmp = bytes; 1271 1272 if ((tmp > 0) && (data != NULL)) 1273 udc_pop_fifo(udc, (u8 *) data, tmp); 1274 1275 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1276 1277 /* Clear the buffer */ 1278 udc_clr_buffer_hwep(udc, hwep); 1279 1280 return tmp; 1281 } 1282 1283 /* Stuffs data into the FIFO, adjusts for alignment and data size */ 1284 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1285 { 1286 int n, i, bl; 1287 u16 *p16; 1288 u32 *p32, tmp, cbytes; 1289 1290 /* Use optimal data transfer method based on source address and size */ 1291 switch (((u32) data) & 0x3) { 1292 case 0: /* 32-bit aligned */ 1293 p32 = (u32 *) data; 1294 cbytes = (bytes & ~0x3); 1295 1296 /* Copy 32-bit aligned data first */ 1297 for (n = 0; n < cbytes; n += 4) 1298 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); 1299 1300 /* Handle any remaining bytes */ 1301 bl = bytes - cbytes; 1302 if (bl) { 1303 tmp = 0; 1304 for (n = 0; n < bl; n++) 1305 tmp |= data[cbytes + n] << (n * 8); 1306 1307 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1308 } 1309 break; 1310 1311 case 1: /* 8-bit aligned */ 1312 case 3: 1313 /* Each byte has to be handled independently */ 1314 for (n = 0; n < bytes; n += 4) { 1315 bl = bytes - n; 1316 if (bl > 4) 1317 bl = 4; 1318 1319 tmp = 0; 1320 for (i = 0; i < bl; i++) 1321 tmp |= data[n + i] << (i * 8); 1322 1323 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1324 } 1325 break; 1326 1327 case 2: /* 16-bit aligned */ 1328 p16 = (u16 *) data; 1329 cbytes = (bytes & ~0x3); 1330 1331 /* Copy 32-bit aligned data first */ 1332 for (n = 0; n < cbytes; n += 4) { 1333 tmp = *p16++ & 0xFFFF; 1334 tmp |= (*p16++ & 0xFFFF) << 16; 1335 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1336 } 1337 1338 /* Handle any remaining bytes */ 1339 bl = bytes - cbytes; 1340 if (bl) { 1341 tmp = 0; 1342 for (n = 0; n < bl; n++) 1343 tmp |= data[cbytes + n] << (n * 8); 1344 1345 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1346 } 1347 break; 1348 } 1349 } 1350 1351 /* Write data to the FIFO for an endpoint. This function is for endpoints (such 1352 * as EP0) that don't use DMA. Note that the endpoint must be selected in the 1353 * protocol engine prior to this call. */ 1354 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1355 u32 bytes) 1356 { 1357 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; 1358 1359 if ((bytes > 0) && (data == NULL)) 1360 return; 1361 1362 /* Setup write of endpoint */ 1363 writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); 1364 1365 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); 1366 1367 /* Need at least 1 byte to trigger TX */ 1368 if (bytes == 0) 1369 writel(0, USBD_TXDATA(udc->udp_baseaddr)); 1370 else 1371 udc_stuff_fifo(udc, (u8 *) data, bytes); 1372 1373 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1374 1375 udc_val_buffer_hwep(udc, hwep); 1376 } 1377 1378 /* USB device reset - resets USB to a default state with just EP0 1379 enabled */ 1380 static void uda_usb_reset(struct lpc32xx_udc *udc) 1381 { 1382 u32 i = 0; 1383 /* Re-init device controller and EP0 */ 1384 udc_enable(udc); 1385 udc->gadget.speed = USB_SPEED_FULL; 1386 1387 for (i = 1; i < NUM_ENDPOINTS; i++) { 1388 struct lpc32xx_ep *ep = &udc->ep[i]; 1389 ep->req_pending = 0; 1390 } 1391 } 1392 1393 /* Send a ZLP on EP0 */ 1394 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) 1395 { 1396 udc_write_hwep(udc, EP_IN, NULL, 0); 1397 } 1398 1399 /* Get current frame number */ 1400 static u16 udc_get_current_frame(struct lpc32xx_udc *udc) 1401 { 1402 u16 flo, fhi; 1403 1404 udc_protocol_cmd_w(udc, CMD_RD_FRAME); 1405 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1406 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1407 1408 return (fhi << 8) | flo; 1409 } 1410 1411 /* Set the device as configured - enables all endpoints */ 1412 static inline void udc_set_device_configured(struct lpc32xx_udc *udc) 1413 { 1414 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); 1415 } 1416 1417 /* Set the device as unconfigured - disables all endpoints */ 1418 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) 1419 { 1420 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1421 } 1422 1423 /* reinit == restore initial software state */ 1424 static void udc_reinit(struct lpc32xx_udc *udc) 1425 { 1426 u32 i; 1427 1428 INIT_LIST_HEAD(&udc->gadget.ep_list); 1429 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); 1430 1431 for (i = 0; i < NUM_ENDPOINTS; i++) { 1432 struct lpc32xx_ep *ep = &udc->ep[i]; 1433 1434 if (i != 0) 1435 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 1436 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); 1437 INIT_LIST_HEAD(&ep->queue); 1438 ep->req_pending = 0; 1439 } 1440 1441 udc->ep0state = WAIT_FOR_SETUP; 1442 } 1443 1444 /* Must be called with lock */ 1445 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) 1446 { 1447 struct lpc32xx_udc *udc = ep->udc; 1448 1449 list_del_init(&req->queue); 1450 if (req->req.status == -EINPROGRESS) 1451 req->req.status = status; 1452 else 1453 status = req->req.status; 1454 1455 if (ep->lep) { 1456 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 1457 1458 /* Free DDs */ 1459 udc_dd_free(udc, req->dd_desc_ptr); 1460 } 1461 1462 if (status && status != -ESHUTDOWN) 1463 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); 1464 1465 ep->req_pending = 0; 1466 spin_unlock(&udc->lock); 1467 usb_gadget_giveback_request(&ep->ep, &req->req); 1468 spin_lock(&udc->lock); 1469 } 1470 1471 /* Must be called with lock */ 1472 static void nuke(struct lpc32xx_ep *ep, int status) 1473 { 1474 struct lpc32xx_request *req; 1475 1476 while (!list_empty(&ep->queue)) { 1477 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1478 done(ep, req, status); 1479 } 1480 1481 if (status == -ESHUTDOWN) { 1482 uda_disable_hwepint(ep->udc, ep->hwep_num); 1483 udc_disable_hwep(ep->udc, ep->hwep_num); 1484 } 1485 } 1486 1487 /* IN endpoint 0 transfer */ 1488 static int udc_ep0_in_req(struct lpc32xx_udc *udc) 1489 { 1490 struct lpc32xx_request *req; 1491 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1492 u32 tsend, ts = 0; 1493 1494 if (list_empty(&ep0->queue)) 1495 /* Nothing to send */ 1496 return 0; 1497 else 1498 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1499 queue); 1500 1501 tsend = ts = req->req.length - req->req.actual; 1502 if (ts == 0) { 1503 /* Send a ZLP */ 1504 udc_ep0_send_zlp(udc); 1505 done(ep0, req, 0); 1506 return 1; 1507 } else if (ts > ep0->ep.maxpacket) 1508 ts = ep0->ep.maxpacket; /* Just send what we can */ 1509 1510 /* Write data to the EP0 FIFO and start transfer */ 1511 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); 1512 1513 /* Increment data pointer */ 1514 req->req.actual += ts; 1515 1516 if (tsend >= ep0->ep.maxpacket) 1517 return 0; /* Stay in data transfer state */ 1518 1519 /* Transfer request is complete */ 1520 udc->ep0state = WAIT_FOR_SETUP; 1521 done(ep0, req, 0); 1522 return 1; 1523 } 1524 1525 /* OUT endpoint 0 transfer */ 1526 static int udc_ep0_out_req(struct lpc32xx_udc *udc) 1527 { 1528 struct lpc32xx_request *req; 1529 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1530 u32 tr, bufferspace; 1531 1532 if (list_empty(&ep0->queue)) 1533 return 0; 1534 else 1535 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1536 queue); 1537 1538 if (req) { 1539 if (req->req.length == 0) { 1540 /* Just dequeue request */ 1541 done(ep0, req, 0); 1542 udc->ep0state = WAIT_FOR_SETUP; 1543 return 1; 1544 } 1545 1546 /* Get data from FIFO */ 1547 bufferspace = req->req.length - req->req.actual; 1548 if (bufferspace > ep0->ep.maxpacket) 1549 bufferspace = ep0->ep.maxpacket; 1550 1551 /* Copy data to buffer */ 1552 prefetchw(req->req.buf + req->req.actual); 1553 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, 1554 bufferspace); 1555 req->req.actual += bufferspace; 1556 1557 if (tr < ep0->ep.maxpacket) { 1558 /* This is the last packet */ 1559 done(ep0, req, 0); 1560 udc->ep0state = WAIT_FOR_SETUP; 1561 return 1; 1562 } 1563 } 1564 1565 return 0; 1566 } 1567 1568 /* Must be called with lock */ 1569 static void stop_activity(struct lpc32xx_udc *udc) 1570 { 1571 struct usb_gadget_driver *driver = udc->driver; 1572 int i; 1573 1574 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1575 driver = NULL; 1576 1577 udc->gadget.speed = USB_SPEED_UNKNOWN; 1578 udc->suspended = 0; 1579 1580 for (i = 0; i < NUM_ENDPOINTS; i++) { 1581 struct lpc32xx_ep *ep = &udc->ep[i]; 1582 nuke(ep, -ESHUTDOWN); 1583 } 1584 if (driver) { 1585 spin_unlock(&udc->lock); 1586 driver->disconnect(&udc->gadget); 1587 spin_lock(&udc->lock); 1588 } 1589 1590 isp1301_pullup_enable(udc, 0, 0); 1591 udc_disable(udc); 1592 udc_reinit(udc); 1593 } 1594 1595 /* 1596 * Activate or kill host pullup 1597 * Can be called with or without lock 1598 */ 1599 static void pullup(struct lpc32xx_udc *udc, int is_on) 1600 { 1601 if (!udc->clocked) 1602 return; 1603 1604 if (!udc->enabled || !udc->vbus) 1605 is_on = 0; 1606 1607 if (is_on != udc->pullup) 1608 isp1301_pullup_enable(udc, is_on, 0); 1609 } 1610 1611 /* Must be called without lock */ 1612 static int lpc32xx_ep_disable(struct usb_ep *_ep) 1613 { 1614 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1615 struct lpc32xx_udc *udc = ep->udc; 1616 unsigned long flags; 1617 1618 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) 1619 return -EINVAL; 1620 spin_lock_irqsave(&udc->lock, flags); 1621 1622 nuke(ep, -ESHUTDOWN); 1623 1624 /* Clear all DMA statuses for this EP */ 1625 udc_ep_dma_disable(udc, ep->hwep_num); 1626 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1627 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1628 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1629 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1630 1631 /* Remove the DD pointer in the UDCA */ 1632 udc->udca_v_base[ep->hwep_num] = 0; 1633 1634 /* Disable and reset endpoint and interrupt */ 1635 uda_clear_hwepint(udc, ep->hwep_num); 1636 udc_unrealize_hwep(udc, ep->hwep_num); 1637 1638 ep->hwep_num = 0; 1639 1640 spin_unlock_irqrestore(&udc->lock, flags); 1641 1642 atomic_dec(&udc->enabled_ep_cnt); 1643 wake_up(&udc->ep_disable_wait_queue); 1644 1645 return 0; 1646 } 1647 1648 /* Must be called without lock */ 1649 static int lpc32xx_ep_enable(struct usb_ep *_ep, 1650 const struct usb_endpoint_descriptor *desc) 1651 { 1652 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1653 struct lpc32xx_udc *udc = ep->udc; 1654 u16 maxpacket; 1655 u32 tmp; 1656 unsigned long flags; 1657 1658 /* Verify EP data */ 1659 if ((!_ep) || (!ep) || (!desc) || 1660 (desc->bDescriptorType != USB_DT_ENDPOINT)) { 1661 dev_dbg(udc->dev, "bad ep or descriptor\n"); 1662 return -EINVAL; 1663 } 1664 maxpacket = usb_endpoint_maxp(desc); 1665 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { 1666 dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); 1667 return -EINVAL; 1668 } 1669 1670 /* Don't touch EP0 */ 1671 if (ep->hwep_num_base == 0) { 1672 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); 1673 return -EINVAL; 1674 } 1675 1676 /* Is driver ready? */ 1677 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 1678 dev_dbg(udc->dev, "bogus device state\n"); 1679 return -ESHUTDOWN; 1680 } 1681 1682 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 1683 switch (tmp) { 1684 case USB_ENDPOINT_XFER_CONTROL: 1685 return -EINVAL; 1686 1687 case USB_ENDPOINT_XFER_INT: 1688 if (maxpacket > ep->maxpacket) { 1689 dev_dbg(udc->dev, 1690 "Bad INT endpoint maxpacket %d\n", maxpacket); 1691 return -EINVAL; 1692 } 1693 break; 1694 1695 case USB_ENDPOINT_XFER_BULK: 1696 switch (maxpacket) { 1697 case 8: 1698 case 16: 1699 case 32: 1700 case 64: 1701 break; 1702 1703 default: 1704 dev_dbg(udc->dev, 1705 "Bad BULK endpoint maxpacket %d\n", maxpacket); 1706 return -EINVAL; 1707 } 1708 break; 1709 1710 case USB_ENDPOINT_XFER_ISOC: 1711 break; 1712 } 1713 spin_lock_irqsave(&udc->lock, flags); 1714 1715 /* Initialize endpoint to match the selected descriptor */ 1716 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 1717 ep->ep.maxpacket = maxpacket; 1718 1719 /* Map hardware endpoint from base and direction */ 1720 if (ep->is_in) 1721 /* IN endpoints are offset 1 from the OUT endpoint */ 1722 ep->hwep_num = ep->hwep_num_base + EP_IN; 1723 else 1724 ep->hwep_num = ep->hwep_num_base; 1725 1726 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, 1727 ep->hwep_num, maxpacket, (ep->is_in == 1)); 1728 1729 /* Realize the endpoint, interrupt is enabled later when 1730 * buffers are queued, IN EPs will NAK until buffers are ready */ 1731 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); 1732 udc_clr_buffer_hwep(udc, ep->hwep_num); 1733 uda_disable_hwepint(udc, ep->hwep_num); 1734 udc_clrstall_hwep(udc, ep->hwep_num); 1735 1736 /* Clear all DMA statuses for this EP */ 1737 udc_ep_dma_disable(udc, ep->hwep_num); 1738 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1739 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1740 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1741 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1742 1743 spin_unlock_irqrestore(&udc->lock, flags); 1744 1745 atomic_inc(&udc->enabled_ep_cnt); 1746 return 0; 1747 } 1748 1749 /* 1750 * Allocate a USB request list 1751 * Can be called with or without lock 1752 */ 1753 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, 1754 gfp_t gfp_flags) 1755 { 1756 struct lpc32xx_request *req; 1757 1758 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); 1759 if (!req) 1760 return NULL; 1761 1762 INIT_LIST_HEAD(&req->queue); 1763 return &req->req; 1764 } 1765 1766 /* 1767 * De-allocate a USB request list 1768 * Can be called with or without lock 1769 */ 1770 static void lpc32xx_ep_free_request(struct usb_ep *_ep, 1771 struct usb_request *_req) 1772 { 1773 struct lpc32xx_request *req; 1774 1775 req = container_of(_req, struct lpc32xx_request, req); 1776 BUG_ON(!list_empty(&req->queue)); 1777 kfree(req); 1778 } 1779 1780 /* Must be called without lock */ 1781 static int lpc32xx_ep_queue(struct usb_ep *_ep, 1782 struct usb_request *_req, gfp_t gfp_flags) 1783 { 1784 struct lpc32xx_request *req; 1785 struct lpc32xx_ep *ep; 1786 struct lpc32xx_udc *udc; 1787 unsigned long flags; 1788 int status = 0; 1789 1790 req = container_of(_req, struct lpc32xx_request, req); 1791 ep = container_of(_ep, struct lpc32xx_ep, ep); 1792 1793 if (!_ep || !_req || !_req->complete || !_req->buf || 1794 !list_empty(&req->queue)) 1795 return -EINVAL; 1796 1797 udc = ep->udc; 1798 1799 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1800 return -EPIPE; 1801 1802 if (ep->lep) { 1803 struct lpc32xx_usbd_dd_gad *dd; 1804 1805 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in); 1806 if (status) 1807 return status; 1808 1809 /* For the request, build a list of DDs */ 1810 dd = udc_dd_alloc(udc); 1811 if (!dd) { 1812 /* Error allocating DD */ 1813 return -ENOMEM; 1814 } 1815 req->dd_desc_ptr = dd; 1816 1817 /* Setup the DMA descriptor */ 1818 dd->dd_next_phy = dd->dd_next_v = 0; 1819 dd->dd_buffer_addr = req->req.dma; 1820 dd->dd_status = 0; 1821 1822 /* Special handling for ISO EPs */ 1823 if (ep->eptype == EP_ISO_TYPE) { 1824 dd->dd_setup = DD_SETUP_ISO_EP | 1825 DD_SETUP_PACKETLEN(0) | 1826 DD_SETUP_DMALENBYTES(1); 1827 dd->dd_iso_ps_mem_addr = dd->this_dma + 24; 1828 if (ep->is_in) 1829 dd->iso_status[0] = req->req.length; 1830 else 1831 dd->iso_status[0] = 0; 1832 } else 1833 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | 1834 DD_SETUP_DMALENBYTES(req->req.length); 1835 } 1836 1837 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, 1838 _req, _req->length, _req->buf, ep->is_in, _req->zero); 1839 1840 spin_lock_irqsave(&udc->lock, flags); 1841 1842 _req->status = -EINPROGRESS; 1843 _req->actual = 0; 1844 req->send_zlp = _req->zero; 1845 1846 /* Kickstart empty queues */ 1847 if (list_empty(&ep->queue)) { 1848 list_add_tail(&req->queue, &ep->queue); 1849 1850 if (ep->hwep_num_base == 0) { 1851 /* Handle expected data direction */ 1852 if (ep->is_in) { 1853 /* IN packet to host */ 1854 udc->ep0state = DATA_IN; 1855 status = udc_ep0_in_req(udc); 1856 } else { 1857 /* OUT packet from host */ 1858 udc->ep0state = DATA_OUT; 1859 status = udc_ep0_out_req(udc); 1860 } 1861 } else if (ep->is_in) { 1862 /* IN packet to host and kick off transfer */ 1863 if (!ep->req_pending) 1864 udc_ep_in_req_dma(udc, ep); 1865 } else 1866 /* OUT packet from host and kick off list */ 1867 if (!ep->req_pending) 1868 udc_ep_out_req_dma(udc, ep); 1869 } else 1870 list_add_tail(&req->queue, &ep->queue); 1871 1872 spin_unlock_irqrestore(&udc->lock, flags); 1873 1874 return (status < 0) ? status : 0; 1875 } 1876 1877 /* Must be called without lock */ 1878 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1879 { 1880 struct lpc32xx_ep *ep; 1881 struct lpc32xx_request *req; 1882 unsigned long flags; 1883 1884 ep = container_of(_ep, struct lpc32xx_ep, ep); 1885 if (!_ep || ep->hwep_num_base == 0) 1886 return -EINVAL; 1887 1888 spin_lock_irqsave(&ep->udc->lock, flags); 1889 1890 /* make sure it's actually queued on this endpoint */ 1891 list_for_each_entry(req, &ep->queue, queue) { 1892 if (&req->req == _req) 1893 break; 1894 } 1895 if (&req->req != _req) { 1896 spin_unlock_irqrestore(&ep->udc->lock, flags); 1897 return -EINVAL; 1898 } 1899 1900 done(ep, req, -ECONNRESET); 1901 1902 spin_unlock_irqrestore(&ep->udc->lock, flags); 1903 1904 return 0; 1905 } 1906 1907 /* Must be called without lock */ 1908 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) 1909 { 1910 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1911 struct lpc32xx_udc *udc = ep->udc; 1912 unsigned long flags; 1913 1914 if ((!ep) || (ep->hwep_num <= 1)) 1915 return -EINVAL; 1916 1917 /* Don't halt an IN EP */ 1918 if (ep->is_in) 1919 return -EAGAIN; 1920 1921 spin_lock_irqsave(&udc->lock, flags); 1922 1923 if (value == 1) { 1924 /* stall */ 1925 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1926 DAT_WR_BYTE(EP_STAT_ST)); 1927 } else { 1928 /* End stall */ 1929 ep->wedge = 0; 1930 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1931 DAT_WR_BYTE(0)); 1932 } 1933 1934 spin_unlock_irqrestore(&udc->lock, flags); 1935 1936 return 0; 1937 } 1938 1939 /* set the halt feature and ignores clear requests */ 1940 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) 1941 { 1942 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1943 1944 if (!_ep || !ep->udc) 1945 return -EINVAL; 1946 1947 ep->wedge = 1; 1948 1949 return usb_ep_set_halt(_ep); 1950 } 1951 1952 static const struct usb_ep_ops lpc32xx_ep_ops = { 1953 .enable = lpc32xx_ep_enable, 1954 .disable = lpc32xx_ep_disable, 1955 .alloc_request = lpc32xx_ep_alloc_request, 1956 .free_request = lpc32xx_ep_free_request, 1957 .queue = lpc32xx_ep_queue, 1958 .dequeue = lpc32xx_ep_dequeue, 1959 .set_halt = lpc32xx_ep_set_halt, 1960 .set_wedge = lpc32xx_ep_set_wedge, 1961 }; 1962 1963 /* Send a ZLP on a non-0 IN EP */ 1964 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1965 { 1966 /* Clear EP status */ 1967 udc_clearep_getsts(udc, ep->hwep_num); 1968 1969 /* Send ZLP via FIFO mechanism */ 1970 udc_write_hwep(udc, ep->hwep_num, NULL, 0); 1971 } 1972 1973 /* 1974 * Handle EP completion for ZLP 1975 * This function will only be called when a delayed ZLP needs to be sent out 1976 * after a DMA transfer has filled both buffers. 1977 */ 1978 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1979 { 1980 u32 epstatus; 1981 struct lpc32xx_request *req; 1982 1983 if (ep->hwep_num <= 0) 1984 return; 1985 1986 uda_clear_hwepint(udc, ep->hwep_num); 1987 1988 /* If this interrupt isn't enabled, return now */ 1989 if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) 1990 return; 1991 1992 /* Get endpoint status */ 1993 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 1994 1995 /* 1996 * This should never happen, but protect against writing to the 1997 * buffer when full. 1998 */ 1999 if (epstatus & EP_SEL_F) 2000 return; 2001 2002 if (ep->is_in) { 2003 udc_send_in_zlp(udc, ep); 2004 uda_disable_hwepint(udc, ep->hwep_num); 2005 } else 2006 return; 2007 2008 /* If there isn't a request waiting, something went wrong */ 2009 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 2010 if (req) { 2011 done(ep, req, 0); 2012 2013 /* Start another request if ready */ 2014 if (!list_empty(&ep->queue)) { 2015 if (ep->is_in) 2016 udc_ep_in_req_dma(udc, ep); 2017 else 2018 udc_ep_out_req_dma(udc, ep); 2019 } else 2020 ep->req_pending = 0; 2021 } 2022 } 2023 2024 2025 /* DMA end of transfer completion */ 2026 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 2027 { 2028 u32 status, epstatus; 2029 struct lpc32xx_request *req; 2030 struct lpc32xx_usbd_dd_gad *dd; 2031 2032 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2033 ep->totalints++; 2034 #endif 2035 2036 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 2037 if (!req) { 2038 ep_err(ep, "DMA interrupt on no req!\n"); 2039 return; 2040 } 2041 dd = req->dd_desc_ptr; 2042 2043 /* DMA descriptor should always be retired for this call */ 2044 if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) 2045 ep_warn(ep, "DMA descriptor did not retire\n"); 2046 2047 /* Disable DMA */ 2048 udc_ep_dma_disable(udc, ep->hwep_num); 2049 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); 2050 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 2051 2052 /* System error? */ 2053 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & 2054 (1 << ep->hwep_num)) { 2055 writel((1 << ep->hwep_num), 2056 USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 2057 ep_err(ep, "AHB critical error!\n"); 2058 ep->req_pending = 0; 2059 2060 /* The error could have occurred on a packet of a multipacket 2061 * transfer, so recovering the transfer is not possible. Close 2062 * the request with an error */ 2063 done(ep, req, -ECONNABORTED); 2064 return; 2065 } 2066 2067 /* Handle the current DD's status */ 2068 status = dd->dd_status; 2069 switch (status & DD_STATUS_STS_MASK) { 2070 case DD_STATUS_STS_NS: 2071 /* DD not serviced? This shouldn't happen! */ 2072 ep->req_pending = 0; 2073 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", 2074 status); 2075 2076 done(ep, req, -ECONNABORTED); 2077 return; 2078 2079 case DD_STATUS_STS_BS: 2080 /* Interrupt only fires on EOT - This shouldn't happen! */ 2081 ep->req_pending = 0; 2082 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", 2083 status); 2084 done(ep, req, -ECONNABORTED); 2085 return; 2086 2087 case DD_STATUS_STS_NC: 2088 case DD_STATUS_STS_DUR: 2089 /* Really just a short packet, not an underrun */ 2090 /* This is a good status and what we expect */ 2091 break; 2092 2093 default: 2094 /* Data overrun, system error, or unknown */ 2095 ep->req_pending = 0; 2096 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", 2097 status); 2098 done(ep, req, -ECONNABORTED); 2099 return; 2100 } 2101 2102 /* ISO endpoints are handled differently */ 2103 if (ep->eptype == EP_ISO_TYPE) { 2104 if (ep->is_in) 2105 req->req.actual = req->req.length; 2106 else 2107 req->req.actual = dd->iso_status[0] & 0xFFFF; 2108 } else 2109 req->req.actual += DD_STATUS_CURDMACNT(status); 2110 2111 /* Send a ZLP if necessary. This will be done for non-int 2112 * packets which have a size that is a divisor of MAXP */ 2113 if (req->send_zlp) { 2114 /* 2115 * If at least 1 buffer is available, send the ZLP now. 2116 * Otherwise, the ZLP send needs to be deferred until a 2117 * buffer is available. 2118 */ 2119 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { 2120 udc_clearep_getsts(udc, ep->hwep_num); 2121 uda_enable_hwepint(udc, ep->hwep_num); 2122 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 2123 2124 /* Let the EP interrupt handle the ZLP */ 2125 return; 2126 } else 2127 udc_send_in_zlp(udc, ep); 2128 } 2129 2130 /* Transfer request is complete */ 2131 done(ep, req, 0); 2132 2133 /* Start another request if ready */ 2134 udc_clearep_getsts(udc, ep->hwep_num); 2135 if (!list_empty((&ep->queue))) { 2136 if (ep->is_in) 2137 udc_ep_in_req_dma(udc, ep); 2138 else 2139 udc_ep_out_req_dma(udc, ep); 2140 } else 2141 ep->req_pending = 0; 2142 2143 } 2144 2145 /* 2146 * 2147 * Endpoint 0 functions 2148 * 2149 */ 2150 static void udc_handle_dev(struct lpc32xx_udc *udc) 2151 { 2152 u32 tmp; 2153 2154 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); 2155 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); 2156 2157 if (tmp & DEV_RST) 2158 uda_usb_reset(udc); 2159 else if (tmp & DEV_CON_CH) 2160 uda_power_event(udc, (tmp & DEV_CON)); 2161 else if (tmp & DEV_SUS_CH) { 2162 if (tmp & DEV_SUS) { 2163 if (udc->vbus == 0) 2164 stop_activity(udc); 2165 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2166 udc->driver) { 2167 /* Power down transceiver */ 2168 udc->poweron = 0; 2169 schedule_work(&udc->pullup_job); 2170 uda_resm_susp_event(udc, 1); 2171 } 2172 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2173 udc->driver && udc->vbus) { 2174 uda_resm_susp_event(udc, 0); 2175 /* Power up transceiver */ 2176 udc->poweron = 1; 2177 schedule_work(&udc->pullup_job); 2178 } 2179 } 2180 } 2181 2182 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) 2183 { 2184 struct lpc32xx_ep *ep; 2185 u32 ep0buff = 0, tmp; 2186 2187 switch (reqtype & USB_RECIP_MASK) { 2188 case USB_RECIP_INTERFACE: 2189 break; /* Not supported */ 2190 2191 case USB_RECIP_DEVICE: 2192 ep0buff = udc->gadget.is_selfpowered; 2193 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) 2194 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); 2195 break; 2196 2197 case USB_RECIP_ENDPOINT: 2198 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2199 ep = &udc->ep[tmp]; 2200 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS)) 2201 return -EOPNOTSUPP; 2202 2203 if (wIndex & USB_DIR_IN) { 2204 if (!ep->is_in) 2205 return -EOPNOTSUPP; /* Something's wrong */ 2206 } else if (ep->is_in) 2207 return -EOPNOTSUPP; /* Not an IN endpoint */ 2208 2209 /* Get status of the endpoint */ 2210 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); 2211 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); 2212 2213 if (tmp & EP_SEL_ST) 2214 ep0buff = (1 << USB_ENDPOINT_HALT); 2215 else 2216 ep0buff = 0; 2217 break; 2218 2219 default: 2220 break; 2221 } 2222 2223 /* Return data */ 2224 udc_write_hwep(udc, EP_IN, &ep0buff, 2); 2225 2226 return 0; 2227 } 2228 2229 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) 2230 { 2231 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; 2232 struct usb_ctrlrequest ctrlpkt; 2233 int i, bytes; 2234 u16 wIndex, wValue, wLength, reqtype, req, tmp; 2235 2236 /* Nuke previous transfers */ 2237 nuke(ep0, -EPROTO); 2238 2239 /* Get setup packet */ 2240 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); 2241 if (bytes != 8) { 2242 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", 2243 bytes); 2244 return; 2245 } 2246 2247 /* Native endianness */ 2248 wIndex = le16_to_cpu(ctrlpkt.wIndex); 2249 wValue = le16_to_cpu(ctrlpkt.wValue); 2250 wLength = le16_to_cpu(ctrlpkt.wLength); 2251 reqtype = le16_to_cpu(ctrlpkt.bRequestType); 2252 2253 /* Set direction of EP0 */ 2254 if (likely(reqtype & USB_DIR_IN)) 2255 ep0->is_in = 1; 2256 else 2257 ep0->is_in = 0; 2258 2259 /* Handle SETUP packet */ 2260 req = le16_to_cpu(ctrlpkt.bRequest); 2261 switch (req) { 2262 case USB_REQ_CLEAR_FEATURE: 2263 case USB_REQ_SET_FEATURE: 2264 switch (reqtype) { 2265 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): 2266 if (wValue != USB_DEVICE_REMOTE_WAKEUP) 2267 goto stall; /* Nothing else handled */ 2268 2269 /* Tell board about event */ 2270 if (req == USB_REQ_CLEAR_FEATURE) 2271 udc->dev_status &= 2272 ~(1 << USB_DEVICE_REMOTE_WAKEUP); 2273 else 2274 udc->dev_status |= 2275 (1 << USB_DEVICE_REMOTE_WAKEUP); 2276 uda_remwkp_cgh(udc); 2277 goto zlp_send; 2278 2279 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): 2280 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2281 if ((wValue != USB_ENDPOINT_HALT) || 2282 (tmp >= NUM_ENDPOINTS)) 2283 break; 2284 2285 /* Find hardware endpoint from logical endpoint */ 2286 ep = &udc->ep[tmp]; 2287 tmp = ep->hwep_num; 2288 if (tmp == 0) 2289 break; 2290 2291 if (req == USB_REQ_SET_FEATURE) 2292 udc_stall_hwep(udc, tmp); 2293 else if (!ep->wedge) 2294 udc_clrstall_hwep(udc, tmp); 2295 2296 goto zlp_send; 2297 2298 default: 2299 break; 2300 } 2301 2302 2303 case USB_REQ_SET_ADDRESS: 2304 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { 2305 udc_set_address(udc, wValue); 2306 goto zlp_send; 2307 } 2308 break; 2309 2310 case USB_REQ_GET_STATUS: 2311 udc_get_status(udc, reqtype, wIndex); 2312 return; 2313 2314 default: 2315 break; /* Let GadgetFS handle the descriptor instead */ 2316 } 2317 2318 if (likely(udc->driver)) { 2319 /* device-2-host (IN) or no data setup command, process 2320 * immediately */ 2321 spin_unlock(&udc->lock); 2322 i = udc->driver->setup(&udc->gadget, &ctrlpkt); 2323 2324 spin_lock(&udc->lock); 2325 if (req == USB_REQ_SET_CONFIGURATION) { 2326 /* Configuration is set after endpoints are realized */ 2327 if (wValue) { 2328 /* Set configuration */ 2329 udc_set_device_configured(udc); 2330 2331 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2332 DAT_WR_BYTE(AP_CLK | 2333 INAK_BI | INAK_II)); 2334 } else { 2335 /* Clear configuration */ 2336 udc_set_device_unconfigured(udc); 2337 2338 /* Disable NAK interrupts */ 2339 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2340 DAT_WR_BYTE(AP_CLK)); 2341 } 2342 } 2343 2344 if (i < 0) { 2345 /* setup processing failed, force stall */ 2346 dev_dbg(udc->dev, 2347 "req %02x.%02x protocol STALL; stat %d\n", 2348 reqtype, req, i); 2349 udc->ep0state = WAIT_FOR_SETUP; 2350 goto stall; 2351 } 2352 } 2353 2354 if (!ep0->is_in) 2355 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ 2356 2357 return; 2358 2359 stall: 2360 udc_stall_hwep(udc, EP_IN); 2361 return; 2362 2363 zlp_send: 2364 udc_ep0_send_zlp(udc); 2365 return; 2366 } 2367 2368 /* IN endpoint 0 transfer */ 2369 static void udc_handle_ep0_in(struct lpc32xx_udc *udc) 2370 { 2371 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2372 u32 epstatus; 2373 2374 /* Clear EP interrupt */ 2375 epstatus = udc_clearep_getsts(udc, EP_IN); 2376 2377 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2378 ep0->totalints++; 2379 #endif 2380 2381 /* Stalled? Clear stall and reset buffers */ 2382 if (epstatus & EP_SEL_ST) { 2383 udc_clrstall_hwep(udc, EP_IN); 2384 nuke(ep0, -ECONNABORTED); 2385 udc->ep0state = WAIT_FOR_SETUP; 2386 return; 2387 } 2388 2389 /* Is a buffer available? */ 2390 if (!(epstatus & EP_SEL_F)) { 2391 /* Handle based on current state */ 2392 if (udc->ep0state == DATA_IN) 2393 udc_ep0_in_req(udc); 2394 else { 2395 /* Unknown state for EP0 oe end of DATA IN phase */ 2396 nuke(ep0, -ECONNABORTED); 2397 udc->ep0state = WAIT_FOR_SETUP; 2398 } 2399 } 2400 } 2401 2402 /* OUT endpoint 0 transfer */ 2403 static void udc_handle_ep0_out(struct lpc32xx_udc *udc) 2404 { 2405 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2406 u32 epstatus; 2407 2408 /* Clear EP interrupt */ 2409 epstatus = udc_clearep_getsts(udc, EP_OUT); 2410 2411 2412 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2413 ep0->totalints++; 2414 #endif 2415 2416 /* Stalled? */ 2417 if (epstatus & EP_SEL_ST) { 2418 udc_clrstall_hwep(udc, EP_OUT); 2419 nuke(ep0, -ECONNABORTED); 2420 udc->ep0state = WAIT_FOR_SETUP; 2421 return; 2422 } 2423 2424 /* A NAK may occur if a packet couldn't be received yet */ 2425 if (epstatus & EP_SEL_EPN) 2426 return; 2427 /* Setup packet incoming? */ 2428 if (epstatus & EP_SEL_STP) { 2429 nuke(ep0, 0); 2430 udc->ep0state = WAIT_FOR_SETUP; 2431 } 2432 2433 /* Data available? */ 2434 if (epstatus & EP_SEL_F) 2435 /* Handle based on current state */ 2436 switch (udc->ep0state) { 2437 case WAIT_FOR_SETUP: 2438 udc_handle_ep0_setup(udc); 2439 break; 2440 2441 case DATA_OUT: 2442 udc_ep0_out_req(udc); 2443 break; 2444 2445 default: 2446 /* Unknown state for EP0 */ 2447 nuke(ep0, -ECONNABORTED); 2448 udc->ep0state = WAIT_FOR_SETUP; 2449 } 2450 } 2451 2452 /* Must be called without lock */ 2453 static int lpc32xx_get_frame(struct usb_gadget *gadget) 2454 { 2455 int frame; 2456 unsigned long flags; 2457 struct lpc32xx_udc *udc = to_udc(gadget); 2458 2459 if (!udc->clocked) 2460 return -EINVAL; 2461 2462 spin_lock_irqsave(&udc->lock, flags); 2463 2464 frame = (int) udc_get_current_frame(udc); 2465 2466 spin_unlock_irqrestore(&udc->lock, flags); 2467 2468 return frame; 2469 } 2470 2471 static int lpc32xx_wakeup(struct usb_gadget *gadget) 2472 { 2473 return -ENOTSUPP; 2474 } 2475 2476 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) 2477 { 2478 gadget->is_selfpowered = (is_on != 0); 2479 2480 return 0; 2481 } 2482 2483 /* 2484 * vbus is here! turn everything on that's ready 2485 * Must be called without lock 2486 */ 2487 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) 2488 { 2489 unsigned long flags; 2490 struct lpc32xx_udc *udc = to_udc(gadget); 2491 2492 spin_lock_irqsave(&udc->lock, flags); 2493 2494 /* Doesn't need lock */ 2495 if (udc->driver) { 2496 udc_clk_set(udc, 1); 2497 udc_enable(udc); 2498 pullup(udc, is_active); 2499 } else { 2500 stop_activity(udc); 2501 pullup(udc, 0); 2502 2503 spin_unlock_irqrestore(&udc->lock, flags); 2504 /* 2505 * Wait for all the endpoints to disable, 2506 * before disabling clocks. Don't wait if 2507 * endpoints are not enabled. 2508 */ 2509 if (atomic_read(&udc->enabled_ep_cnt)) 2510 wait_event_interruptible(udc->ep_disable_wait_queue, 2511 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2512 2513 spin_lock_irqsave(&udc->lock, flags); 2514 2515 udc_clk_set(udc, 0); 2516 } 2517 2518 spin_unlock_irqrestore(&udc->lock, flags); 2519 2520 return 0; 2521 } 2522 2523 /* Can be called with or without lock */ 2524 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) 2525 { 2526 struct lpc32xx_udc *udc = to_udc(gadget); 2527 2528 /* Doesn't need lock */ 2529 pullup(udc, is_on); 2530 2531 return 0; 2532 } 2533 2534 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *); 2535 static int lpc32xx_stop(struct usb_gadget *); 2536 2537 static const struct usb_gadget_ops lpc32xx_udc_ops = { 2538 .get_frame = lpc32xx_get_frame, 2539 .wakeup = lpc32xx_wakeup, 2540 .set_selfpowered = lpc32xx_set_selfpowered, 2541 .vbus_session = lpc32xx_vbus_session, 2542 .pullup = lpc32xx_pullup, 2543 .udc_start = lpc32xx_start, 2544 .udc_stop = lpc32xx_stop, 2545 }; 2546 2547 static void nop_release(struct device *dev) 2548 { 2549 /* nothing to free */ 2550 } 2551 2552 static const struct lpc32xx_udc controller_template = { 2553 .gadget = { 2554 .ops = &lpc32xx_udc_ops, 2555 .name = driver_name, 2556 .dev = { 2557 .init_name = "gadget", 2558 .release = nop_release, 2559 } 2560 }, 2561 .ep[0] = { 2562 .ep = { 2563 .name = "ep0", 2564 .ops = &lpc32xx_ep_ops, 2565 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, 2566 USB_EP_CAPS_DIR_ALL), 2567 }, 2568 .maxpacket = 64, 2569 .hwep_num_base = 0, 2570 .hwep_num = 0, /* Can be 0 or 1, has special handling */ 2571 .lep = 0, 2572 .eptype = EP_CTL_TYPE, 2573 }, 2574 .ep[1] = { 2575 .ep = { 2576 .name = "ep1-int", 2577 .ops = &lpc32xx_ep_ops, 2578 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2579 USB_EP_CAPS_DIR_ALL), 2580 }, 2581 .maxpacket = 64, 2582 .hwep_num_base = 2, 2583 .hwep_num = 0, /* 2 or 3, will be set later */ 2584 .lep = 1, 2585 .eptype = EP_INT_TYPE, 2586 }, 2587 .ep[2] = { 2588 .ep = { 2589 .name = "ep2-bulk", 2590 .ops = &lpc32xx_ep_ops, 2591 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2592 USB_EP_CAPS_DIR_ALL), 2593 }, 2594 .maxpacket = 64, 2595 .hwep_num_base = 4, 2596 .hwep_num = 0, /* 4 or 5, will be set later */ 2597 .lep = 2, 2598 .eptype = EP_BLK_TYPE, 2599 }, 2600 .ep[3] = { 2601 .ep = { 2602 .name = "ep3-iso", 2603 .ops = &lpc32xx_ep_ops, 2604 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2605 USB_EP_CAPS_DIR_ALL), 2606 }, 2607 .maxpacket = 1023, 2608 .hwep_num_base = 6, 2609 .hwep_num = 0, /* 6 or 7, will be set later */ 2610 .lep = 3, 2611 .eptype = EP_ISO_TYPE, 2612 }, 2613 .ep[4] = { 2614 .ep = { 2615 .name = "ep4-int", 2616 .ops = &lpc32xx_ep_ops, 2617 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2618 USB_EP_CAPS_DIR_ALL), 2619 }, 2620 .maxpacket = 64, 2621 .hwep_num_base = 8, 2622 .hwep_num = 0, /* 8 or 9, will be set later */ 2623 .lep = 4, 2624 .eptype = EP_INT_TYPE, 2625 }, 2626 .ep[5] = { 2627 .ep = { 2628 .name = "ep5-bulk", 2629 .ops = &lpc32xx_ep_ops, 2630 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2631 USB_EP_CAPS_DIR_ALL), 2632 }, 2633 .maxpacket = 64, 2634 .hwep_num_base = 10, 2635 .hwep_num = 0, /* 10 or 11, will be set later */ 2636 .lep = 5, 2637 .eptype = EP_BLK_TYPE, 2638 }, 2639 .ep[6] = { 2640 .ep = { 2641 .name = "ep6-iso", 2642 .ops = &lpc32xx_ep_ops, 2643 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2644 USB_EP_CAPS_DIR_ALL), 2645 }, 2646 .maxpacket = 1023, 2647 .hwep_num_base = 12, 2648 .hwep_num = 0, /* 12 or 13, will be set later */ 2649 .lep = 6, 2650 .eptype = EP_ISO_TYPE, 2651 }, 2652 .ep[7] = { 2653 .ep = { 2654 .name = "ep7-int", 2655 .ops = &lpc32xx_ep_ops, 2656 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2657 USB_EP_CAPS_DIR_ALL), 2658 }, 2659 .maxpacket = 64, 2660 .hwep_num_base = 14, 2661 .hwep_num = 0, 2662 .lep = 7, 2663 .eptype = EP_INT_TYPE, 2664 }, 2665 .ep[8] = { 2666 .ep = { 2667 .name = "ep8-bulk", 2668 .ops = &lpc32xx_ep_ops, 2669 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2670 USB_EP_CAPS_DIR_ALL), 2671 }, 2672 .maxpacket = 64, 2673 .hwep_num_base = 16, 2674 .hwep_num = 0, 2675 .lep = 8, 2676 .eptype = EP_BLK_TYPE, 2677 }, 2678 .ep[9] = { 2679 .ep = { 2680 .name = "ep9-iso", 2681 .ops = &lpc32xx_ep_ops, 2682 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2683 USB_EP_CAPS_DIR_ALL), 2684 }, 2685 .maxpacket = 1023, 2686 .hwep_num_base = 18, 2687 .hwep_num = 0, 2688 .lep = 9, 2689 .eptype = EP_ISO_TYPE, 2690 }, 2691 .ep[10] = { 2692 .ep = { 2693 .name = "ep10-int", 2694 .ops = &lpc32xx_ep_ops, 2695 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2696 USB_EP_CAPS_DIR_ALL), 2697 }, 2698 .maxpacket = 64, 2699 .hwep_num_base = 20, 2700 .hwep_num = 0, 2701 .lep = 10, 2702 .eptype = EP_INT_TYPE, 2703 }, 2704 .ep[11] = { 2705 .ep = { 2706 .name = "ep11-bulk", 2707 .ops = &lpc32xx_ep_ops, 2708 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2709 USB_EP_CAPS_DIR_ALL), 2710 }, 2711 .maxpacket = 64, 2712 .hwep_num_base = 22, 2713 .hwep_num = 0, 2714 .lep = 11, 2715 .eptype = EP_BLK_TYPE, 2716 }, 2717 .ep[12] = { 2718 .ep = { 2719 .name = "ep12-iso", 2720 .ops = &lpc32xx_ep_ops, 2721 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2722 USB_EP_CAPS_DIR_ALL), 2723 }, 2724 .maxpacket = 1023, 2725 .hwep_num_base = 24, 2726 .hwep_num = 0, 2727 .lep = 12, 2728 .eptype = EP_ISO_TYPE, 2729 }, 2730 .ep[13] = { 2731 .ep = { 2732 .name = "ep13-int", 2733 .ops = &lpc32xx_ep_ops, 2734 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2735 USB_EP_CAPS_DIR_ALL), 2736 }, 2737 .maxpacket = 64, 2738 .hwep_num_base = 26, 2739 .hwep_num = 0, 2740 .lep = 13, 2741 .eptype = EP_INT_TYPE, 2742 }, 2743 .ep[14] = { 2744 .ep = { 2745 .name = "ep14-bulk", 2746 .ops = &lpc32xx_ep_ops, 2747 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2748 USB_EP_CAPS_DIR_ALL), 2749 }, 2750 .maxpacket = 64, 2751 .hwep_num_base = 28, 2752 .hwep_num = 0, 2753 .lep = 14, 2754 .eptype = EP_BLK_TYPE, 2755 }, 2756 .ep[15] = { 2757 .ep = { 2758 .name = "ep15-bulk", 2759 .ops = &lpc32xx_ep_ops, 2760 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2761 USB_EP_CAPS_DIR_ALL), 2762 }, 2763 .maxpacket = 1023, 2764 .hwep_num_base = 30, 2765 .hwep_num = 0, 2766 .lep = 15, 2767 .eptype = EP_BLK_TYPE, 2768 }, 2769 }; 2770 2771 /* ISO and status interrupts */ 2772 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) 2773 { 2774 u32 tmp, devstat; 2775 struct lpc32xx_udc *udc = _udc; 2776 2777 spin_lock(&udc->lock); 2778 2779 /* Read the device status register */ 2780 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); 2781 2782 devstat &= ~USBD_EP_FAST; 2783 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); 2784 devstat = devstat & udc->enabled_devints; 2785 2786 /* Device specific handling needed? */ 2787 if (devstat & USBD_DEV_STAT) 2788 udc_handle_dev(udc); 2789 2790 /* Start of frame? (devstat & FRAME_INT): 2791 * The frame interrupt isn't really needed for ISO support, 2792 * as the driver will queue the necessary packets */ 2793 2794 /* Error? */ 2795 if (devstat & ERR_INT) { 2796 /* All types of errors, from cable removal during transfer to 2797 * misc protocol and bit errors. These are mostly for just info, 2798 * as the USB hardware will work around these. If these errors 2799 * happen alot, something is wrong. */ 2800 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); 2801 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); 2802 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); 2803 } 2804 2805 spin_unlock(&udc->lock); 2806 2807 return IRQ_HANDLED; 2808 } 2809 2810 /* EP interrupts */ 2811 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) 2812 { 2813 u32 tmp; 2814 struct lpc32xx_udc *udc = _udc; 2815 2816 spin_lock(&udc->lock); 2817 2818 /* Read the device status register */ 2819 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); 2820 2821 /* Endpoints */ 2822 tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); 2823 2824 /* Special handling for EP0 */ 2825 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2826 /* Handle EP0 IN */ 2827 if (tmp & (EP_MASK_SEL(0, EP_IN))) 2828 udc_handle_ep0_in(udc); 2829 2830 /* Handle EP0 OUT */ 2831 if (tmp & (EP_MASK_SEL(0, EP_OUT))) 2832 udc_handle_ep0_out(udc); 2833 } 2834 2835 /* All other EPs */ 2836 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2837 int i; 2838 2839 /* Handle other EP interrupts */ 2840 for (i = 1; i < NUM_ENDPOINTS; i++) { 2841 if (tmp & (1 << udc->ep[i].hwep_num)) 2842 udc_handle_eps(udc, &udc->ep[i]); 2843 } 2844 } 2845 2846 spin_unlock(&udc->lock); 2847 2848 return IRQ_HANDLED; 2849 } 2850 2851 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) 2852 { 2853 struct lpc32xx_udc *udc = _udc; 2854 2855 int i; 2856 u32 tmp; 2857 2858 spin_lock(&udc->lock); 2859 2860 /* Handle EP DMA EOT interrupts */ 2861 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | 2862 (readl(USBD_EPDMAST(udc->udp_baseaddr)) & 2863 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | 2864 readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); 2865 for (i = 1; i < NUM_ENDPOINTS; i++) { 2866 if (tmp & (1 << udc->ep[i].hwep_num)) 2867 udc_handle_dma_ep(udc, &udc->ep[i]); 2868 } 2869 2870 spin_unlock(&udc->lock); 2871 2872 return IRQ_HANDLED; 2873 } 2874 2875 /* 2876 * 2877 * VBUS detection, pullup handler, and Gadget cable state notification 2878 * 2879 */ 2880 static void vbus_work(struct work_struct *work) 2881 { 2882 u8 value; 2883 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc, 2884 vbus_job); 2885 2886 if (udc->enabled != 0) { 2887 /* Discharge VBUS real quick */ 2888 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2889 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 2890 2891 /* Give VBUS some time (100mS) to discharge */ 2892 msleep(100); 2893 2894 /* Disable VBUS discharge resistor */ 2895 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2896 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 2897 OTG1_VBUS_DISCHRG); 2898 2899 /* Clear interrupt */ 2900 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2901 ISP1301_I2C_INTERRUPT_LATCH | 2902 ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2903 2904 /* Get the VBUS status from the transceiver */ 2905 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, 2906 ISP1301_I2C_INTERRUPT_SOURCE); 2907 2908 /* VBUS on or off? */ 2909 if (value & INT_SESS_VLD) 2910 udc->vbus = 1; 2911 else 2912 udc->vbus = 0; 2913 2914 /* VBUS changed? */ 2915 if (udc->last_vbus != udc->vbus) { 2916 udc->last_vbus = udc->vbus; 2917 lpc32xx_vbus_session(&udc->gadget, udc->vbus); 2918 } 2919 } 2920 2921 /* Re-enable after completion */ 2922 enable_irq(udc->udp_irq[IRQ_USB_ATX]); 2923 } 2924 2925 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) 2926 { 2927 struct lpc32xx_udc *udc = _udc; 2928 2929 /* Defer handling of VBUS IRQ to work queue */ 2930 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]); 2931 schedule_work(&udc->vbus_job); 2932 2933 return IRQ_HANDLED; 2934 } 2935 2936 static int lpc32xx_start(struct usb_gadget *gadget, 2937 struct usb_gadget_driver *driver) 2938 { 2939 struct lpc32xx_udc *udc = to_udc(gadget); 2940 int i; 2941 2942 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) { 2943 dev_err(udc->dev, "bad parameter.\n"); 2944 return -EINVAL; 2945 } 2946 2947 if (udc->driver) { 2948 dev_err(udc->dev, "UDC already has a gadget driver\n"); 2949 return -EBUSY; 2950 } 2951 2952 udc->driver = driver; 2953 udc->gadget.dev.of_node = udc->dev->of_node; 2954 udc->enabled = 1; 2955 udc->gadget.is_selfpowered = 1; 2956 udc->vbus = 0; 2957 2958 /* Force VBUS process once to check for cable insertion */ 2959 udc->last_vbus = udc->vbus = 0; 2960 schedule_work(&udc->vbus_job); 2961 2962 /* Do not re-enable ATX IRQ (3) */ 2963 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++) 2964 enable_irq(udc->udp_irq[i]); 2965 2966 return 0; 2967 } 2968 2969 static int lpc32xx_stop(struct usb_gadget *gadget) 2970 { 2971 int i; 2972 struct lpc32xx_udc *udc = to_udc(gadget); 2973 2974 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) 2975 disable_irq(udc->udp_irq[i]); 2976 2977 if (udc->clocked) { 2978 spin_lock(&udc->lock); 2979 stop_activity(udc); 2980 spin_unlock(&udc->lock); 2981 2982 /* 2983 * Wait for all the endpoints to disable, 2984 * before disabling clocks. Don't wait if 2985 * endpoints are not enabled. 2986 */ 2987 if (atomic_read(&udc->enabled_ep_cnt)) 2988 wait_event_interruptible(udc->ep_disable_wait_queue, 2989 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2990 2991 spin_lock(&udc->lock); 2992 udc_clk_set(udc, 0); 2993 spin_unlock(&udc->lock); 2994 } 2995 2996 udc->enabled = 0; 2997 udc->driver = NULL; 2998 2999 return 0; 3000 } 3001 3002 static void lpc32xx_udc_shutdown(struct platform_device *dev) 3003 { 3004 /* Force disconnect on reboot */ 3005 struct lpc32xx_udc *udc = platform_get_drvdata(dev); 3006 3007 pullup(udc, 0); 3008 } 3009 3010 /* 3011 * Callbacks to be overridden by options passed via OF (TODO) 3012 */ 3013 3014 static void lpc32xx_usbd_conn_chg(int conn) 3015 { 3016 /* Do nothing, it might be nice to enable an LED 3017 * based on conn state being !0 */ 3018 } 3019 3020 static void lpc32xx_usbd_susp_chg(int susp) 3021 { 3022 /* Device suspend if susp != 0 */ 3023 } 3024 3025 static void lpc32xx_rmwkup_chg(int remote_wakup_enable) 3026 { 3027 /* Enable or disable USB remote wakeup */ 3028 } 3029 3030 struct lpc32xx_usbd_cfg lpc32xx_usbddata = { 3031 .vbus_drv_pol = 0, 3032 .conn_chgb = &lpc32xx_usbd_conn_chg, 3033 .susp_chgb = &lpc32xx_usbd_susp_chg, 3034 .rmwk_chgb = &lpc32xx_rmwkup_chg, 3035 }; 3036 3037 3038 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; 3039 3040 static int lpc32xx_udc_probe(struct platform_device *pdev) 3041 { 3042 struct device *dev = &pdev->dev; 3043 struct lpc32xx_udc *udc; 3044 int retval, i; 3045 struct resource *res; 3046 dma_addr_t dma_handle; 3047 struct device_node *isp1301_node; 3048 3049 udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL); 3050 if (!udc) 3051 return -ENOMEM; 3052 3053 for (i = 0; i <= 15; i++) 3054 udc->ep[i].udc = udc; 3055 udc->gadget.ep0 = &udc->ep[0].ep; 3056 3057 /* init software state */ 3058 udc->gadget.dev.parent = dev; 3059 udc->pdev = pdev; 3060 udc->dev = &pdev->dev; 3061 udc->enabled = 0; 3062 3063 if (pdev->dev.of_node) { 3064 isp1301_node = of_parse_phandle(pdev->dev.of_node, 3065 "transceiver", 0); 3066 } else { 3067 isp1301_node = NULL; 3068 } 3069 3070 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); 3071 if (!udc->isp1301_i2c_client) { 3072 retval = -EPROBE_DEFER; 3073 goto phy_fail; 3074 } 3075 3076 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", 3077 udc->isp1301_i2c_client->addr); 3078 3079 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; 3080 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3081 if (retval) 3082 goto resource_fail; 3083 3084 udc->board = &lpc32xx_usbddata; 3085 3086 /* 3087 * Resources are mapped as follows: 3088 * IORESOURCE_MEM, base address and size of USB space 3089 * IORESOURCE_IRQ, USB device low priority interrupt number 3090 * IORESOURCE_IRQ, USB device high priority interrupt number 3091 * IORESOURCE_IRQ, USB device interrupt number 3092 * IORESOURCE_IRQ, USB transceiver interrupt number 3093 */ 3094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3095 if (!res) { 3096 retval = -ENXIO; 3097 goto resource_fail; 3098 } 3099 3100 spin_lock_init(&udc->lock); 3101 3102 /* Get IRQs */ 3103 for (i = 0; i < 4; i++) { 3104 udc->udp_irq[i] = platform_get_irq(pdev, i); 3105 if (udc->udp_irq[i] < 0) { 3106 dev_err(udc->dev, 3107 "irq resource %d not available!\n", i); 3108 retval = udc->udp_irq[i]; 3109 goto irq_fail; 3110 } 3111 } 3112 3113 udc->io_p_start = res->start; 3114 udc->io_p_size = resource_size(res); 3115 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) { 3116 dev_err(udc->dev, "someone's using UDC memory\n"); 3117 retval = -EBUSY; 3118 goto request_mem_region_fail; 3119 } 3120 3121 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size); 3122 if (!udc->udp_baseaddr) { 3123 retval = -ENOMEM; 3124 dev_err(udc->dev, "IO map failure\n"); 3125 goto io_map_fail; 3126 } 3127 3128 /* Enable AHB slave USB clock, needed for further USB clock control */ 3129 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL); 3130 3131 /* Get required clocks */ 3132 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5"); 3133 if (IS_ERR(udc->usb_pll_clk)) { 3134 dev_err(udc->dev, "failed to acquire USB PLL\n"); 3135 retval = PTR_ERR(udc->usb_pll_clk); 3136 goto pll_get_fail; 3137 } 3138 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd"); 3139 if (IS_ERR(udc->usb_slv_clk)) { 3140 dev_err(udc->dev, "failed to acquire USB device clock\n"); 3141 retval = PTR_ERR(udc->usb_slv_clk); 3142 goto usb_clk_get_fail; 3143 } 3144 udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg"); 3145 if (IS_ERR(udc->usb_otg_clk)) { 3146 dev_err(udc->dev, "failed to acquire USB otg clock\n"); 3147 retval = PTR_ERR(udc->usb_otg_clk); 3148 goto usb_otg_clk_get_fail; 3149 } 3150 3151 /* Setup PLL clock to 48MHz */ 3152 retval = clk_enable(udc->usb_pll_clk); 3153 if (retval < 0) { 3154 dev_err(udc->dev, "failed to start USB PLL\n"); 3155 goto pll_enable_fail; 3156 } 3157 3158 retval = clk_set_rate(udc->usb_pll_clk, 48000); 3159 if (retval < 0) { 3160 dev_err(udc->dev, "failed to set USB clock rate\n"); 3161 goto pll_set_fail; 3162 } 3163 3164 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL); 3165 3166 /* Enable USB device clock */ 3167 retval = clk_enable(udc->usb_slv_clk); 3168 if (retval < 0) { 3169 dev_err(udc->dev, "failed to start USB device clock\n"); 3170 goto usb_clk_enable_fail; 3171 } 3172 3173 /* Enable USB OTG clock */ 3174 retval = clk_enable(udc->usb_otg_clk); 3175 if (retval < 0) { 3176 dev_err(udc->dev, "failed to start USB otg clock\n"); 3177 goto usb_otg_clk_enable_fail; 3178 } 3179 3180 /* Setup deferred workqueue data */ 3181 udc->poweron = udc->pullup = 0; 3182 INIT_WORK(&udc->pullup_job, pullup_work); 3183 INIT_WORK(&udc->vbus_job, vbus_work); 3184 #ifdef CONFIG_PM 3185 INIT_WORK(&udc->power_job, power_work); 3186 #endif 3187 3188 /* All clocks are now on */ 3189 udc->clocked = 1; 3190 3191 isp1301_udc_configure(udc); 3192 /* Allocate memory for the UDCA */ 3193 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3194 &dma_handle, 3195 (GFP_KERNEL | GFP_DMA)); 3196 if (!udc->udca_v_base) { 3197 dev_err(udc->dev, "error getting UDCA region\n"); 3198 retval = -ENOMEM; 3199 goto i2c_fail; 3200 } 3201 udc->udca_p_base = dma_handle; 3202 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", 3203 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); 3204 3205 /* Setup the DD DMA memory pool */ 3206 udc->dd_cache = dma_pool_create("udc_dd", udc->dev, 3207 sizeof(struct lpc32xx_usbd_dd_gad), 3208 sizeof(u32), 0); 3209 if (!udc->dd_cache) { 3210 dev_err(udc->dev, "error getting DD DMA region\n"); 3211 retval = -ENOMEM; 3212 goto dma_alloc_fail; 3213 } 3214 3215 /* Clear USB peripheral and initialize gadget endpoints */ 3216 udc_disable(udc); 3217 udc_reinit(udc); 3218 3219 /* Request IRQs - low and high priority USB device IRQs are routed to 3220 * the same handler, while the DMA interrupt is routed elsewhere */ 3221 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq, 3222 0, "udc_lp", udc); 3223 if (retval < 0) { 3224 dev_err(udc->dev, "LP request irq %d failed\n", 3225 udc->udp_irq[IRQ_USB_LP]); 3226 goto irq_lp_fail; 3227 } 3228 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq, 3229 0, "udc_hp", udc); 3230 if (retval < 0) { 3231 dev_err(udc->dev, "HP request irq %d failed\n", 3232 udc->udp_irq[IRQ_USB_HP]); 3233 goto irq_hp_fail; 3234 } 3235 3236 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA], 3237 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); 3238 if (retval < 0) { 3239 dev_err(udc->dev, "DEV request irq %d failed\n", 3240 udc->udp_irq[IRQ_USB_DEVDMA]); 3241 goto irq_dev_fail; 3242 } 3243 3244 /* The transceiver interrupt is used for VBUS detection and will 3245 kick off the VBUS handler function */ 3246 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq, 3247 0, "udc_otg", udc); 3248 if (retval < 0) { 3249 dev_err(udc->dev, "VBUS request irq %d failed\n", 3250 udc->udp_irq[IRQ_USB_ATX]); 3251 goto irq_xcvr_fail; 3252 } 3253 3254 /* Initialize wait queue */ 3255 init_waitqueue_head(&udc->ep_disable_wait_queue); 3256 atomic_set(&udc->enabled_ep_cnt, 0); 3257 3258 /* Keep all IRQs disabled until GadgetFS starts up */ 3259 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) 3260 disable_irq(udc->udp_irq[i]); 3261 3262 retval = usb_add_gadget_udc(dev, &udc->gadget); 3263 if (retval < 0) 3264 goto add_gadget_fail; 3265 3266 dev_set_drvdata(dev, udc); 3267 device_init_wakeup(dev, 1); 3268 create_debug_file(udc); 3269 3270 /* Disable clocks for now */ 3271 udc_clk_set(udc, 0); 3272 3273 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); 3274 return 0; 3275 3276 add_gadget_fail: 3277 free_irq(udc->udp_irq[IRQ_USB_ATX], udc); 3278 irq_xcvr_fail: 3279 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); 3280 irq_dev_fail: 3281 free_irq(udc->udp_irq[IRQ_USB_HP], udc); 3282 irq_hp_fail: 3283 free_irq(udc->udp_irq[IRQ_USB_LP], udc); 3284 irq_lp_fail: 3285 dma_pool_destroy(udc->dd_cache); 3286 dma_alloc_fail: 3287 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3288 udc->udca_v_base, udc->udca_p_base); 3289 i2c_fail: 3290 clk_disable(udc->usb_otg_clk); 3291 usb_otg_clk_enable_fail: 3292 clk_disable(udc->usb_slv_clk); 3293 usb_clk_enable_fail: 3294 pll_set_fail: 3295 clk_disable(udc->usb_pll_clk); 3296 pll_enable_fail: 3297 clk_put(udc->usb_otg_clk); 3298 usb_otg_clk_get_fail: 3299 clk_put(udc->usb_slv_clk); 3300 usb_clk_get_fail: 3301 clk_put(udc->usb_pll_clk); 3302 pll_get_fail: 3303 iounmap(udc->udp_baseaddr); 3304 io_map_fail: 3305 release_mem_region(udc->io_p_start, udc->io_p_size); 3306 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); 3307 request_mem_region_fail: 3308 irq_fail: 3309 resource_fail: 3310 phy_fail: 3311 kfree(udc); 3312 return retval; 3313 } 3314 3315 static int lpc32xx_udc_remove(struct platform_device *pdev) 3316 { 3317 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3318 3319 usb_del_gadget_udc(&udc->gadget); 3320 if (udc->driver) 3321 return -EBUSY; 3322 3323 udc_clk_set(udc, 1); 3324 udc_disable(udc); 3325 pullup(udc, 0); 3326 3327 free_irq(udc->udp_irq[IRQ_USB_ATX], udc); 3328 3329 device_init_wakeup(&pdev->dev, 0); 3330 remove_debug_file(udc); 3331 3332 dma_pool_destroy(udc->dd_cache); 3333 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3334 udc->udca_v_base, udc->udca_p_base); 3335 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); 3336 free_irq(udc->udp_irq[IRQ_USB_HP], udc); 3337 free_irq(udc->udp_irq[IRQ_USB_LP], udc); 3338 3339 clk_disable(udc->usb_otg_clk); 3340 clk_put(udc->usb_otg_clk); 3341 clk_disable(udc->usb_slv_clk); 3342 clk_put(udc->usb_slv_clk); 3343 clk_disable(udc->usb_pll_clk); 3344 clk_put(udc->usb_pll_clk); 3345 iounmap(udc->udp_baseaddr); 3346 release_mem_region(udc->io_p_start, udc->io_p_size); 3347 kfree(udc); 3348 3349 return 0; 3350 } 3351 3352 #ifdef CONFIG_PM 3353 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) 3354 { 3355 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3356 3357 if (udc->clocked) { 3358 /* Power down ISP */ 3359 udc->poweron = 0; 3360 isp1301_set_powerstate(udc, 0); 3361 3362 /* Disable clocking */ 3363 udc_clk_set(udc, 0); 3364 3365 /* Keep clock flag on, so we know to re-enable clocks 3366 on resume */ 3367 udc->clocked = 1; 3368 3369 /* Kill global USB clock */ 3370 clk_disable(udc->usb_slv_clk); 3371 } 3372 3373 return 0; 3374 } 3375 3376 static int lpc32xx_udc_resume(struct platform_device *pdev) 3377 { 3378 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3379 3380 if (udc->clocked) { 3381 /* Enable global USB clock */ 3382 clk_enable(udc->usb_slv_clk); 3383 3384 /* Enable clocking */ 3385 udc_clk_set(udc, 1); 3386 3387 /* ISP back to normal power mode */ 3388 udc->poweron = 1; 3389 isp1301_set_powerstate(udc, 1); 3390 } 3391 3392 return 0; 3393 } 3394 #else 3395 #define lpc32xx_udc_suspend NULL 3396 #define lpc32xx_udc_resume NULL 3397 #endif 3398 3399 #ifdef CONFIG_OF 3400 static const struct of_device_id lpc32xx_udc_of_match[] = { 3401 { .compatible = "nxp,lpc3220-udc", }, 3402 { }, 3403 }; 3404 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); 3405 #endif 3406 3407 static struct platform_driver lpc32xx_udc_driver = { 3408 .remove = lpc32xx_udc_remove, 3409 .shutdown = lpc32xx_udc_shutdown, 3410 .suspend = lpc32xx_udc_suspend, 3411 .resume = lpc32xx_udc_resume, 3412 .driver = { 3413 .name = (char *) driver_name, 3414 .of_match_table = of_match_ptr(lpc32xx_udc_of_match), 3415 }, 3416 }; 3417 3418 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe); 3419 3420 MODULE_DESCRIPTION("LPC32XX udc driver"); 3421 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 3422 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 3423 MODULE_LICENSE("GPL"); 3424 MODULE_ALIAS("platform:lpc32xx_udc"); 3425