xref: /linux/drivers/usb/dwc3/gadget.c (revision 52a9dab6d892763b2a8334a568bd4e2c1a6fde66)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
21 
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24 
25 #include "debug.h"
26 #include "core.h"
27 #include "gadget.h"
28 #include "io.h"
29 
30 #define DWC3_ALIGN_FRAME(d, n)	(((d)->frame_number + ((d)->interval * (n))) \
31 					& ~((d)->interval - 1))
32 
33 /**
34  * dwc3_gadget_set_test_mode - enables usb2 test modes
35  * @dwc: pointer to our context structure
36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37  *
38  * Caller should take care of locking. This function will return 0 on
39  * success or -EINVAL if wrong Test Selector is passed.
40  */
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42 {
43 	u32		reg;
44 
45 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47 
48 	switch (mode) {
49 	case USB_TEST_J:
50 	case USB_TEST_K:
51 	case USB_TEST_SE0_NAK:
52 	case USB_TEST_PACKET:
53 	case USB_TEST_FORCE_ENABLE:
54 		reg |= mode << 1;
55 		break;
56 	default:
57 		return -EINVAL;
58 	}
59 
60 	dwc3_gadget_dctl_write_safe(dwc, reg);
61 
62 	return 0;
63 }
64 
65 /**
66  * dwc3_gadget_get_link_state - gets current state of usb link
67  * @dwc: pointer to our context structure
68  *
69  * Caller should take care of locking. This function will
70  * return the link state on success (>= 0) or -ETIMEDOUT.
71  */
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73 {
74 	u32		reg;
75 
76 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77 
78 	return DWC3_DSTS_USBLNKST(reg);
79 }
80 
81 /**
82  * dwc3_gadget_set_link_state - sets usb link to a particular state
83  * @dwc: pointer to our context structure
84  * @state: the state to put link into
85  *
86  * Caller should take care of locking. This function will
87  * return 0 on success or -ETIMEDOUT.
88  */
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90 {
91 	int		retries = 10000;
92 	u32		reg;
93 
94 	/*
95 	 * Wait until device controller is ready. Only applies to 1.94a and
96 	 * later RTL.
97 	 */
98 	if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 		while (--retries) {
100 			reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 			if (reg & DWC3_DSTS_DCNRD)
102 				udelay(5);
103 			else
104 				break;
105 		}
106 
107 		if (retries <= 0)
108 			return -ETIMEDOUT;
109 	}
110 
111 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 	reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113 
114 	/* set no action before sending new link state change */
115 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116 
117 	/* set requested state */
118 	reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120 
121 	/*
122 	 * The following code is racy when called from dwc3_gadget_wakeup,
123 	 * and is not needed, at least on newer versions
124 	 */
125 	if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 		return 0;
127 
128 	/* wait for a change in DSTS */
129 	retries = 10000;
130 	while (--retries) {
131 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132 
133 		if (DWC3_DSTS_USBLNKST(reg) == state)
134 			return 0;
135 
136 		udelay(5);
137 	}
138 
139 	return -ETIMEDOUT;
140 }
141 
142 /**
143  * dwc3_ep_inc_trb - increment a trb index.
144  * @index: Pointer to the TRB index to increment.
145  *
146  * The index should never point to the link TRB. After incrementing,
147  * if it is point to the link TRB, wrap around to the beginning. The
148  * link TRB is always at the last TRB entry.
149  */
150 static void dwc3_ep_inc_trb(u8 *index)
151 {
152 	(*index)++;
153 	if (*index == (DWC3_TRB_NUM - 1))
154 		*index = 0;
155 }
156 
157 /**
158  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159  * @dep: The endpoint whose enqueue pointer we're incrementing
160  */
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
162 {
163 	dwc3_ep_inc_trb(&dep->trb_enqueue);
164 }
165 
166 /**
167  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168  * @dep: The endpoint whose enqueue pointer we're incrementing
169  */
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
171 {
172 	dwc3_ep_inc_trb(&dep->trb_dequeue);
173 }
174 
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 		struct dwc3_request *req, int status)
177 {
178 	struct dwc3			*dwc = dep->dwc;
179 
180 	list_del(&req->list);
181 	req->remaining = 0;
182 	req->needs_extra_trb = false;
183 
184 	if (req->request.status == -EINPROGRESS)
185 		req->request.status = status;
186 
187 	if (req->trb)
188 		usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 				&req->request, req->direction);
190 
191 	req->trb = NULL;
192 	trace_dwc3_gadget_giveback(req);
193 
194 	if (dep->number > 1)
195 		pm_runtime_put(dwc->dev);
196 }
197 
198 /**
199  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200  * @dep: The endpoint to whom the request belongs to
201  * @req: The request we're giving back
202  * @status: completion code for the request
203  *
204  * Must be called with controller's lock held and interrupts disabled. This
205  * function will unmap @req and call its ->complete() callback to notify upper
206  * layers that it has completed.
207  */
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209 		int status)
210 {
211 	struct dwc3			*dwc = dep->dwc;
212 
213 	dwc3_gadget_del_and_unmap_request(dep, req, status);
214 	req->status = DWC3_REQUEST_STATUS_COMPLETED;
215 
216 	spin_unlock(&dwc->lock);
217 	usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 	spin_lock(&dwc->lock);
219 }
220 
221 /**
222  * dwc3_send_gadget_generic_command - issue a generic command for the controller
223  * @dwc: pointer to the controller context
224  * @cmd: the command to be issued
225  * @param: command parameter
226  *
227  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228  * and wait for its completion.
229  */
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
231 		u32 param)
232 {
233 	u32		timeout = 500;
234 	int		status = 0;
235 	int		ret = 0;
236 	u32		reg;
237 
238 	dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 	dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
240 
241 	do {
242 		reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 		if (!(reg & DWC3_DGCMD_CMDACT)) {
244 			status = DWC3_DGCMD_STATUS(reg);
245 			if (status)
246 				ret = -EINVAL;
247 			break;
248 		}
249 	} while (--timeout);
250 
251 	if (!timeout) {
252 		ret = -ETIMEDOUT;
253 		status = -ETIMEDOUT;
254 	}
255 
256 	trace_dwc3_gadget_generic_cmd(cmd, param, status);
257 
258 	return ret;
259 }
260 
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
262 
263 /**
264  * dwc3_send_gadget_ep_cmd - issue an endpoint command
265  * @dep: the endpoint to which the command is going to be issued
266  * @cmd: the command to be issued
267  * @params: parameters to the command
268  *
269  * Caller should handle locking. This function will issue @cmd with given
270  * @params to @dep and wait for its completion.
271  */
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 		struct dwc3_gadget_ep_cmd_params *params)
274 {
275 	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 	struct dwc3		*dwc = dep->dwc;
277 	u32			timeout = 5000;
278 	u32			saved_config = 0;
279 	u32			reg;
280 
281 	int			cmd_status = 0;
282 	int			ret = -EINVAL;
283 
284 	/*
285 	 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 	 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
287 	 * endpoint command.
288 	 *
289 	 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 	 * settings. Restore them after the command is completed.
291 	 *
292 	 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
293 	 */
294 	if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 		if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 			saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
299 		}
300 
301 		if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 			saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 			reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
304 		}
305 
306 		if (saved_config)
307 			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
308 	}
309 
310 	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
311 		int link_state;
312 
313 		/*
314 		 * Initiate remote wakeup if the link state is in U3 when
315 		 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
316 		 * link state is in U1/U2, no remote wakeup is needed. The Start
317 		 * Transfer command will initiate the link recovery.
318 		 */
319 		link_state = dwc3_gadget_get_link_state(dwc);
320 		switch (link_state) {
321 		case DWC3_LINK_STATE_U2:
322 			if (dwc->gadget->speed >= USB_SPEED_SUPER)
323 				break;
324 
325 			fallthrough;
326 		case DWC3_LINK_STATE_U3:
327 			ret = __dwc3_gadget_wakeup(dwc);
328 			dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
329 					ret);
330 			break;
331 		}
332 	}
333 
334 	/*
335 	 * For some commands such as Update Transfer command, DEPCMDPARn
336 	 * registers are reserved. Since the driver often sends Update Transfer
337 	 * command, don't write to DEPCMDPARn to avoid register write delays and
338 	 * improve performance.
339 	 */
340 	if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
341 		dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
342 		dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
343 		dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
344 	}
345 
346 	/*
347 	 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
348 	 * not relying on XferNotReady, we can make use of a special "No
349 	 * Response Update Transfer" command where we should clear both CmdAct
350 	 * and CmdIOC bits.
351 	 *
352 	 * With this, we don't need to wait for command completion and can
353 	 * straight away issue further commands to the endpoint.
354 	 *
355 	 * NOTICE: We're making an assumption that control endpoints will never
356 	 * make use of Update Transfer command. This is a safe assumption
357 	 * because we can never have more than one request at a time with
358 	 * Control Endpoints. If anybody changes that assumption, this chunk
359 	 * needs to be updated accordingly.
360 	 */
361 	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
362 			!usb_endpoint_xfer_isoc(desc))
363 		cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
364 	else
365 		cmd |= DWC3_DEPCMD_CMDACT;
366 
367 	dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
368 
369 	if (!(cmd & DWC3_DEPCMD_CMDACT)) {
370 		ret = 0;
371 		goto skip_status;
372 	}
373 
374 	do {
375 		reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
376 		if (!(reg & DWC3_DEPCMD_CMDACT)) {
377 			cmd_status = DWC3_DEPCMD_STATUS(reg);
378 
379 			switch (cmd_status) {
380 			case 0:
381 				ret = 0;
382 				break;
383 			case DEPEVT_TRANSFER_NO_RESOURCE:
384 				dev_WARN(dwc->dev, "No resource for %s\n",
385 					 dep->name);
386 				ret = -EINVAL;
387 				break;
388 			case DEPEVT_TRANSFER_BUS_EXPIRY:
389 				/*
390 				 * SW issues START TRANSFER command to
391 				 * isochronous ep with future frame interval. If
392 				 * future interval time has already passed when
393 				 * core receives the command, it will respond
394 				 * with an error status of 'Bus Expiry'.
395 				 *
396 				 * Instead of always returning -EINVAL, let's
397 				 * give a hint to the gadget driver that this is
398 				 * the case by returning -EAGAIN.
399 				 */
400 				ret = -EAGAIN;
401 				break;
402 			default:
403 				dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
404 			}
405 
406 			break;
407 		}
408 	} while (--timeout);
409 
410 	if (timeout == 0) {
411 		ret = -ETIMEDOUT;
412 		cmd_status = -ETIMEDOUT;
413 	}
414 
415 skip_status:
416 	trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
417 
418 	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
419 		if (ret == 0)
420 			dep->flags |= DWC3_EP_TRANSFER_STARTED;
421 
422 		if (ret != -ETIMEDOUT)
423 			dwc3_gadget_ep_get_transfer_index(dep);
424 	}
425 
426 	if (saved_config) {
427 		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
428 		reg |= saved_config;
429 		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
430 	}
431 
432 	return ret;
433 }
434 
435 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
436 {
437 	struct dwc3 *dwc = dep->dwc;
438 	struct dwc3_gadget_ep_cmd_params params;
439 	u32 cmd = DWC3_DEPCMD_CLEARSTALL;
440 
441 	/*
442 	 * As of core revision 2.60a the recommended programming model
443 	 * is to set the ClearPendIN bit when issuing a Clear Stall EP
444 	 * command for IN endpoints. This is to prevent an issue where
445 	 * some (non-compliant) hosts may not send ACK TPs for pending
446 	 * IN transfers due to a mishandled error condition. Synopsys
447 	 * STAR 9000614252.
448 	 */
449 	if (dep->direction &&
450 	    !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
451 	    (dwc->gadget->speed >= USB_SPEED_SUPER))
452 		cmd |= DWC3_DEPCMD_CLEARPENDIN;
453 
454 	memset(&params, 0, sizeof(params));
455 
456 	return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
457 }
458 
459 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
460 		struct dwc3_trb *trb)
461 {
462 	u32		offset = (char *) trb - (char *) dep->trb_pool;
463 
464 	return dep->trb_pool_dma + offset;
465 }
466 
467 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
468 {
469 	struct dwc3		*dwc = dep->dwc;
470 
471 	if (dep->trb_pool)
472 		return 0;
473 
474 	dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
475 			sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
476 			&dep->trb_pool_dma, GFP_KERNEL);
477 	if (!dep->trb_pool) {
478 		dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
479 				dep->name);
480 		return -ENOMEM;
481 	}
482 
483 	return 0;
484 }
485 
486 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
487 {
488 	struct dwc3		*dwc = dep->dwc;
489 
490 	dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
491 			dep->trb_pool, dep->trb_pool_dma);
492 
493 	dep->trb_pool = NULL;
494 	dep->trb_pool_dma = 0;
495 }
496 
497 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
498 {
499 	struct dwc3_gadget_ep_cmd_params params;
500 
501 	memset(&params, 0x00, sizeof(params));
502 
503 	params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
504 
505 	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
506 			&params);
507 }
508 
509 /**
510  * dwc3_gadget_start_config - configure ep resources
511  * @dep: endpoint that is being enabled
512  *
513  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
514  * completion, it will set Transfer Resource for all available endpoints.
515  *
516  * The assignment of transfer resources cannot perfectly follow the data book
517  * due to the fact that the controller driver does not have all knowledge of the
518  * configuration in advance. It is given this information piecemeal by the
519  * composite gadget framework after every SET_CONFIGURATION and
520  * SET_INTERFACE. Trying to follow the databook programming model in this
521  * scenario can cause errors. For two reasons:
522  *
523  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
524  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
525  * incorrect in the scenario of multiple interfaces.
526  *
527  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
528  * endpoint on alt setting (8.1.6).
529  *
530  * The following simplified method is used instead:
531  *
532  * All hardware endpoints can be assigned a transfer resource and this setting
533  * will stay persistent until either a core reset or hibernation. So whenever we
534  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
535  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
536  * guaranteed that there are as many transfer resources as endpoints.
537  *
538  * This function is called for each endpoint when it is being enabled but is
539  * triggered only when called for EP0-out, which always happens first, and which
540  * should only happen in one of the above conditions.
541  */
542 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
543 {
544 	struct dwc3_gadget_ep_cmd_params params;
545 	struct dwc3		*dwc;
546 	u32			cmd;
547 	int			i;
548 	int			ret;
549 
550 	if (dep->number)
551 		return 0;
552 
553 	memset(&params, 0x00, sizeof(params));
554 	cmd = DWC3_DEPCMD_DEPSTARTCFG;
555 	dwc = dep->dwc;
556 
557 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
558 	if (ret)
559 		return ret;
560 
561 	for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
562 		struct dwc3_ep *dep = dwc->eps[i];
563 
564 		if (!dep)
565 			continue;
566 
567 		ret = dwc3_gadget_set_xfer_resource(dep);
568 		if (ret)
569 			return ret;
570 	}
571 
572 	return 0;
573 }
574 
575 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
576 {
577 	const struct usb_ss_ep_comp_descriptor *comp_desc;
578 	const struct usb_endpoint_descriptor *desc;
579 	struct dwc3_gadget_ep_cmd_params params;
580 	struct dwc3 *dwc = dep->dwc;
581 
582 	comp_desc = dep->endpoint.comp_desc;
583 	desc = dep->endpoint.desc;
584 
585 	memset(&params, 0x00, sizeof(params));
586 
587 	params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
588 		| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
589 
590 	/* Burst size is only needed in SuperSpeed mode */
591 	if (dwc->gadget->speed >= USB_SPEED_SUPER) {
592 		u32 burst = dep->endpoint.maxburst;
593 
594 		params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
595 	}
596 
597 	params.param0 |= action;
598 	if (action == DWC3_DEPCFG_ACTION_RESTORE)
599 		params.param2 |= dep->saved_state;
600 
601 	if (usb_endpoint_xfer_control(desc))
602 		params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
603 
604 	if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
605 		params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
606 
607 	if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
608 		params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
609 			| DWC3_DEPCFG_XFER_COMPLETE_EN
610 			| DWC3_DEPCFG_STREAM_EVENT_EN;
611 		dep->stream_capable = true;
612 	}
613 
614 	if (!usb_endpoint_xfer_control(desc))
615 		params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
616 
617 	/*
618 	 * We are doing 1:1 mapping for endpoints, meaning
619 	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
620 	 * so on. We consider the direction bit as part of the physical
621 	 * endpoint number. So USB endpoint 0x81 is 0x03.
622 	 */
623 	params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
624 
625 	/*
626 	 * We must use the lower 16 TX FIFOs even though
627 	 * HW might have more
628 	 */
629 	if (dep->direction)
630 		params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
631 
632 	if (desc->bInterval) {
633 		u8 bInterval_m1;
634 
635 		/*
636 		 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
637 		 *
638 		 * NOTE: The programming guide incorrectly stated bInterval_m1
639 		 * must be set to 0 when operating in fullspeed. Internally the
640 		 * controller does not have this limitation. See DWC_usb3x
641 		 * programming guide section 3.2.2.1.
642 		 */
643 		bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
644 
645 		if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
646 		    dwc->gadget->speed == USB_SPEED_FULL)
647 			dep->interval = desc->bInterval;
648 		else
649 			dep->interval = 1 << (desc->bInterval - 1);
650 
651 		params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
652 	}
653 
654 	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
655 }
656 
657 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
658 		bool interrupt);
659 
660 /**
661  * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
662  * @dwc: pointer to the DWC3 context
663  * @nfifos: number of fifos to calculate for
664  *
665  * Calculates the size value based on the equation below:
666  *
667  * DWC3 revision 280A and prior:
668  * fifo_size = mult * (max_packet / mdwidth) + 1;
669  *
670  * DWC3 revision 290A and onwards:
671  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
672  *
673  * The max packet size is set to 1024, as the txfifo requirements mainly apply
674  * to super speed USB use cases.  However, it is safe to overestimate the fifo
675  * allocations for other scenarios, i.e. high speed USB.
676  */
677 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
678 {
679 	int max_packet = 1024;
680 	int fifo_size;
681 	int mdwidth;
682 
683 	mdwidth = dwc3_mdwidth(dwc);
684 
685 	/* MDWIDTH is represented in bits, we need it in bytes */
686 	mdwidth >>= 3;
687 
688 	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
689 		fifo_size = mult * (max_packet / mdwidth) + 1;
690 	else
691 		fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
692 	return fifo_size;
693 }
694 
695 /**
696  * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
697  * @dwc: pointer to the DWC3 context
698  *
699  * Iterates through all the endpoint registers and clears the previous txfifo
700  * allocations.
701  */
702 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
703 {
704 	struct dwc3_ep *dep;
705 	int fifo_depth;
706 	int size;
707 	int num;
708 
709 	if (!dwc->do_fifo_resize)
710 		return;
711 
712 	/* Read ep0IN related TXFIFO size */
713 	dep = dwc->eps[1];
714 	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
715 	if (DWC3_IP_IS(DWC3))
716 		fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
717 	else
718 		fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
719 
720 	dwc->last_fifo_depth = fifo_depth;
721 	/* Clear existing TXFIFO for all IN eps except ep0 */
722 	for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
723 	     num += 2) {
724 		dep = dwc->eps[num];
725 		/* Don't change TXFRAMNUM on usb31 version */
726 		size = DWC3_IP_IS(DWC3) ? 0 :
727 			dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
728 				   DWC31_GTXFIFOSIZ_TXFRAMNUM;
729 
730 		dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
731 		dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
732 	}
733 	dwc->num_ep_resized = 0;
734 }
735 
736 /*
737  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
738  * @dwc: pointer to our context structure
739  *
740  * This function will a best effort FIFO allocation in order
741  * to improve FIFO usage and throughput, while still allowing
742  * us to enable as many endpoints as possible.
743  *
744  * Keep in mind that this operation will be highly dependent
745  * on the configured size for RAM1 - which contains TxFifo -,
746  * the amount of endpoints enabled on coreConsultant tool, and
747  * the width of the Master Bus.
748  *
749  * In general, FIFO depths are represented with the following equation:
750  *
751  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
752  *
753  * In conjunction with dwc3_gadget_check_config(), this resizing logic will
754  * ensure that all endpoints will have enough internal memory for one max
755  * packet per endpoint.
756  */
757 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
758 {
759 	struct dwc3 *dwc = dep->dwc;
760 	int fifo_0_start;
761 	int ram1_depth;
762 	int fifo_size;
763 	int min_depth;
764 	int num_in_ep;
765 	int remaining;
766 	int num_fifos = 1;
767 	int fifo;
768 	int tmp;
769 
770 	if (!dwc->do_fifo_resize)
771 		return 0;
772 
773 	/* resize IN endpoints except ep0 */
774 	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
775 		return 0;
776 
777 	/* bail if already resized */
778 	if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
779 		return 0;
780 
781 	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
782 
783 	if ((dep->endpoint.maxburst > 1 &&
784 	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
785 	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
786 		num_fifos = 3;
787 
788 	if (dep->endpoint.maxburst > 6 &&
789 	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
790 		num_fifos = dwc->tx_fifo_resize_max_num;
791 
792 	/* FIFO size for a single buffer */
793 	fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
794 
795 	/* Calculate the number of remaining EPs w/o any FIFO */
796 	num_in_ep = dwc->max_cfg_eps;
797 	num_in_ep -= dwc->num_ep_resized;
798 
799 	/* Reserve at least one FIFO for the number of IN EPs */
800 	min_depth = num_in_ep * (fifo + 1);
801 	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
802 	remaining = max_t(int, 0, remaining);
803 	/*
804 	 * We've already reserved 1 FIFO per EP, so check what we can fit in
805 	 * addition to it.  If there is not enough remaining space, allocate
806 	 * all the remaining space to the EP.
807 	 */
808 	fifo_size = (num_fifos - 1) * fifo;
809 	if (remaining < fifo_size)
810 		fifo_size = remaining;
811 
812 	fifo_size += fifo;
813 	/* Last increment according to the TX FIFO size equation */
814 	fifo_size++;
815 
816 	/* Check if TXFIFOs start at non-zero addr */
817 	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
818 	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
819 
820 	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
821 	if (DWC3_IP_IS(DWC3))
822 		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
823 	else
824 		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
825 
826 	/* Check fifo size allocation doesn't exceed available RAM size. */
827 	if (dwc->last_fifo_depth >= ram1_depth) {
828 		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
829 			dwc->last_fifo_depth, ram1_depth,
830 			dep->endpoint.name, fifo_size);
831 		if (DWC3_IP_IS(DWC3))
832 			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
833 		else
834 			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
835 
836 		dwc->last_fifo_depth -= fifo_size;
837 		return -ENOMEM;
838 	}
839 
840 	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
841 	dep->flags |= DWC3_EP_TXFIFO_RESIZED;
842 	dwc->num_ep_resized++;
843 
844 	return 0;
845 }
846 
847 /**
848  * __dwc3_gadget_ep_enable - initializes a hw endpoint
849  * @dep: endpoint to be initialized
850  * @action: one of INIT, MODIFY or RESTORE
851  *
852  * Caller should take care of locking. Execute all necessary commands to
853  * initialize a HW endpoint so it can be used by a gadget driver.
854  */
855 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
856 {
857 	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
858 	struct dwc3		*dwc = dep->dwc;
859 
860 	u32			reg;
861 	int			ret;
862 
863 	if (!(dep->flags & DWC3_EP_ENABLED)) {
864 		ret = dwc3_gadget_resize_tx_fifos(dep);
865 		if (ret)
866 			return ret;
867 
868 		ret = dwc3_gadget_start_config(dep);
869 		if (ret)
870 			return ret;
871 	}
872 
873 	ret = dwc3_gadget_set_ep_config(dep, action);
874 	if (ret)
875 		return ret;
876 
877 	if (!(dep->flags & DWC3_EP_ENABLED)) {
878 		struct dwc3_trb	*trb_st_hw;
879 		struct dwc3_trb	*trb_link;
880 
881 		dep->type = usb_endpoint_type(desc);
882 		dep->flags |= DWC3_EP_ENABLED;
883 
884 		reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
885 		reg |= DWC3_DALEPENA_EP(dep->number);
886 		dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
887 
888 		if (usb_endpoint_xfer_control(desc))
889 			goto out;
890 
891 		/* Initialize the TRB ring */
892 		dep->trb_dequeue = 0;
893 		dep->trb_enqueue = 0;
894 		memset(dep->trb_pool, 0,
895 		       sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
896 
897 		/* Link TRB. The HWO bit is never reset */
898 		trb_st_hw = &dep->trb_pool[0];
899 
900 		trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
901 		trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
902 		trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
903 		trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
904 		trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
905 	}
906 
907 	/*
908 	 * Issue StartTransfer here with no-op TRB so we can always rely on No
909 	 * Response Update Transfer command.
910 	 */
911 	if (usb_endpoint_xfer_bulk(desc) ||
912 			usb_endpoint_xfer_int(desc)) {
913 		struct dwc3_gadget_ep_cmd_params params;
914 		struct dwc3_trb	*trb;
915 		dma_addr_t trb_dma;
916 		u32 cmd;
917 
918 		memset(&params, 0, sizeof(params));
919 		trb = &dep->trb_pool[0];
920 		trb_dma = dwc3_trb_dma_offset(dep, trb);
921 
922 		params.param0 = upper_32_bits(trb_dma);
923 		params.param1 = lower_32_bits(trb_dma);
924 
925 		cmd = DWC3_DEPCMD_STARTTRANSFER;
926 
927 		ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
928 		if (ret < 0)
929 			return ret;
930 
931 		if (dep->stream_capable) {
932 			/*
933 			 * For streams, at start, there maybe a race where the
934 			 * host primes the endpoint before the function driver
935 			 * queues a request to initiate a stream. In that case,
936 			 * the controller will not see the prime to generate the
937 			 * ERDY and start stream. To workaround this, issue a
938 			 * no-op TRB as normal, but end it immediately. As a
939 			 * result, when the function driver queues the request,
940 			 * the next START_TRANSFER command will cause the
941 			 * controller to generate an ERDY to initiate the
942 			 * stream.
943 			 */
944 			dwc3_stop_active_transfer(dep, true, true);
945 
946 			/*
947 			 * All stream eps will reinitiate stream on NoStream
948 			 * rejection until we can determine that the host can
949 			 * prime after the first transfer.
950 			 *
951 			 * However, if the controller is capable of
952 			 * TXF_FLUSH_BYPASS, then IN direction endpoints will
953 			 * automatically restart the stream without the driver
954 			 * initiation.
955 			 */
956 			if (!dep->direction ||
957 			    !(dwc->hwparams.hwparams9 &
958 			      DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
959 				dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
960 		}
961 	}
962 
963 out:
964 	trace_dwc3_gadget_ep_enable(dep);
965 
966 	return 0;
967 }
968 
969 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
970 {
971 	struct dwc3_request		*req;
972 
973 	dwc3_stop_active_transfer(dep, true, false);
974 
975 	/* - giveback all requests to gadget driver */
976 	while (!list_empty(&dep->started_list)) {
977 		req = next_request(&dep->started_list);
978 
979 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
980 	}
981 
982 	while (!list_empty(&dep->pending_list)) {
983 		req = next_request(&dep->pending_list);
984 
985 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
986 	}
987 
988 	while (!list_empty(&dep->cancelled_list)) {
989 		req = next_request(&dep->cancelled_list);
990 
991 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
992 	}
993 }
994 
995 /**
996  * __dwc3_gadget_ep_disable - disables a hw endpoint
997  * @dep: the endpoint to disable
998  *
999  * This function undoes what __dwc3_gadget_ep_enable did and also removes
1000  * requests which are currently being processed by the hardware and those which
1001  * are not yet scheduled.
1002  *
1003  * Caller should take care of locking.
1004  */
1005 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1006 {
1007 	struct dwc3		*dwc = dep->dwc;
1008 	u32			reg;
1009 
1010 	trace_dwc3_gadget_ep_disable(dep);
1011 
1012 	/* make sure HW endpoint isn't stalled */
1013 	if (dep->flags & DWC3_EP_STALL)
1014 		__dwc3_gadget_ep_set_halt(dep, 0, false);
1015 
1016 	reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1017 	reg &= ~DWC3_DALEPENA_EP(dep->number);
1018 	dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1019 
1020 	/* Clear out the ep descriptors for non-ep0 */
1021 	if (dep->number > 1) {
1022 		dep->endpoint.comp_desc = NULL;
1023 		dep->endpoint.desc = NULL;
1024 	}
1025 
1026 	dwc3_remove_requests(dwc, dep);
1027 
1028 	dep->stream_capable = false;
1029 	dep->type = 0;
1030 	dep->flags &= DWC3_EP_TXFIFO_RESIZED;
1031 
1032 	return 0;
1033 }
1034 
1035 /* -------------------------------------------------------------------------- */
1036 
1037 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1038 		const struct usb_endpoint_descriptor *desc)
1039 {
1040 	return -EINVAL;
1041 }
1042 
1043 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1044 {
1045 	return -EINVAL;
1046 }
1047 
1048 /* -------------------------------------------------------------------------- */
1049 
1050 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1051 		const struct usb_endpoint_descriptor *desc)
1052 {
1053 	struct dwc3_ep			*dep;
1054 	struct dwc3			*dwc;
1055 	unsigned long			flags;
1056 	int				ret;
1057 
1058 	if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1059 		pr_debug("dwc3: invalid parameters\n");
1060 		return -EINVAL;
1061 	}
1062 
1063 	if (!desc->wMaxPacketSize) {
1064 		pr_debug("dwc3: missing wMaxPacketSize\n");
1065 		return -EINVAL;
1066 	}
1067 
1068 	dep = to_dwc3_ep(ep);
1069 	dwc = dep->dwc;
1070 
1071 	if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1072 					"%s is already enabled\n",
1073 					dep->name))
1074 		return 0;
1075 
1076 	spin_lock_irqsave(&dwc->lock, flags);
1077 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1078 	spin_unlock_irqrestore(&dwc->lock, flags);
1079 
1080 	return ret;
1081 }
1082 
1083 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1084 {
1085 	struct dwc3_ep			*dep;
1086 	struct dwc3			*dwc;
1087 	unsigned long			flags;
1088 	int				ret;
1089 
1090 	if (!ep) {
1091 		pr_debug("dwc3: invalid parameters\n");
1092 		return -EINVAL;
1093 	}
1094 
1095 	dep = to_dwc3_ep(ep);
1096 	dwc = dep->dwc;
1097 
1098 	if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1099 					"%s is already disabled\n",
1100 					dep->name))
1101 		return 0;
1102 
1103 	spin_lock_irqsave(&dwc->lock, flags);
1104 	ret = __dwc3_gadget_ep_disable(dep);
1105 	spin_unlock_irqrestore(&dwc->lock, flags);
1106 
1107 	return ret;
1108 }
1109 
1110 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1111 		gfp_t gfp_flags)
1112 {
1113 	struct dwc3_request		*req;
1114 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1115 
1116 	req = kzalloc(sizeof(*req), gfp_flags);
1117 	if (!req)
1118 		return NULL;
1119 
1120 	req->direction	= dep->direction;
1121 	req->epnum	= dep->number;
1122 	req->dep	= dep;
1123 	req->status	= DWC3_REQUEST_STATUS_UNKNOWN;
1124 
1125 	trace_dwc3_alloc_request(req);
1126 
1127 	return &req->request;
1128 }
1129 
1130 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1131 		struct usb_request *request)
1132 {
1133 	struct dwc3_request		*req = to_dwc3_request(request);
1134 
1135 	trace_dwc3_free_request(req);
1136 	kfree(req);
1137 }
1138 
1139 /**
1140  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1141  * @dep: The endpoint with the TRB ring
1142  * @index: The index of the current TRB in the ring
1143  *
1144  * Returns the TRB prior to the one pointed to by the index. If the
1145  * index is 0, we will wrap backwards, skip the link TRB, and return
1146  * the one just before that.
1147  */
1148 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1149 {
1150 	u8 tmp = index;
1151 
1152 	if (!tmp)
1153 		tmp = DWC3_TRB_NUM - 1;
1154 
1155 	return &dep->trb_pool[tmp - 1];
1156 }
1157 
1158 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1159 {
1160 	u8			trbs_left;
1161 
1162 	/*
1163 	 * If the enqueue & dequeue are equal then the TRB ring is either full
1164 	 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1165 	 * pending to be processed by the driver.
1166 	 */
1167 	if (dep->trb_enqueue == dep->trb_dequeue) {
1168 		/*
1169 		 * If there is any request remained in the started_list at
1170 		 * this point, that means there is no TRB available.
1171 		 */
1172 		if (!list_empty(&dep->started_list))
1173 			return 0;
1174 
1175 		return DWC3_TRB_NUM - 1;
1176 	}
1177 
1178 	trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1179 	trbs_left &= (DWC3_TRB_NUM - 1);
1180 
1181 	if (dep->trb_dequeue < dep->trb_enqueue)
1182 		trbs_left--;
1183 
1184 	return trbs_left;
1185 }
1186 
1187 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
1188 		dma_addr_t dma, unsigned int length, unsigned int chain,
1189 		unsigned int node, unsigned int stream_id,
1190 		unsigned int short_not_ok, unsigned int no_interrupt,
1191 		unsigned int is_last, bool must_interrupt)
1192 {
1193 	struct dwc3		*dwc = dep->dwc;
1194 	struct usb_gadget	*gadget = dwc->gadget;
1195 	enum usb_device_speed	speed = gadget->speed;
1196 
1197 	trb->size = DWC3_TRB_SIZE_LENGTH(length);
1198 	trb->bpl = lower_32_bits(dma);
1199 	trb->bph = upper_32_bits(dma);
1200 
1201 	switch (usb_endpoint_type(dep->endpoint.desc)) {
1202 	case USB_ENDPOINT_XFER_CONTROL:
1203 		trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1204 		break;
1205 
1206 	case USB_ENDPOINT_XFER_ISOC:
1207 		if (!node) {
1208 			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1209 
1210 			/*
1211 			 * USB Specification 2.0 Section 5.9.2 states that: "If
1212 			 * there is only a single transaction in the microframe,
1213 			 * only a DATA0 data packet PID is used.  If there are
1214 			 * two transactions per microframe, DATA1 is used for
1215 			 * the first transaction data packet and DATA0 is used
1216 			 * for the second transaction data packet.  If there are
1217 			 * three transactions per microframe, DATA2 is used for
1218 			 * the first transaction data packet, DATA1 is used for
1219 			 * the second, and DATA0 is used for the third."
1220 			 *
1221 			 * IOW, we should satisfy the following cases:
1222 			 *
1223 			 * 1) length <= maxpacket
1224 			 *	- DATA0
1225 			 *
1226 			 * 2) maxpacket < length <= (2 * maxpacket)
1227 			 *	- DATA1, DATA0
1228 			 *
1229 			 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1230 			 *	- DATA2, DATA1, DATA0
1231 			 */
1232 			if (speed == USB_SPEED_HIGH) {
1233 				struct usb_ep *ep = &dep->endpoint;
1234 				unsigned int mult = 2;
1235 				unsigned int maxp = usb_endpoint_maxp(ep->desc);
1236 
1237 				if (length <= (2 * maxp))
1238 					mult--;
1239 
1240 				if (length <= maxp)
1241 					mult--;
1242 
1243 				trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1244 			}
1245 		} else {
1246 			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1247 		}
1248 
1249 		/* always enable Interrupt on Missed ISOC */
1250 		trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1251 		break;
1252 
1253 	case USB_ENDPOINT_XFER_BULK:
1254 	case USB_ENDPOINT_XFER_INT:
1255 		trb->ctrl = DWC3_TRBCTL_NORMAL;
1256 		break;
1257 	default:
1258 		/*
1259 		 * This is only possible with faulty memory because we
1260 		 * checked it already :)
1261 		 */
1262 		dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1263 				usb_endpoint_type(dep->endpoint.desc));
1264 	}
1265 
1266 	/*
1267 	 * Enable Continue on Short Packet
1268 	 * when endpoint is not a stream capable
1269 	 */
1270 	if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1271 		if (!dep->stream_capable)
1272 			trb->ctrl |= DWC3_TRB_CTRL_CSP;
1273 
1274 		if (short_not_ok)
1275 			trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1276 	}
1277 
1278 	/* All TRBs setup for MST must set CSP=1 when LST=0 */
1279 	if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1280 		trb->ctrl |= DWC3_TRB_CTRL_CSP;
1281 
1282 	if ((!no_interrupt && !chain) || must_interrupt)
1283 		trb->ctrl |= DWC3_TRB_CTRL_IOC;
1284 
1285 	if (chain)
1286 		trb->ctrl |= DWC3_TRB_CTRL_CHN;
1287 	else if (dep->stream_capable && is_last &&
1288 		 !DWC3_MST_CAPABLE(&dwc->hwparams))
1289 		trb->ctrl |= DWC3_TRB_CTRL_LST;
1290 
1291 	if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1292 		trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1293 
1294 	/*
1295 	 * As per data book 4.2.3.2TRB Control Bit Rules section
1296 	 *
1297 	 * The controller autonomously checks the HWO field of a TRB to determine if the
1298 	 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1299 	 * is valid before setting the HWO field to '1'. In most systems, this means that
1300 	 * software must update the fourth DWORD of a TRB last.
1301 	 *
1302 	 * However there is a possibility of CPU re-ordering here which can cause
1303 	 * controller to observe the HWO bit set prematurely.
1304 	 * Add a write memory barrier to prevent CPU re-ordering.
1305 	 */
1306 	wmb();
1307 	trb->ctrl |= DWC3_TRB_CTRL_HWO;
1308 
1309 	dwc3_ep_inc_enq(dep);
1310 
1311 	trace_dwc3_prepare_trb(dep, trb);
1312 }
1313 
1314 /**
1315  * dwc3_prepare_one_trb - setup one TRB from one request
1316  * @dep: endpoint for which this request is prepared
1317  * @req: dwc3_request pointer
1318  * @trb_length: buffer size of the TRB
1319  * @chain: should this TRB be chained to the next?
1320  * @node: only for isochronous endpoints. First TRB needs different type.
1321  * @use_bounce_buffer: set to use bounce buffer
1322  * @must_interrupt: set to interrupt on TRB completion
1323  */
1324 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1325 		struct dwc3_request *req, unsigned int trb_length,
1326 		unsigned int chain, unsigned int node, bool use_bounce_buffer,
1327 		bool must_interrupt)
1328 {
1329 	struct dwc3_trb		*trb;
1330 	dma_addr_t		dma;
1331 	unsigned int		stream_id = req->request.stream_id;
1332 	unsigned int		short_not_ok = req->request.short_not_ok;
1333 	unsigned int		no_interrupt = req->request.no_interrupt;
1334 	unsigned int		is_last = req->request.is_last;
1335 
1336 	if (use_bounce_buffer)
1337 		dma = dep->dwc->bounce_addr;
1338 	else if (req->request.num_sgs > 0)
1339 		dma = sg_dma_address(req->start_sg);
1340 	else
1341 		dma = req->request.dma;
1342 
1343 	trb = &dep->trb_pool[dep->trb_enqueue];
1344 
1345 	if (!req->trb) {
1346 		dwc3_gadget_move_started_request(req);
1347 		req->trb = trb;
1348 		req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1349 	}
1350 
1351 	req->num_trbs++;
1352 
1353 	__dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1354 			stream_id, short_not_ok, no_interrupt, is_last,
1355 			must_interrupt);
1356 }
1357 
1358 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1359 {
1360 	unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1361 	unsigned int rem = req->request.length % maxp;
1362 
1363 	if ((req->request.length && req->request.zero && !rem &&
1364 			!usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1365 			(!req->direction && rem))
1366 		return true;
1367 
1368 	return false;
1369 }
1370 
1371 /**
1372  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1373  * @dep: The endpoint that the request belongs to
1374  * @req: The request to prepare
1375  * @entry_length: The last SG entry size
1376  * @node: Indicates whether this is not the first entry (for isoc only)
1377  *
1378  * Return the number of TRBs prepared.
1379  */
1380 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1381 		struct dwc3_request *req, unsigned int entry_length,
1382 		unsigned int node)
1383 {
1384 	unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1385 	unsigned int rem = req->request.length % maxp;
1386 	unsigned int num_trbs = 1;
1387 
1388 	if (dwc3_needs_extra_trb(dep, req))
1389 		num_trbs++;
1390 
1391 	if (dwc3_calc_trbs_left(dep) < num_trbs)
1392 		return 0;
1393 
1394 	req->needs_extra_trb = num_trbs > 1;
1395 
1396 	/* Prepare a normal TRB */
1397 	if (req->direction || req->request.length)
1398 		dwc3_prepare_one_trb(dep, req, entry_length,
1399 				req->needs_extra_trb, node, false, false);
1400 
1401 	/* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1402 	if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1403 		dwc3_prepare_one_trb(dep, req,
1404 				req->direction ? 0 : maxp - rem,
1405 				false, 1, true, false);
1406 
1407 	return num_trbs;
1408 }
1409 
1410 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1411 		struct dwc3_request *req)
1412 {
1413 	struct scatterlist *sg = req->start_sg;
1414 	struct scatterlist *s;
1415 	int		i;
1416 	unsigned int length = req->request.length;
1417 	unsigned int remaining = req->request.num_mapped_sgs
1418 		- req->num_queued_sgs;
1419 	unsigned int num_trbs = req->num_trbs;
1420 	bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1421 
1422 	/*
1423 	 * If we resume preparing the request, then get the remaining length of
1424 	 * the request and resume where we left off.
1425 	 */
1426 	for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1427 		length -= sg_dma_len(s);
1428 
1429 	for_each_sg(sg, s, remaining, i) {
1430 		unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1431 		unsigned int trb_length;
1432 		bool must_interrupt = false;
1433 		bool last_sg = false;
1434 
1435 		trb_length = min_t(unsigned int, length, sg_dma_len(s));
1436 
1437 		length -= trb_length;
1438 
1439 		/*
1440 		 * IOMMU driver is coalescing the list of sgs which shares a
1441 		 * page boundary into one and giving it to USB driver. With
1442 		 * this the number of sgs mapped is not equal to the number of
1443 		 * sgs passed. So mark the chain bit to false if it isthe last
1444 		 * mapped sg.
1445 		 */
1446 		if ((i == remaining - 1) || !length)
1447 			last_sg = true;
1448 
1449 		if (!num_trbs_left)
1450 			break;
1451 
1452 		if (last_sg) {
1453 			if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1454 				break;
1455 		} else {
1456 			/*
1457 			 * Look ahead to check if we have enough TRBs for the
1458 			 * next SG entry. If not, set interrupt on this TRB to
1459 			 * resume preparing the next SG entry when more TRBs are
1460 			 * free.
1461 			 */
1462 			if (num_trbs_left == 1 || (needs_extra_trb &&
1463 					num_trbs_left <= 2 &&
1464 					sg_dma_len(sg_next(s)) >= length))
1465 				must_interrupt = true;
1466 
1467 			dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1468 					must_interrupt);
1469 		}
1470 
1471 		/*
1472 		 * There can be a situation where all sgs in sglist are not
1473 		 * queued because of insufficient trb number. To handle this
1474 		 * case, update start_sg to next sg to be queued, so that
1475 		 * we have free trbs we can continue queuing from where we
1476 		 * previously stopped
1477 		 */
1478 		if (!last_sg)
1479 			req->start_sg = sg_next(s);
1480 
1481 		req->num_queued_sgs++;
1482 		req->num_pending_sgs--;
1483 
1484 		/*
1485 		 * The number of pending SG entries may not correspond to the
1486 		 * number of mapped SG entries. If all the data are queued, then
1487 		 * don't include unused SG entries.
1488 		 */
1489 		if (length == 0) {
1490 			req->num_pending_sgs = 0;
1491 			break;
1492 		}
1493 
1494 		if (must_interrupt)
1495 			break;
1496 	}
1497 
1498 	return req->num_trbs - num_trbs;
1499 }
1500 
1501 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1502 		struct dwc3_request *req)
1503 {
1504 	return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1505 }
1506 
1507 /*
1508  * dwc3_prepare_trbs - setup TRBs from requests
1509  * @dep: endpoint for which requests are being prepared
1510  *
1511  * The function goes through the requests list and sets up TRBs for the
1512  * transfers. The function returns once there are no more TRBs available or
1513  * it runs out of requests.
1514  *
1515  * Returns the number of TRBs prepared or negative errno.
1516  */
1517 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1518 {
1519 	struct dwc3_request	*req, *n;
1520 	int			ret = 0;
1521 
1522 	BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1523 
1524 	/*
1525 	 * We can get in a situation where there's a request in the started list
1526 	 * but there weren't enough TRBs to fully kick it in the first time
1527 	 * around, so it has been waiting for more TRBs to be freed up.
1528 	 *
1529 	 * In that case, we should check if we have a request with pending_sgs
1530 	 * in the started list and prepare TRBs for that request first,
1531 	 * otherwise we will prepare TRBs completely out of order and that will
1532 	 * break things.
1533 	 */
1534 	list_for_each_entry(req, &dep->started_list, list) {
1535 		if (req->num_pending_sgs > 0) {
1536 			ret = dwc3_prepare_trbs_sg(dep, req);
1537 			if (!ret || req->num_pending_sgs)
1538 				return ret;
1539 		}
1540 
1541 		if (!dwc3_calc_trbs_left(dep))
1542 			return ret;
1543 
1544 		/*
1545 		 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1546 		 * burst capability may try to read and use TRBs beyond the
1547 		 * active transfer instead of stopping.
1548 		 */
1549 		if (dep->stream_capable && req->request.is_last &&
1550 		    !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1551 			return ret;
1552 	}
1553 
1554 	list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1555 		struct dwc3	*dwc = dep->dwc;
1556 
1557 		ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1558 						    dep->direction);
1559 		if (ret)
1560 			return ret;
1561 
1562 		req->sg			= req->request.sg;
1563 		req->start_sg		= req->sg;
1564 		req->num_queued_sgs	= 0;
1565 		req->num_pending_sgs	= req->request.num_mapped_sgs;
1566 
1567 		if (req->num_pending_sgs > 0) {
1568 			ret = dwc3_prepare_trbs_sg(dep, req);
1569 			if (req->num_pending_sgs)
1570 				return ret;
1571 		} else {
1572 			ret = dwc3_prepare_trbs_linear(dep, req);
1573 		}
1574 
1575 		if (!ret || !dwc3_calc_trbs_left(dep))
1576 			return ret;
1577 
1578 		/*
1579 		 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1580 		 * burst capability may try to read and use TRBs beyond the
1581 		 * active transfer instead of stopping.
1582 		 */
1583 		if (dep->stream_capable && req->request.is_last &&
1584 		    !DWC3_MST_CAPABLE(&dwc->hwparams))
1585 			return ret;
1586 	}
1587 
1588 	return ret;
1589 }
1590 
1591 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1592 
1593 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1594 {
1595 	struct dwc3_gadget_ep_cmd_params params;
1596 	struct dwc3_request		*req;
1597 	int				starting;
1598 	int				ret;
1599 	u32				cmd;
1600 
1601 	/*
1602 	 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1603 	 * This happens when we need to stop and restart a transfer such as in
1604 	 * the case of reinitiating a stream or retrying an isoc transfer.
1605 	 */
1606 	ret = dwc3_prepare_trbs(dep);
1607 	if (ret < 0)
1608 		return ret;
1609 
1610 	starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1611 
1612 	/*
1613 	 * If there's no new TRB prepared and we don't need to restart a
1614 	 * transfer, there's no need to update the transfer.
1615 	 */
1616 	if (!ret && !starting)
1617 		return ret;
1618 
1619 	req = next_request(&dep->started_list);
1620 	if (!req) {
1621 		dep->flags |= DWC3_EP_PENDING_REQUEST;
1622 		return 0;
1623 	}
1624 
1625 	memset(&params, 0, sizeof(params));
1626 
1627 	if (starting) {
1628 		params.param0 = upper_32_bits(req->trb_dma);
1629 		params.param1 = lower_32_bits(req->trb_dma);
1630 		cmd = DWC3_DEPCMD_STARTTRANSFER;
1631 
1632 		if (dep->stream_capable)
1633 			cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1634 
1635 		if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1636 			cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1637 	} else {
1638 		cmd = DWC3_DEPCMD_UPDATETRANSFER |
1639 			DWC3_DEPCMD_PARAM(dep->resource_index);
1640 	}
1641 
1642 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1643 	if (ret < 0) {
1644 		struct dwc3_request *tmp;
1645 
1646 		if (ret == -EAGAIN)
1647 			return ret;
1648 
1649 		dwc3_stop_active_transfer(dep, true, true);
1650 
1651 		list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1652 			dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1653 
1654 		/* If ep isn't started, then there's no end transfer pending */
1655 		if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1656 			dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1657 
1658 		return ret;
1659 	}
1660 
1661 	if (dep->stream_capable && req->request.is_last &&
1662 	    !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1663 		dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1664 
1665 	return 0;
1666 }
1667 
1668 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1669 {
1670 	u32			reg;
1671 
1672 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1673 	return DWC3_DSTS_SOFFN(reg);
1674 }
1675 
1676 /**
1677  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1678  * @dep: isoc endpoint
1679  *
1680  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1681  * microframe number reported by the XferNotReady event for the future frame
1682  * number to start the isoc transfer.
1683  *
1684  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1685  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1686  * XferNotReady event are invalid. The driver uses this number to schedule the
1687  * isochronous transfer and passes it to the START TRANSFER command. Because
1688  * this number is invalid, the command may fail. If BIT[15:14] matches the
1689  * internal 16-bit microframe, the START TRANSFER command will pass and the
1690  * transfer will start at the scheduled time, if it is off by 1, the command
1691  * will still pass, but the transfer will start 2 seconds in the future. For all
1692  * other conditions, the START TRANSFER command will fail with bus-expiry.
1693  *
1694  * In order to workaround this issue, we can test for the correct combination of
1695  * BIT[15:14] by sending START TRANSFER commands with different values of
1696  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1697  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1698  * As the result, within the 4 possible combinations for BIT[15:14], there will
1699  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1700  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1701  * value is the correct combination.
1702  *
1703  * Since there are only 4 outcomes and the results are ordered, we can simply
1704  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1705  * deduce the smaller successful combination.
1706  *
1707  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1708  * of BIT[15:14]. The correct combination is as follow:
1709  *
1710  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1711  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1712  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1713  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1714  *
1715  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1716  * endpoints.
1717  */
1718 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1719 {
1720 	int cmd_status = 0;
1721 	bool test0;
1722 	bool test1;
1723 
1724 	while (dep->combo_num < 2) {
1725 		struct dwc3_gadget_ep_cmd_params params;
1726 		u32 test_frame_number;
1727 		u32 cmd;
1728 
1729 		/*
1730 		 * Check if we can start isoc transfer on the next interval or
1731 		 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1732 		 */
1733 		test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1734 		test_frame_number |= dep->combo_num << 14;
1735 		test_frame_number += max_t(u32, 4, dep->interval);
1736 
1737 		params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1738 		params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1739 
1740 		cmd = DWC3_DEPCMD_STARTTRANSFER;
1741 		cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1742 		cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1743 
1744 		/* Redo if some other failure beside bus-expiry is received */
1745 		if (cmd_status && cmd_status != -EAGAIN) {
1746 			dep->start_cmd_status = 0;
1747 			dep->combo_num = 0;
1748 			return 0;
1749 		}
1750 
1751 		/* Store the first test status */
1752 		if (dep->combo_num == 0)
1753 			dep->start_cmd_status = cmd_status;
1754 
1755 		dep->combo_num++;
1756 
1757 		/*
1758 		 * End the transfer if the START_TRANSFER command is successful
1759 		 * to wait for the next XferNotReady to test the command again
1760 		 */
1761 		if (cmd_status == 0) {
1762 			dwc3_stop_active_transfer(dep, true, true);
1763 			return 0;
1764 		}
1765 	}
1766 
1767 	/* test0 and test1 are both completed at this point */
1768 	test0 = (dep->start_cmd_status == 0);
1769 	test1 = (cmd_status == 0);
1770 
1771 	if (!test0 && test1)
1772 		dep->combo_num = 1;
1773 	else if (!test0 && !test1)
1774 		dep->combo_num = 2;
1775 	else if (test0 && !test1)
1776 		dep->combo_num = 3;
1777 	else if (test0 && test1)
1778 		dep->combo_num = 0;
1779 
1780 	dep->frame_number &= DWC3_FRNUMBER_MASK;
1781 	dep->frame_number |= dep->combo_num << 14;
1782 	dep->frame_number += max_t(u32, 4, dep->interval);
1783 
1784 	/* Reinitialize test variables */
1785 	dep->start_cmd_status = 0;
1786 	dep->combo_num = 0;
1787 
1788 	return __dwc3_gadget_kick_transfer(dep);
1789 }
1790 
1791 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1792 {
1793 	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1794 	struct dwc3 *dwc = dep->dwc;
1795 	int ret;
1796 	int i;
1797 
1798 	if (list_empty(&dep->pending_list) &&
1799 	    list_empty(&dep->started_list)) {
1800 		dep->flags |= DWC3_EP_PENDING_REQUEST;
1801 		return -EAGAIN;
1802 	}
1803 
1804 	if (!dwc->dis_start_transfer_quirk &&
1805 	    (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1806 	     DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1807 		if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1808 			return dwc3_gadget_start_isoc_quirk(dep);
1809 	}
1810 
1811 	if (desc->bInterval <= 14 &&
1812 	    dwc->gadget->speed >= USB_SPEED_HIGH) {
1813 		u32 frame = __dwc3_gadget_get_frame(dwc);
1814 		bool rollover = frame <
1815 				(dep->frame_number & DWC3_FRNUMBER_MASK);
1816 
1817 		/*
1818 		 * frame_number is set from XferNotReady and may be already
1819 		 * out of date. DSTS only provides the lower 14 bit of the
1820 		 * current frame number. So add the upper two bits of
1821 		 * frame_number and handle a possible rollover.
1822 		 * This will provide the correct frame_number unless more than
1823 		 * rollover has happened since XferNotReady.
1824 		 */
1825 
1826 		dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1827 				     frame;
1828 		if (rollover)
1829 			dep->frame_number += BIT(14);
1830 	}
1831 
1832 	for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1833 		dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1834 
1835 		ret = __dwc3_gadget_kick_transfer(dep);
1836 		if (ret != -EAGAIN)
1837 			break;
1838 	}
1839 
1840 	/*
1841 	 * After a number of unsuccessful start attempts due to bus-expiry
1842 	 * status, issue END_TRANSFER command and retry on the next XferNotReady
1843 	 * event.
1844 	 */
1845 	if (ret == -EAGAIN) {
1846 		struct dwc3_gadget_ep_cmd_params params;
1847 		u32 cmd;
1848 
1849 		cmd = DWC3_DEPCMD_ENDTRANSFER |
1850 			DWC3_DEPCMD_CMDIOC |
1851 			DWC3_DEPCMD_PARAM(dep->resource_index);
1852 
1853 		dep->resource_index = 0;
1854 		memset(&params, 0, sizeof(params));
1855 
1856 		ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1857 		if (!ret)
1858 			dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1859 	}
1860 
1861 	return ret;
1862 }
1863 
1864 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1865 {
1866 	struct dwc3		*dwc = dep->dwc;
1867 
1868 	if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1869 		dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1870 				dep->name);
1871 		return -ESHUTDOWN;
1872 	}
1873 
1874 	if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1875 				&req->request, req->dep->name))
1876 		return -EINVAL;
1877 
1878 	if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1879 				"%s: request %pK already in flight\n",
1880 				dep->name, &req->request))
1881 		return -EINVAL;
1882 
1883 	pm_runtime_get(dwc->dev);
1884 
1885 	req->request.actual	= 0;
1886 	req->request.status	= -EINPROGRESS;
1887 
1888 	trace_dwc3_ep_queue(req);
1889 
1890 	list_add_tail(&req->list, &dep->pending_list);
1891 	req->status = DWC3_REQUEST_STATUS_QUEUED;
1892 
1893 	if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1894 		return 0;
1895 
1896 	/*
1897 	 * Start the transfer only after the END_TRANSFER is completed
1898 	 * and endpoint STALL is cleared.
1899 	 */
1900 	if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1901 	    (dep->flags & DWC3_EP_WEDGE) ||
1902 	    (dep->flags & DWC3_EP_STALL)) {
1903 		dep->flags |= DWC3_EP_DELAY_START;
1904 		return 0;
1905 	}
1906 
1907 	/*
1908 	 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1909 	 * wait for a XferNotReady event so we will know what's the current
1910 	 * (micro-)frame number.
1911 	 *
1912 	 * Without this trick, we are very, very likely gonna get Bus Expiry
1913 	 * errors which will force us issue EndTransfer command.
1914 	 */
1915 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1916 		if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1917 				!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1918 			return 0;
1919 
1920 		if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1921 			if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1922 				return __dwc3_gadget_start_isoc(dep);
1923 		}
1924 	}
1925 
1926 	__dwc3_gadget_kick_transfer(dep);
1927 
1928 	return 0;
1929 }
1930 
1931 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1932 	gfp_t gfp_flags)
1933 {
1934 	struct dwc3_request		*req = to_dwc3_request(request);
1935 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1936 	struct dwc3			*dwc = dep->dwc;
1937 
1938 	unsigned long			flags;
1939 
1940 	int				ret;
1941 
1942 	spin_lock_irqsave(&dwc->lock, flags);
1943 	ret = __dwc3_gadget_ep_queue(dep, req);
1944 	spin_unlock_irqrestore(&dwc->lock, flags);
1945 
1946 	return ret;
1947 }
1948 
1949 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1950 {
1951 	int i;
1952 
1953 	/* If req->trb is not set, then the request has not started */
1954 	if (!req->trb)
1955 		return;
1956 
1957 	/*
1958 	 * If request was already started, this means we had to
1959 	 * stop the transfer. With that we also need to ignore
1960 	 * all TRBs used by the request, however TRBs can only
1961 	 * be modified after completion of END_TRANSFER
1962 	 * command. So what we do here is that we wait for
1963 	 * END_TRANSFER completion and only after that, we jump
1964 	 * over TRBs by clearing HWO and incrementing dequeue
1965 	 * pointer.
1966 	 */
1967 	for (i = 0; i < req->num_trbs; i++) {
1968 		struct dwc3_trb *trb;
1969 
1970 		trb = &dep->trb_pool[dep->trb_dequeue];
1971 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1972 		dwc3_ep_inc_deq(dep);
1973 	}
1974 
1975 	req->num_trbs = 0;
1976 }
1977 
1978 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1979 {
1980 	struct dwc3_request		*req;
1981 	struct dwc3_request		*tmp;
1982 	struct dwc3			*dwc = dep->dwc;
1983 
1984 	list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1985 		dwc3_gadget_ep_skip_trbs(dep, req);
1986 		switch (req->status) {
1987 		case DWC3_REQUEST_STATUS_DISCONNECTED:
1988 			dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1989 			break;
1990 		case DWC3_REQUEST_STATUS_DEQUEUED:
1991 			dwc3_gadget_giveback(dep, req, -ECONNRESET);
1992 			break;
1993 		case DWC3_REQUEST_STATUS_STALLED:
1994 			dwc3_gadget_giveback(dep, req, -EPIPE);
1995 			break;
1996 		default:
1997 			dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1998 			dwc3_gadget_giveback(dep, req, -ECONNRESET);
1999 			break;
2000 		}
2001 	}
2002 }
2003 
2004 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2005 		struct usb_request *request)
2006 {
2007 	struct dwc3_request		*req = to_dwc3_request(request);
2008 	struct dwc3_request		*r = NULL;
2009 
2010 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
2011 	struct dwc3			*dwc = dep->dwc;
2012 
2013 	unsigned long			flags;
2014 	int				ret = 0;
2015 
2016 	trace_dwc3_ep_dequeue(req);
2017 
2018 	spin_lock_irqsave(&dwc->lock, flags);
2019 
2020 	list_for_each_entry(r, &dep->cancelled_list, list) {
2021 		if (r == req)
2022 			goto out;
2023 	}
2024 
2025 	list_for_each_entry(r, &dep->pending_list, list) {
2026 		if (r == req) {
2027 			dwc3_gadget_giveback(dep, req, -ECONNRESET);
2028 			goto out;
2029 		}
2030 	}
2031 
2032 	list_for_each_entry(r, &dep->started_list, list) {
2033 		if (r == req) {
2034 			struct dwc3_request *t;
2035 
2036 			/* wait until it is processed */
2037 			dwc3_stop_active_transfer(dep, true, true);
2038 
2039 			/*
2040 			 * Remove any started request if the transfer is
2041 			 * cancelled.
2042 			 */
2043 			list_for_each_entry_safe(r, t, &dep->started_list, list)
2044 				dwc3_gadget_move_cancelled_request(r,
2045 						DWC3_REQUEST_STATUS_DEQUEUED);
2046 
2047 			dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2048 
2049 			goto out;
2050 		}
2051 	}
2052 
2053 	dev_err(dwc->dev, "request %pK was not queued to %s\n",
2054 		request, ep->name);
2055 	ret = -EINVAL;
2056 out:
2057 	spin_unlock_irqrestore(&dwc->lock, flags);
2058 
2059 	return ret;
2060 }
2061 
2062 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2063 {
2064 	struct dwc3_gadget_ep_cmd_params	params;
2065 	struct dwc3				*dwc = dep->dwc;
2066 	struct dwc3_request			*req;
2067 	struct dwc3_request			*tmp;
2068 	int					ret;
2069 
2070 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2071 		dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2072 		return -EINVAL;
2073 	}
2074 
2075 	memset(&params, 0x00, sizeof(params));
2076 
2077 	if (value) {
2078 		struct dwc3_trb *trb;
2079 
2080 		unsigned int transfer_in_flight;
2081 		unsigned int started;
2082 
2083 		if (dep->number > 1)
2084 			trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2085 		else
2086 			trb = &dwc->ep0_trb[dep->trb_enqueue];
2087 
2088 		transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2089 		started = !list_empty(&dep->started_list);
2090 
2091 		if (!protocol && ((dep->direction && transfer_in_flight) ||
2092 				(!dep->direction && started))) {
2093 			return -EAGAIN;
2094 		}
2095 
2096 		ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2097 				&params);
2098 		if (ret)
2099 			dev_err(dwc->dev, "failed to set STALL on %s\n",
2100 					dep->name);
2101 		else
2102 			dep->flags |= DWC3_EP_STALL;
2103 	} else {
2104 		/*
2105 		 * Don't issue CLEAR_STALL command to control endpoints. The
2106 		 * controller automatically clears the STALL when it receives
2107 		 * the SETUP token.
2108 		 */
2109 		if (dep->number <= 1) {
2110 			dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2111 			return 0;
2112 		}
2113 
2114 		dwc3_stop_active_transfer(dep, true, true);
2115 
2116 		list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2117 			dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2118 
2119 		if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
2120 			dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2121 			return 0;
2122 		}
2123 
2124 		dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2125 
2126 		ret = dwc3_send_clear_stall_ep_cmd(dep);
2127 		if (ret) {
2128 			dev_err(dwc->dev, "failed to clear STALL on %s\n",
2129 					dep->name);
2130 			return ret;
2131 		}
2132 
2133 		dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2134 
2135 		if ((dep->flags & DWC3_EP_DELAY_START) &&
2136 		    !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2137 			__dwc3_gadget_kick_transfer(dep);
2138 
2139 		dep->flags &= ~DWC3_EP_DELAY_START;
2140 	}
2141 
2142 	return ret;
2143 }
2144 
2145 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2146 {
2147 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
2148 	struct dwc3			*dwc = dep->dwc;
2149 
2150 	unsigned long			flags;
2151 
2152 	int				ret;
2153 
2154 	spin_lock_irqsave(&dwc->lock, flags);
2155 	ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2156 	spin_unlock_irqrestore(&dwc->lock, flags);
2157 
2158 	return ret;
2159 }
2160 
2161 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2162 {
2163 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
2164 	struct dwc3			*dwc = dep->dwc;
2165 	unsigned long			flags;
2166 	int				ret;
2167 
2168 	spin_lock_irqsave(&dwc->lock, flags);
2169 	dep->flags |= DWC3_EP_WEDGE;
2170 
2171 	if (dep->number == 0 || dep->number == 1)
2172 		ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2173 	else
2174 		ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2175 	spin_unlock_irqrestore(&dwc->lock, flags);
2176 
2177 	return ret;
2178 }
2179 
2180 /* -------------------------------------------------------------------------- */
2181 
2182 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2183 	.bLength	= USB_DT_ENDPOINT_SIZE,
2184 	.bDescriptorType = USB_DT_ENDPOINT,
2185 	.bmAttributes	= USB_ENDPOINT_XFER_CONTROL,
2186 };
2187 
2188 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2189 	.enable		= dwc3_gadget_ep0_enable,
2190 	.disable	= dwc3_gadget_ep0_disable,
2191 	.alloc_request	= dwc3_gadget_ep_alloc_request,
2192 	.free_request	= dwc3_gadget_ep_free_request,
2193 	.queue		= dwc3_gadget_ep0_queue,
2194 	.dequeue	= dwc3_gadget_ep_dequeue,
2195 	.set_halt	= dwc3_gadget_ep0_set_halt,
2196 	.set_wedge	= dwc3_gadget_ep_set_wedge,
2197 };
2198 
2199 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2200 	.enable		= dwc3_gadget_ep_enable,
2201 	.disable	= dwc3_gadget_ep_disable,
2202 	.alloc_request	= dwc3_gadget_ep_alloc_request,
2203 	.free_request	= dwc3_gadget_ep_free_request,
2204 	.queue		= dwc3_gadget_ep_queue,
2205 	.dequeue	= dwc3_gadget_ep_dequeue,
2206 	.set_halt	= dwc3_gadget_ep_set_halt,
2207 	.set_wedge	= dwc3_gadget_ep_set_wedge,
2208 };
2209 
2210 /* -------------------------------------------------------------------------- */
2211 
2212 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2213 {
2214 	struct dwc3		*dwc = gadget_to_dwc(g);
2215 
2216 	return __dwc3_gadget_get_frame(dwc);
2217 }
2218 
2219 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2220 {
2221 	int			retries;
2222 
2223 	int			ret;
2224 	u32			reg;
2225 
2226 	u8			link_state;
2227 
2228 	/*
2229 	 * According to the Databook Remote wakeup request should
2230 	 * be issued only when the device is in early suspend state.
2231 	 *
2232 	 * We can check that via USB Link State bits in DSTS register.
2233 	 */
2234 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2235 
2236 	link_state = DWC3_DSTS_USBLNKST(reg);
2237 
2238 	switch (link_state) {
2239 	case DWC3_LINK_STATE_RESET:
2240 	case DWC3_LINK_STATE_RX_DET:	/* in HS, means Early Suspend */
2241 	case DWC3_LINK_STATE_U3:	/* in HS, means SUSPEND */
2242 	case DWC3_LINK_STATE_U2:	/* in HS, means Sleep (L1) */
2243 	case DWC3_LINK_STATE_U1:
2244 	case DWC3_LINK_STATE_RESUME:
2245 		break;
2246 	default:
2247 		return -EINVAL;
2248 	}
2249 
2250 	ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2251 	if (ret < 0) {
2252 		dev_err(dwc->dev, "failed to put link in Recovery\n");
2253 		return ret;
2254 	}
2255 
2256 	/* Recent versions do this automatically */
2257 	if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2258 		/* write zeroes to Link Change Request */
2259 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2260 		reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2261 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2262 	}
2263 
2264 	/* poll until Link State changes to ON */
2265 	retries = 20000;
2266 
2267 	while (retries--) {
2268 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2269 
2270 		/* in HS, means ON */
2271 		if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2272 			break;
2273 	}
2274 
2275 	if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2276 		dev_err(dwc->dev, "failed to send remote wakeup\n");
2277 		return -EINVAL;
2278 	}
2279 
2280 	return 0;
2281 }
2282 
2283 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2284 {
2285 	struct dwc3		*dwc = gadget_to_dwc(g);
2286 	unsigned long		flags;
2287 	int			ret;
2288 
2289 	spin_lock_irqsave(&dwc->lock, flags);
2290 	ret = __dwc3_gadget_wakeup(dwc);
2291 	spin_unlock_irqrestore(&dwc->lock, flags);
2292 
2293 	return ret;
2294 }
2295 
2296 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2297 		int is_selfpowered)
2298 {
2299 	struct dwc3		*dwc = gadget_to_dwc(g);
2300 	unsigned long		flags;
2301 
2302 	spin_lock_irqsave(&dwc->lock, flags);
2303 	g->is_selfpowered = !!is_selfpowered;
2304 	spin_unlock_irqrestore(&dwc->lock, flags);
2305 
2306 	return 0;
2307 }
2308 
2309 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2310 {
2311 	u32 epnum;
2312 
2313 	for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2314 		struct dwc3_ep *dep;
2315 
2316 		dep = dwc->eps[epnum];
2317 		if (!dep)
2318 			continue;
2319 
2320 		dwc3_remove_requests(dwc, dep);
2321 	}
2322 }
2323 
2324 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2325 {
2326 	enum usb_ssp_rate	ssp_rate = dwc->gadget_ssp_rate;
2327 	u32			reg;
2328 
2329 	if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2330 		ssp_rate = dwc->max_ssp_rate;
2331 
2332 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2333 	reg &= ~DWC3_DCFG_SPEED_MASK;
2334 	reg &= ~DWC3_DCFG_NUMLANES(~0);
2335 
2336 	if (ssp_rate == USB_SSP_GEN_1x2)
2337 		reg |= DWC3_DCFG_SUPERSPEED;
2338 	else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2339 		reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2340 
2341 	if (ssp_rate != USB_SSP_GEN_2x1 &&
2342 	    dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2343 		reg |= DWC3_DCFG_NUMLANES(1);
2344 
2345 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2346 }
2347 
2348 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2349 {
2350 	enum usb_device_speed	speed;
2351 	u32			reg;
2352 
2353 	speed = dwc->gadget_max_speed;
2354 	if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2355 		speed = dwc->maximum_speed;
2356 
2357 	if (speed == USB_SPEED_SUPER_PLUS &&
2358 	    DWC3_IP_IS(DWC32)) {
2359 		__dwc3_gadget_set_ssp_rate(dwc);
2360 		return;
2361 	}
2362 
2363 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2364 	reg &= ~(DWC3_DCFG_SPEED_MASK);
2365 
2366 	/*
2367 	 * WORKAROUND: DWC3 revision < 2.20a have an issue
2368 	 * which would cause metastability state on Run/Stop
2369 	 * bit if we try to force the IP to USB2-only mode.
2370 	 *
2371 	 * Because of that, we cannot configure the IP to any
2372 	 * speed other than the SuperSpeed
2373 	 *
2374 	 * Refers to:
2375 	 *
2376 	 * STAR#9000525659: Clock Domain Crossing on DCTL in
2377 	 * USB 2.0 Mode
2378 	 */
2379 	if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2380 	    !dwc->dis_metastability_quirk) {
2381 		reg |= DWC3_DCFG_SUPERSPEED;
2382 	} else {
2383 		switch (speed) {
2384 		case USB_SPEED_FULL:
2385 			reg |= DWC3_DCFG_FULLSPEED;
2386 			break;
2387 		case USB_SPEED_HIGH:
2388 			reg |= DWC3_DCFG_HIGHSPEED;
2389 			break;
2390 		case USB_SPEED_SUPER:
2391 			reg |= DWC3_DCFG_SUPERSPEED;
2392 			break;
2393 		case USB_SPEED_SUPER_PLUS:
2394 			if (DWC3_IP_IS(DWC3))
2395 				reg |= DWC3_DCFG_SUPERSPEED;
2396 			else
2397 				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2398 			break;
2399 		default:
2400 			dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2401 
2402 			if (DWC3_IP_IS(DWC3))
2403 				reg |= DWC3_DCFG_SUPERSPEED;
2404 			else
2405 				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2406 		}
2407 	}
2408 
2409 	if (DWC3_IP_IS(DWC32) &&
2410 	    speed > USB_SPEED_UNKNOWN &&
2411 	    speed < USB_SPEED_SUPER_PLUS)
2412 		reg &= ~DWC3_DCFG_NUMLANES(~0);
2413 
2414 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2415 }
2416 
2417 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2418 {
2419 	u32			reg;
2420 	u32			timeout = 500;
2421 
2422 	if (pm_runtime_suspended(dwc->dev))
2423 		return 0;
2424 
2425 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2426 	if (is_on) {
2427 		if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2428 			reg &= ~DWC3_DCTL_TRGTULST_MASK;
2429 			reg |= DWC3_DCTL_TRGTULST_RX_DET;
2430 		}
2431 
2432 		if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2433 			reg &= ~DWC3_DCTL_KEEP_CONNECT;
2434 		reg |= DWC3_DCTL_RUN_STOP;
2435 
2436 		if (dwc->has_hibernation)
2437 			reg |= DWC3_DCTL_KEEP_CONNECT;
2438 
2439 		__dwc3_gadget_set_speed(dwc);
2440 		dwc->pullups_connected = true;
2441 	} else {
2442 		reg &= ~DWC3_DCTL_RUN_STOP;
2443 
2444 		if (dwc->has_hibernation && !suspend)
2445 			reg &= ~DWC3_DCTL_KEEP_CONNECT;
2446 
2447 		dwc->pullups_connected = false;
2448 	}
2449 
2450 	dwc3_gadget_dctl_write_safe(dwc, reg);
2451 
2452 	do {
2453 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2454 		reg &= DWC3_DSTS_DEVCTRLHLT;
2455 	} while (--timeout && !(!is_on ^ !reg));
2456 
2457 	if (!timeout)
2458 		return -ETIMEDOUT;
2459 
2460 	return 0;
2461 }
2462 
2463 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2464 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2465 static int __dwc3_gadget_start(struct dwc3 *dwc);
2466 
2467 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2468 {
2469 	struct dwc3		*dwc = gadget_to_dwc(g);
2470 	unsigned long		flags;
2471 	int			ret;
2472 
2473 	is_on = !!is_on;
2474 	dwc->softconnect = is_on;
2475 	/*
2476 	 * Per databook, when we want to stop the gadget, if a control transfer
2477 	 * is still in process, complete it and get the core into setup phase.
2478 	 */
2479 	if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2480 		reinit_completion(&dwc->ep0_in_setup);
2481 
2482 		ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2483 				msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2484 		if (ret == 0)
2485 			dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2486 	}
2487 
2488 	/*
2489 	 * Avoid issuing a runtime resume if the device is already in the
2490 	 * suspended state during gadget disconnect.  DWC3 gadget was already
2491 	 * halted/stopped during runtime suspend.
2492 	 */
2493 	if (!is_on) {
2494 		pm_runtime_barrier(dwc->dev);
2495 		if (pm_runtime_suspended(dwc->dev))
2496 			return 0;
2497 	}
2498 
2499 	/*
2500 	 * Check the return value for successful resume, or error.  For a
2501 	 * successful resume, the DWC3 runtime PM resume routine will handle
2502 	 * the run stop sequence, so avoid duplicate operations here.
2503 	 */
2504 	ret = pm_runtime_get_sync(dwc->dev);
2505 	if (!ret || ret < 0) {
2506 		pm_runtime_put(dwc->dev);
2507 		return 0;
2508 	}
2509 
2510 	/*
2511 	 * Synchronize and disable any further event handling while controller
2512 	 * is being enabled/disabled.
2513 	 */
2514 	disable_irq(dwc->irq_gadget);
2515 
2516 	spin_lock_irqsave(&dwc->lock, flags);
2517 
2518 	if (!is_on) {
2519 		u32 count;
2520 
2521 		dwc->connected = false;
2522 		/*
2523 		 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2524 		 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2525 		 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2526 		 * command for any active transfers" before clearing the RunStop
2527 		 * bit.
2528 		 */
2529 		dwc3_stop_active_transfers(dwc);
2530 		__dwc3_gadget_stop(dwc);
2531 
2532 		/*
2533 		 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2534 		 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2535 		 * "software needs to acknowledge the events that are generated
2536 		 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2537 		 * to be set to '1'."
2538 		 */
2539 		count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2540 		count &= DWC3_GEVNTCOUNT_MASK;
2541 		if (count > 0) {
2542 			dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2543 			dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2544 						dwc->ev_buf->length;
2545 		}
2546 	} else {
2547 		__dwc3_gadget_start(dwc);
2548 	}
2549 
2550 	ret = dwc3_gadget_run_stop(dwc, is_on, false);
2551 	spin_unlock_irqrestore(&dwc->lock, flags);
2552 	enable_irq(dwc->irq_gadget);
2553 
2554 	pm_runtime_put(dwc->dev);
2555 
2556 	return ret;
2557 }
2558 
2559 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2560 {
2561 	u32			reg;
2562 
2563 	/* Enable all but Start and End of Frame IRQs */
2564 	reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2565 			DWC3_DEVTEN_CMDCMPLTEN |
2566 			DWC3_DEVTEN_ERRTICERREN |
2567 			DWC3_DEVTEN_WKUPEVTEN |
2568 			DWC3_DEVTEN_CONNECTDONEEN |
2569 			DWC3_DEVTEN_USBRSTEN |
2570 			DWC3_DEVTEN_DISCONNEVTEN);
2571 
2572 	if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2573 		reg |= DWC3_DEVTEN_ULSTCNGEN;
2574 
2575 	/* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2576 	if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2577 		reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2578 
2579 	dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2580 }
2581 
2582 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2583 {
2584 	/* mask all interrupts */
2585 	dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2586 }
2587 
2588 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2589 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2590 
2591 /**
2592  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2593  * @dwc: pointer to our context structure
2594  *
2595  * The following looks like complex but it's actually very simple. In order to
2596  * calculate the number of packets we can burst at once on OUT transfers, we're
2597  * gonna use RxFIFO size.
2598  *
2599  * To calculate RxFIFO size we need two numbers:
2600  * MDWIDTH = size, in bits, of the internal memory bus
2601  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2602  *
2603  * Given these two numbers, the formula is simple:
2604  *
2605  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2606  *
2607  * 24 bytes is for 3x SETUP packets
2608  * 16 bytes is a clock domain crossing tolerance
2609  *
2610  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2611  */
2612 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2613 {
2614 	u32 ram2_depth;
2615 	u32 mdwidth;
2616 	u32 nump;
2617 	u32 reg;
2618 
2619 	ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2620 	mdwidth = dwc3_mdwidth(dwc);
2621 
2622 	nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2623 	nump = min_t(u32, nump, 16);
2624 
2625 	/* update NumP */
2626 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2627 	reg &= ~DWC3_DCFG_NUMP_MASK;
2628 	reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2629 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2630 }
2631 
2632 static int __dwc3_gadget_start(struct dwc3 *dwc)
2633 {
2634 	struct dwc3_ep		*dep;
2635 	int			ret = 0;
2636 	u32			reg;
2637 
2638 	/*
2639 	 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2640 	 * the core supports IMOD, disable it.
2641 	 */
2642 	if (dwc->imod_interval) {
2643 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2644 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2645 	} else if (dwc3_has_imod(dwc)) {
2646 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2647 	}
2648 
2649 	/*
2650 	 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2651 	 * field instead of letting dwc3 itself calculate that automatically.
2652 	 *
2653 	 * This way, we maximize the chances that we'll be able to get several
2654 	 * bursts of data without going through any sort of endpoint throttling.
2655 	 */
2656 	reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2657 	if (DWC3_IP_IS(DWC3))
2658 		reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2659 	else
2660 		reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2661 
2662 	dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2663 
2664 	dwc3_gadget_setup_nump(dwc);
2665 
2666 	/*
2667 	 * Currently the controller handles single stream only. So, Ignore
2668 	 * Packet Pending bit for stream selection and don't search for another
2669 	 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2670 	 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2671 	 * the stream performance.
2672 	 */
2673 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2674 	reg |= DWC3_DCFG_IGNSTRMPP;
2675 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2676 
2677 	/* Enable MST by default if the device is capable of MST */
2678 	if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2679 		reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2680 		reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2681 		dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2682 	}
2683 
2684 	/* Start with SuperSpeed Default */
2685 	dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2686 
2687 	dep = dwc->eps[0];
2688 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2689 	if (ret) {
2690 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2691 		goto err0;
2692 	}
2693 
2694 	dep = dwc->eps[1];
2695 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2696 	if (ret) {
2697 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2698 		goto err1;
2699 	}
2700 
2701 	/* begin to receive SETUP packets */
2702 	dwc->ep0state = EP0_SETUP_PHASE;
2703 	dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2704 	dwc->delayed_status = false;
2705 	dwc3_ep0_out_start(dwc);
2706 
2707 	dwc3_gadget_enable_irq(dwc);
2708 
2709 	return 0;
2710 
2711 err1:
2712 	__dwc3_gadget_ep_disable(dwc->eps[0]);
2713 
2714 err0:
2715 	return ret;
2716 }
2717 
2718 static int dwc3_gadget_start(struct usb_gadget *g,
2719 		struct usb_gadget_driver *driver)
2720 {
2721 	struct dwc3		*dwc = gadget_to_dwc(g);
2722 	unsigned long		flags;
2723 	int			ret;
2724 	int			irq;
2725 
2726 	irq = dwc->irq_gadget;
2727 	ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2728 			IRQF_SHARED, "dwc3", dwc->ev_buf);
2729 	if (ret) {
2730 		dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2731 				irq, ret);
2732 		return ret;
2733 	}
2734 
2735 	spin_lock_irqsave(&dwc->lock, flags);
2736 	dwc->gadget_driver	= driver;
2737 	spin_unlock_irqrestore(&dwc->lock, flags);
2738 
2739 	return 0;
2740 }
2741 
2742 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2743 {
2744 	dwc3_gadget_disable_irq(dwc);
2745 	__dwc3_gadget_ep_disable(dwc->eps[0]);
2746 	__dwc3_gadget_ep_disable(dwc->eps[1]);
2747 }
2748 
2749 static int dwc3_gadget_stop(struct usb_gadget *g)
2750 {
2751 	struct dwc3		*dwc = gadget_to_dwc(g);
2752 	unsigned long		flags;
2753 
2754 	spin_lock_irqsave(&dwc->lock, flags);
2755 	dwc->gadget_driver	= NULL;
2756 	dwc->max_cfg_eps = 0;
2757 	spin_unlock_irqrestore(&dwc->lock, flags);
2758 
2759 	free_irq(dwc->irq_gadget, dwc->ev_buf);
2760 
2761 	return 0;
2762 }
2763 
2764 static void dwc3_gadget_config_params(struct usb_gadget *g,
2765 				      struct usb_dcd_config_params *params)
2766 {
2767 	struct dwc3		*dwc = gadget_to_dwc(g);
2768 
2769 	params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2770 	params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2771 
2772 	/* Recommended BESL */
2773 	if (!dwc->dis_enblslpm_quirk) {
2774 		/*
2775 		 * If the recommended BESL baseline is 0 or if the BESL deep is
2776 		 * less than 2, Microsoft's Windows 10 host usb stack will issue
2777 		 * a usb reset immediately after it receives the extended BOS
2778 		 * descriptor and the enumeration will fail. To maintain
2779 		 * compatibility with the Windows' usb stack, let's set the
2780 		 * recommended BESL baseline to 1 and clamp the BESL deep to be
2781 		 * within 2 to 15.
2782 		 */
2783 		params->besl_baseline = 1;
2784 		if (dwc->is_utmi_l1_suspend)
2785 			params->besl_deep =
2786 				clamp_t(u8, dwc->hird_threshold, 2, 15);
2787 	}
2788 
2789 	/* U1 Device exit Latency */
2790 	if (dwc->dis_u1_entry_quirk)
2791 		params->bU1devExitLat = 0;
2792 	else
2793 		params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2794 
2795 	/* U2 Device exit Latency */
2796 	if (dwc->dis_u2_entry_quirk)
2797 		params->bU2DevExitLat = 0;
2798 	else
2799 		params->bU2DevExitLat =
2800 				cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2801 }
2802 
2803 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2804 				  enum usb_device_speed speed)
2805 {
2806 	struct dwc3		*dwc = gadget_to_dwc(g);
2807 	unsigned long		flags;
2808 
2809 	spin_lock_irqsave(&dwc->lock, flags);
2810 	dwc->gadget_max_speed = speed;
2811 	spin_unlock_irqrestore(&dwc->lock, flags);
2812 }
2813 
2814 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2815 				     enum usb_ssp_rate rate)
2816 {
2817 	struct dwc3		*dwc = gadget_to_dwc(g);
2818 	unsigned long		flags;
2819 
2820 	spin_lock_irqsave(&dwc->lock, flags);
2821 	dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2822 	dwc->gadget_ssp_rate = rate;
2823 	spin_unlock_irqrestore(&dwc->lock, flags);
2824 }
2825 
2826 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2827 {
2828 	struct dwc3		*dwc = gadget_to_dwc(g);
2829 	union power_supply_propval	val = {0};
2830 	int				ret;
2831 
2832 	if (dwc->usb2_phy)
2833 		return usb_phy_set_power(dwc->usb2_phy, mA);
2834 
2835 	if (!dwc->usb_psy)
2836 		return -EOPNOTSUPP;
2837 
2838 	val.intval = 1000 * mA;
2839 	ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2840 
2841 	return ret;
2842 }
2843 
2844 /**
2845  * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2846  * @g: pointer to the USB gadget
2847  *
2848  * Used to record the maximum number of endpoints being used in a USB composite
2849  * device. (across all configurations)  This is to be used in the calculation
2850  * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2851  * It will help ensured that the resizing logic reserves enough space for at
2852  * least one max packet.
2853  */
2854 static int dwc3_gadget_check_config(struct usb_gadget *g)
2855 {
2856 	struct dwc3 *dwc = gadget_to_dwc(g);
2857 	struct usb_ep *ep;
2858 	int fifo_size = 0;
2859 	int ram1_depth;
2860 	int ep_num = 0;
2861 
2862 	if (!dwc->do_fifo_resize)
2863 		return 0;
2864 
2865 	list_for_each_entry(ep, &g->ep_list, ep_list) {
2866 		/* Only interested in the IN endpoints */
2867 		if (ep->claimed && (ep->address & USB_DIR_IN))
2868 			ep_num++;
2869 	}
2870 
2871 	if (ep_num <= dwc->max_cfg_eps)
2872 		return 0;
2873 
2874 	/* Update the max number of eps in the composition */
2875 	dwc->max_cfg_eps = ep_num;
2876 
2877 	fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2878 	/* Based on the equation, increment by one for every ep */
2879 	fifo_size += dwc->max_cfg_eps;
2880 
2881 	/* Check if we can fit a single fifo per endpoint */
2882 	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2883 	if (fifo_size > ram1_depth)
2884 		return -ENOMEM;
2885 
2886 	return 0;
2887 }
2888 
2889 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2890 {
2891 	struct dwc3		*dwc = gadget_to_dwc(g);
2892 	unsigned long		flags;
2893 
2894 	spin_lock_irqsave(&dwc->lock, flags);
2895 	dwc->async_callbacks = enable;
2896 	spin_unlock_irqrestore(&dwc->lock, flags);
2897 }
2898 
2899 static const struct usb_gadget_ops dwc3_gadget_ops = {
2900 	.get_frame		= dwc3_gadget_get_frame,
2901 	.wakeup			= dwc3_gadget_wakeup,
2902 	.set_selfpowered	= dwc3_gadget_set_selfpowered,
2903 	.pullup			= dwc3_gadget_pullup,
2904 	.udc_start		= dwc3_gadget_start,
2905 	.udc_stop		= dwc3_gadget_stop,
2906 	.udc_set_speed		= dwc3_gadget_set_speed,
2907 	.udc_set_ssp_rate	= dwc3_gadget_set_ssp_rate,
2908 	.get_config_params	= dwc3_gadget_config_params,
2909 	.vbus_draw		= dwc3_gadget_vbus_draw,
2910 	.check_config		= dwc3_gadget_check_config,
2911 	.udc_async_callbacks	= dwc3_gadget_async_callbacks,
2912 };
2913 
2914 /* -------------------------------------------------------------------------- */
2915 
2916 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2917 {
2918 	struct dwc3 *dwc = dep->dwc;
2919 
2920 	usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2921 	dep->endpoint.maxburst = 1;
2922 	dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2923 	if (!dep->direction)
2924 		dwc->gadget->ep0 = &dep->endpoint;
2925 
2926 	dep->endpoint.caps.type_control = true;
2927 
2928 	return 0;
2929 }
2930 
2931 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2932 {
2933 	struct dwc3 *dwc = dep->dwc;
2934 	u32 mdwidth;
2935 	int size;
2936 
2937 	mdwidth = dwc3_mdwidth(dwc);
2938 
2939 	/* MDWIDTH is represented in bits, we need it in bytes */
2940 	mdwidth /= 8;
2941 
2942 	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2943 	if (DWC3_IP_IS(DWC3))
2944 		size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2945 	else
2946 		size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2947 
2948 	/* FIFO Depth is in MDWDITH bytes. Multiply */
2949 	size *= mdwidth;
2950 
2951 	/*
2952 	 * To meet performance requirement, a minimum TxFIFO size of 3x
2953 	 * MaxPacketSize is recommended for endpoints that support burst and a
2954 	 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2955 	 * support burst. Use those numbers and we can calculate the max packet
2956 	 * limit as below.
2957 	 */
2958 	if (dwc->maximum_speed >= USB_SPEED_SUPER)
2959 		size /= 3;
2960 	else
2961 		size /= 2;
2962 
2963 	usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2964 
2965 	dep->endpoint.max_streams = 16;
2966 	dep->endpoint.ops = &dwc3_gadget_ep_ops;
2967 	list_add_tail(&dep->endpoint.ep_list,
2968 			&dwc->gadget->ep_list);
2969 	dep->endpoint.caps.type_iso = true;
2970 	dep->endpoint.caps.type_bulk = true;
2971 	dep->endpoint.caps.type_int = true;
2972 
2973 	return dwc3_alloc_trb_pool(dep);
2974 }
2975 
2976 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2977 {
2978 	struct dwc3 *dwc = dep->dwc;
2979 	u32 mdwidth;
2980 	int size;
2981 
2982 	mdwidth = dwc3_mdwidth(dwc);
2983 
2984 	/* MDWIDTH is represented in bits, convert to bytes */
2985 	mdwidth /= 8;
2986 
2987 	/* All OUT endpoints share a single RxFIFO space */
2988 	size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2989 	if (DWC3_IP_IS(DWC3))
2990 		size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2991 	else
2992 		size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2993 
2994 	/* FIFO depth is in MDWDITH bytes */
2995 	size *= mdwidth;
2996 
2997 	/*
2998 	 * To meet performance requirement, a minimum recommended RxFIFO size
2999 	 * is defined as follow:
3000 	 * RxFIFO size >= (3 x MaxPacketSize) +
3001 	 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3002 	 *
3003 	 * Then calculate the max packet limit as below.
3004 	 */
3005 	size -= (3 * 8) + 16;
3006 	if (size < 0)
3007 		size = 0;
3008 	else
3009 		size /= 3;
3010 
3011 	usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3012 	dep->endpoint.max_streams = 16;
3013 	dep->endpoint.ops = &dwc3_gadget_ep_ops;
3014 	list_add_tail(&dep->endpoint.ep_list,
3015 			&dwc->gadget->ep_list);
3016 	dep->endpoint.caps.type_iso = true;
3017 	dep->endpoint.caps.type_bulk = true;
3018 	dep->endpoint.caps.type_int = true;
3019 
3020 	return dwc3_alloc_trb_pool(dep);
3021 }
3022 
3023 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3024 {
3025 	struct dwc3_ep			*dep;
3026 	bool				direction = epnum & 1;
3027 	int				ret;
3028 	u8				num = epnum >> 1;
3029 
3030 	dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3031 	if (!dep)
3032 		return -ENOMEM;
3033 
3034 	dep->dwc = dwc;
3035 	dep->number = epnum;
3036 	dep->direction = direction;
3037 	dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3038 	dwc->eps[epnum] = dep;
3039 	dep->combo_num = 0;
3040 	dep->start_cmd_status = 0;
3041 
3042 	snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3043 			direction ? "in" : "out");
3044 
3045 	dep->endpoint.name = dep->name;
3046 
3047 	if (!(dep->number > 1)) {
3048 		dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3049 		dep->endpoint.comp_desc = NULL;
3050 	}
3051 
3052 	if (num == 0)
3053 		ret = dwc3_gadget_init_control_endpoint(dep);
3054 	else if (direction)
3055 		ret = dwc3_gadget_init_in_endpoint(dep);
3056 	else
3057 		ret = dwc3_gadget_init_out_endpoint(dep);
3058 
3059 	if (ret)
3060 		return ret;
3061 
3062 	dep->endpoint.caps.dir_in = direction;
3063 	dep->endpoint.caps.dir_out = !direction;
3064 
3065 	INIT_LIST_HEAD(&dep->pending_list);
3066 	INIT_LIST_HEAD(&dep->started_list);
3067 	INIT_LIST_HEAD(&dep->cancelled_list);
3068 
3069 	dwc3_debugfs_create_endpoint_dir(dep);
3070 
3071 	return 0;
3072 }
3073 
3074 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3075 {
3076 	u8				epnum;
3077 
3078 	INIT_LIST_HEAD(&dwc->gadget->ep_list);
3079 
3080 	for (epnum = 0; epnum < total; epnum++) {
3081 		int			ret;
3082 
3083 		ret = dwc3_gadget_init_endpoint(dwc, epnum);
3084 		if (ret)
3085 			return ret;
3086 	}
3087 
3088 	return 0;
3089 }
3090 
3091 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3092 {
3093 	struct dwc3_ep			*dep;
3094 	u8				epnum;
3095 
3096 	for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3097 		dep = dwc->eps[epnum];
3098 		if (!dep)
3099 			continue;
3100 		/*
3101 		 * Physical endpoints 0 and 1 are special; they form the
3102 		 * bi-directional USB endpoint 0.
3103 		 *
3104 		 * For those two physical endpoints, we don't allocate a TRB
3105 		 * pool nor do we add them the endpoints list. Due to that, we
3106 		 * shouldn't do these two operations otherwise we would end up
3107 		 * with all sorts of bugs when removing dwc3.ko.
3108 		 */
3109 		if (epnum != 0 && epnum != 1) {
3110 			dwc3_free_trb_pool(dep);
3111 			list_del(&dep->endpoint.ep_list);
3112 		}
3113 
3114 		debugfs_remove_recursive(debugfs_lookup(dep->name,
3115 				debugfs_lookup(dev_name(dep->dwc->dev),
3116 					       usb_debug_root)));
3117 		kfree(dep);
3118 	}
3119 }
3120 
3121 /* -------------------------------------------------------------------------- */
3122 
3123 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3124 		struct dwc3_request *req, struct dwc3_trb *trb,
3125 		const struct dwc3_event_depevt *event, int status, int chain)
3126 {
3127 	unsigned int		count;
3128 
3129 	dwc3_ep_inc_deq(dep);
3130 
3131 	trace_dwc3_complete_trb(dep, trb);
3132 	req->num_trbs--;
3133 
3134 	/*
3135 	 * If we're in the middle of series of chained TRBs and we
3136 	 * receive a short transfer along the way, DWC3 will skip
3137 	 * through all TRBs including the last TRB in the chain (the
3138 	 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3139 	 * bit and SW has to do it manually.
3140 	 *
3141 	 * We're going to do that here to avoid problems of HW trying
3142 	 * to use bogus TRBs for transfers.
3143 	 */
3144 	if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3145 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3146 
3147 	/*
3148 	 * For isochronous transfers, the first TRB in a service interval must
3149 	 * have the Isoc-First type. Track and report its interval frame number.
3150 	 */
3151 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3152 	    (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3153 		unsigned int frame_number;
3154 
3155 		frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3156 		frame_number &= ~(dep->interval - 1);
3157 		req->request.frame_number = frame_number;
3158 	}
3159 
3160 	/*
3161 	 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3162 	 * this TRB points to the bounce buffer address, it's a MPS alignment
3163 	 * TRB. Don't add it to req->remaining calculation.
3164 	 */
3165 	if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3166 	    trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3167 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3168 		return 1;
3169 	}
3170 
3171 	count = trb->size & DWC3_TRB_SIZE_MASK;
3172 	req->remaining += count;
3173 
3174 	if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3175 		return 1;
3176 
3177 	if (event->status & DEPEVT_STATUS_SHORT && !chain)
3178 		return 1;
3179 
3180 	if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3181 	    (trb->ctrl & DWC3_TRB_CTRL_LST))
3182 		return 1;
3183 
3184 	return 0;
3185 }
3186 
3187 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3188 		struct dwc3_request *req, const struct dwc3_event_depevt *event,
3189 		int status)
3190 {
3191 	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3192 	struct scatterlist *sg = req->sg;
3193 	struct scatterlist *s;
3194 	unsigned int num_queued = req->num_queued_sgs;
3195 	unsigned int i;
3196 	int ret = 0;
3197 
3198 	for_each_sg(sg, s, num_queued, i) {
3199 		trb = &dep->trb_pool[dep->trb_dequeue];
3200 
3201 		req->sg = sg_next(s);
3202 		req->num_queued_sgs--;
3203 
3204 		ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3205 				trb, event, status, true);
3206 		if (ret)
3207 			break;
3208 	}
3209 
3210 	return ret;
3211 }
3212 
3213 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3214 		struct dwc3_request *req, const struct dwc3_event_depevt *event,
3215 		int status)
3216 {
3217 	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3218 
3219 	return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3220 			event, status, false);
3221 }
3222 
3223 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3224 {
3225 	return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3226 }
3227 
3228 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3229 		const struct dwc3_event_depevt *event,
3230 		struct dwc3_request *req, int status)
3231 {
3232 	int ret;
3233 
3234 	if (req->request.num_mapped_sgs)
3235 		ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3236 				status);
3237 	else
3238 		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3239 				status);
3240 
3241 	req->request.actual = req->request.length - req->remaining;
3242 
3243 	if (!dwc3_gadget_ep_request_completed(req))
3244 		goto out;
3245 
3246 	if (req->needs_extra_trb) {
3247 		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3248 				status);
3249 		req->needs_extra_trb = false;
3250 	}
3251 
3252 	dwc3_gadget_giveback(dep, req, status);
3253 
3254 out:
3255 	return ret;
3256 }
3257 
3258 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3259 		const struct dwc3_event_depevt *event, int status)
3260 {
3261 	struct dwc3_request	*req;
3262 	struct dwc3_request	*tmp;
3263 
3264 	list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
3265 		int ret;
3266 
3267 		ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3268 				req, status);
3269 		if (ret)
3270 			break;
3271 	}
3272 }
3273 
3274 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3275 {
3276 	struct dwc3_request	*req;
3277 	struct dwc3		*dwc = dep->dwc;
3278 
3279 	if (!dep->endpoint.desc || !dwc->pullups_connected ||
3280 	    !dwc->connected)
3281 		return false;
3282 
3283 	if (!list_empty(&dep->pending_list))
3284 		return true;
3285 
3286 	/*
3287 	 * We only need to check the first entry of the started list. We can
3288 	 * assume the completed requests are removed from the started list.
3289 	 */
3290 	req = next_request(&dep->started_list);
3291 	if (!req)
3292 		return false;
3293 
3294 	return !dwc3_gadget_ep_request_completed(req);
3295 }
3296 
3297 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3298 		const struct dwc3_event_depevt *event)
3299 {
3300 	dep->frame_number = event->parameters;
3301 }
3302 
3303 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3304 		const struct dwc3_event_depevt *event, int status)
3305 {
3306 	struct dwc3		*dwc = dep->dwc;
3307 	bool			no_started_trb = true;
3308 
3309 	if (!dep->endpoint.desc)
3310 		return no_started_trb;
3311 
3312 	dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3313 
3314 	if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3315 		goto out;
3316 
3317 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3318 		list_empty(&dep->started_list) &&
3319 		(list_empty(&dep->pending_list) || status == -EXDEV))
3320 		dwc3_stop_active_transfer(dep, true, true);
3321 	else if (dwc3_gadget_ep_should_continue(dep))
3322 		if (__dwc3_gadget_kick_transfer(dep) == 0)
3323 			no_started_trb = false;
3324 
3325 out:
3326 	/*
3327 	 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3328 	 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3329 	 */
3330 	if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3331 		u32		reg;
3332 		int		i;
3333 
3334 		for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3335 			dep = dwc->eps[i];
3336 
3337 			if (!(dep->flags & DWC3_EP_ENABLED))
3338 				continue;
3339 
3340 			if (!list_empty(&dep->started_list))
3341 				return no_started_trb;
3342 		}
3343 
3344 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3345 		reg |= dwc->u1u2;
3346 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3347 
3348 		dwc->u1u2 = 0;
3349 	}
3350 
3351 	return no_started_trb;
3352 }
3353 
3354 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3355 		const struct dwc3_event_depevt *event)
3356 {
3357 	int status = 0;
3358 
3359 	if (!dep->endpoint.desc)
3360 		return;
3361 
3362 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3363 		dwc3_gadget_endpoint_frame_from_event(dep, event);
3364 
3365 	if (event->status & DEPEVT_STATUS_BUSERR)
3366 		status = -ECONNRESET;
3367 
3368 	if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3369 		status = -EXDEV;
3370 
3371 	dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3372 }
3373 
3374 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3375 		const struct dwc3_event_depevt *event)
3376 {
3377 	int status = 0;
3378 
3379 	dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3380 
3381 	if (event->status & DEPEVT_STATUS_BUSERR)
3382 		status = -ECONNRESET;
3383 
3384 	if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3385 		dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3386 }
3387 
3388 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3389 		const struct dwc3_event_depevt *event)
3390 {
3391 	dwc3_gadget_endpoint_frame_from_event(dep, event);
3392 
3393 	/*
3394 	 * The XferNotReady event is generated only once before the endpoint
3395 	 * starts. It will be generated again when END_TRANSFER command is
3396 	 * issued. For some controller versions, the XferNotReady event may be
3397 	 * generated while the END_TRANSFER command is still in process. Ignore
3398 	 * it and wait for the next XferNotReady event after the command is
3399 	 * completed.
3400 	 */
3401 	if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3402 		return;
3403 
3404 	(void) __dwc3_gadget_start_isoc(dep);
3405 }
3406 
3407 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3408 		const struct dwc3_event_depevt *event)
3409 {
3410 	u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3411 
3412 	if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3413 		return;
3414 
3415 	/*
3416 	 * The END_TRANSFER command will cause the controller to generate a
3417 	 * NoStream Event, and it's not due to the host DP NoStream rejection.
3418 	 * Ignore the next NoStream event.
3419 	 */
3420 	if (dep->stream_capable)
3421 		dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3422 
3423 	dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3424 	dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3425 	dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3426 
3427 	if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3428 		struct dwc3 *dwc = dep->dwc;
3429 
3430 		dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3431 		if (dwc3_send_clear_stall_ep_cmd(dep)) {
3432 			struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3433 
3434 			dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3435 			if (dwc->delayed_status)
3436 				__dwc3_gadget_ep0_set_halt(ep0, 1);
3437 			return;
3438 		}
3439 
3440 		dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3441 		if (dwc->delayed_status)
3442 			dwc3_ep0_send_delayed_status(dwc);
3443 	}
3444 
3445 	if ((dep->flags & DWC3_EP_DELAY_START) &&
3446 	    !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3447 		__dwc3_gadget_kick_transfer(dep);
3448 
3449 	dep->flags &= ~DWC3_EP_DELAY_START;
3450 }
3451 
3452 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3453 		const struct dwc3_event_depevt *event)
3454 {
3455 	struct dwc3 *dwc = dep->dwc;
3456 
3457 	if (event->status == DEPEVT_STREAMEVT_FOUND) {
3458 		dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3459 		goto out;
3460 	}
3461 
3462 	/* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3463 	switch (event->parameters) {
3464 	case DEPEVT_STREAM_PRIME:
3465 		/*
3466 		 * If the host can properly transition the endpoint state from
3467 		 * idle to prime after a NoStream rejection, there's no need to
3468 		 * force restarting the endpoint to reinitiate the stream. To
3469 		 * simplify the check, assume the host follows the USB spec if
3470 		 * it primed the endpoint more than once.
3471 		 */
3472 		if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3473 			if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3474 				dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3475 			else
3476 				dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3477 		}
3478 
3479 		break;
3480 	case DEPEVT_STREAM_NOSTREAM:
3481 		if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3482 		    !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3483 		    (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3484 		     !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3485 			break;
3486 
3487 		/*
3488 		 * If the host rejects a stream due to no active stream, by the
3489 		 * USB and xHCI spec, the endpoint will be put back to idle
3490 		 * state. When the host is ready (buffer added/updated), it will
3491 		 * prime the endpoint to inform the usb device controller. This
3492 		 * triggers the device controller to issue ERDY to restart the
3493 		 * stream. However, some hosts don't follow this and keep the
3494 		 * endpoint in the idle state. No prime will come despite host
3495 		 * streams are updated, and the device controller will not be
3496 		 * triggered to generate ERDY to move the next stream data. To
3497 		 * workaround this and maintain compatibility with various
3498 		 * hosts, force to reinitate the stream until the host is ready
3499 		 * instead of waiting for the host to prime the endpoint.
3500 		 */
3501 		if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3502 			unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3503 
3504 			dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3505 		} else {
3506 			dep->flags |= DWC3_EP_DELAY_START;
3507 			dwc3_stop_active_transfer(dep, true, true);
3508 			return;
3509 		}
3510 		break;
3511 	}
3512 
3513 out:
3514 	dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3515 }
3516 
3517 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3518 		const struct dwc3_event_depevt *event)
3519 {
3520 	struct dwc3_ep		*dep;
3521 	u8			epnum = event->endpoint_number;
3522 
3523 	dep = dwc->eps[epnum];
3524 
3525 	if (!(dep->flags & DWC3_EP_ENABLED)) {
3526 		if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3527 			return;
3528 
3529 		/* Handle only EPCMDCMPLT when EP disabled */
3530 		if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3531 			return;
3532 	}
3533 
3534 	if (epnum == 0 || epnum == 1) {
3535 		dwc3_ep0_interrupt(dwc, event);
3536 		return;
3537 	}
3538 
3539 	switch (event->endpoint_event) {
3540 	case DWC3_DEPEVT_XFERINPROGRESS:
3541 		dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3542 		break;
3543 	case DWC3_DEPEVT_XFERNOTREADY:
3544 		dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3545 		break;
3546 	case DWC3_DEPEVT_EPCMDCMPLT:
3547 		dwc3_gadget_endpoint_command_complete(dep, event);
3548 		break;
3549 	case DWC3_DEPEVT_XFERCOMPLETE:
3550 		dwc3_gadget_endpoint_transfer_complete(dep, event);
3551 		break;
3552 	case DWC3_DEPEVT_STREAMEVT:
3553 		dwc3_gadget_endpoint_stream_event(dep, event);
3554 		break;
3555 	case DWC3_DEPEVT_RXTXFIFOEVT:
3556 		break;
3557 	}
3558 }
3559 
3560 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3561 {
3562 	if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3563 		spin_unlock(&dwc->lock);
3564 		dwc->gadget_driver->disconnect(dwc->gadget);
3565 		spin_lock(&dwc->lock);
3566 	}
3567 }
3568 
3569 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3570 {
3571 	if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3572 		spin_unlock(&dwc->lock);
3573 		dwc->gadget_driver->suspend(dwc->gadget);
3574 		spin_lock(&dwc->lock);
3575 	}
3576 }
3577 
3578 static void dwc3_resume_gadget(struct dwc3 *dwc)
3579 {
3580 	if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3581 		spin_unlock(&dwc->lock);
3582 		dwc->gadget_driver->resume(dwc->gadget);
3583 		spin_lock(&dwc->lock);
3584 	}
3585 }
3586 
3587 static void dwc3_reset_gadget(struct dwc3 *dwc)
3588 {
3589 	if (!dwc->gadget_driver)
3590 		return;
3591 
3592 	if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3593 		spin_unlock(&dwc->lock);
3594 		usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3595 		spin_lock(&dwc->lock);
3596 	}
3597 }
3598 
3599 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3600 	bool interrupt)
3601 {
3602 	struct dwc3_gadget_ep_cmd_params params;
3603 	u32 cmd;
3604 	int ret;
3605 
3606 	if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3607 	    (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3608 		return;
3609 
3610 	/*
3611 	 * NOTICE: We are violating what the Databook says about the
3612 	 * EndTransfer command. Ideally we would _always_ wait for the
3613 	 * EndTransfer Command Completion IRQ, but that's causing too
3614 	 * much trouble synchronizing between us and gadget driver.
3615 	 *
3616 	 * We have discussed this with the IP Provider and it was
3617 	 * suggested to giveback all requests here.
3618 	 *
3619 	 * Note also that a similar handling was tested by Synopsys
3620 	 * (thanks a lot Paul) and nothing bad has come out of it.
3621 	 * In short, what we're doing is issuing EndTransfer with
3622 	 * CMDIOC bit set and delay kicking transfer until the
3623 	 * EndTransfer command had completed.
3624 	 *
3625 	 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3626 	 * supports a mode to work around the above limitation. The
3627 	 * software can poll the CMDACT bit in the DEPCMD register
3628 	 * after issuing a EndTransfer command. This mode is enabled
3629 	 * by writing GUCTL2[14]. This polling is already done in the
3630 	 * dwc3_send_gadget_ep_cmd() function so if the mode is
3631 	 * enabled, the EndTransfer command will have completed upon
3632 	 * returning from this function.
3633 	 *
3634 	 * This mode is NOT available on the DWC_usb31 IP.
3635 	 */
3636 
3637 	cmd = DWC3_DEPCMD_ENDTRANSFER;
3638 	cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3639 	cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3640 	cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3641 	memset(&params, 0, sizeof(params));
3642 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3643 	WARN_ON_ONCE(ret);
3644 	dep->resource_index = 0;
3645 
3646 	if (!interrupt)
3647 		dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3648 	else
3649 		dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3650 }
3651 
3652 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3653 {
3654 	u32 epnum;
3655 
3656 	for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3657 		struct dwc3_ep *dep;
3658 		int ret;
3659 
3660 		dep = dwc->eps[epnum];
3661 		if (!dep)
3662 			continue;
3663 
3664 		if (!(dep->flags & DWC3_EP_STALL))
3665 			continue;
3666 
3667 		dep->flags &= ~DWC3_EP_STALL;
3668 
3669 		ret = dwc3_send_clear_stall_ep_cmd(dep);
3670 		WARN_ON_ONCE(ret);
3671 	}
3672 }
3673 
3674 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3675 {
3676 	int			reg;
3677 
3678 	dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3679 
3680 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3681 	reg &= ~DWC3_DCTL_INITU1ENA;
3682 	reg &= ~DWC3_DCTL_INITU2ENA;
3683 	dwc3_gadget_dctl_write_safe(dwc, reg);
3684 
3685 	dwc3_disconnect_gadget(dwc);
3686 
3687 	dwc->gadget->speed = USB_SPEED_UNKNOWN;
3688 	dwc->setup_packet_pending = false;
3689 	usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3690 
3691 	dwc->connected = false;
3692 }
3693 
3694 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3695 {
3696 	u32			reg;
3697 
3698 	/*
3699 	 * Ideally, dwc3_reset_gadget() would trigger the function
3700 	 * drivers to stop any active transfers through ep disable.
3701 	 * However, for functions which defer ep disable, such as mass
3702 	 * storage, we will need to rely on the call to stop active
3703 	 * transfers here, and avoid allowing of request queuing.
3704 	 */
3705 	dwc->connected = false;
3706 
3707 	/*
3708 	 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3709 	 * would cause a missing Disconnect Event if there's a
3710 	 * pending Setup Packet in the FIFO.
3711 	 *
3712 	 * There's no suggested workaround on the official Bug
3713 	 * report, which states that "unless the driver/application
3714 	 * is doing any special handling of a disconnect event,
3715 	 * there is no functional issue".
3716 	 *
3717 	 * Unfortunately, it turns out that we _do_ some special
3718 	 * handling of a disconnect event, namely complete all
3719 	 * pending transfers, notify gadget driver of the
3720 	 * disconnection, and so on.
3721 	 *
3722 	 * Our suggested workaround is to follow the Disconnect
3723 	 * Event steps here, instead, based on a setup_packet_pending
3724 	 * flag. Such flag gets set whenever we have a SETUP_PENDING
3725 	 * status for EP0 TRBs and gets cleared on XferComplete for the
3726 	 * same endpoint.
3727 	 *
3728 	 * Refers to:
3729 	 *
3730 	 * STAR#9000466709: RTL: Device : Disconnect event not
3731 	 * generated if setup packet pending in FIFO
3732 	 */
3733 	if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3734 		if (dwc->setup_packet_pending)
3735 			dwc3_gadget_disconnect_interrupt(dwc);
3736 	}
3737 
3738 	dwc3_reset_gadget(dwc);
3739 	/*
3740 	 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3741 	 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3742 	 * needs to ensure that it sends "a DEPENDXFER command for any active
3743 	 * transfers."
3744 	 */
3745 	dwc3_stop_active_transfers(dwc);
3746 	dwc->connected = true;
3747 
3748 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3749 	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3750 	dwc3_gadget_dctl_write_safe(dwc, reg);
3751 	dwc->test_mode = false;
3752 	dwc3_clear_stall_all_ep(dwc);
3753 
3754 	/* Reset device address to zero */
3755 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3756 	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3757 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3758 }
3759 
3760 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3761 {
3762 	struct dwc3_ep		*dep;
3763 	int			ret;
3764 	u32			reg;
3765 	u8			lanes = 1;
3766 	u8			speed;
3767 
3768 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3769 	speed = reg & DWC3_DSTS_CONNECTSPD;
3770 	dwc->speed = speed;
3771 
3772 	if (DWC3_IP_IS(DWC32))
3773 		lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3774 
3775 	dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3776 
3777 	/*
3778 	 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3779 	 * each time on Connect Done.
3780 	 *
3781 	 * Currently we always use the reset value. If any platform
3782 	 * wants to set this to a different value, we need to add a
3783 	 * setting and update GCTL.RAMCLKSEL here.
3784 	 */
3785 
3786 	switch (speed) {
3787 	case DWC3_DSTS_SUPERSPEED_PLUS:
3788 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3789 		dwc->gadget->ep0->maxpacket = 512;
3790 		dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3791 
3792 		if (lanes > 1)
3793 			dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3794 		else
3795 			dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3796 		break;
3797 	case DWC3_DSTS_SUPERSPEED:
3798 		/*
3799 		 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3800 		 * would cause a missing USB3 Reset event.
3801 		 *
3802 		 * In such situations, we should force a USB3 Reset
3803 		 * event by calling our dwc3_gadget_reset_interrupt()
3804 		 * routine.
3805 		 *
3806 		 * Refers to:
3807 		 *
3808 		 * STAR#9000483510: RTL: SS : USB3 reset event may
3809 		 * not be generated always when the link enters poll
3810 		 */
3811 		if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3812 			dwc3_gadget_reset_interrupt(dwc);
3813 
3814 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3815 		dwc->gadget->ep0->maxpacket = 512;
3816 		dwc->gadget->speed = USB_SPEED_SUPER;
3817 
3818 		if (lanes > 1) {
3819 			dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3820 			dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3821 		}
3822 		break;
3823 	case DWC3_DSTS_HIGHSPEED:
3824 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3825 		dwc->gadget->ep0->maxpacket = 64;
3826 		dwc->gadget->speed = USB_SPEED_HIGH;
3827 		break;
3828 	case DWC3_DSTS_FULLSPEED:
3829 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3830 		dwc->gadget->ep0->maxpacket = 64;
3831 		dwc->gadget->speed = USB_SPEED_FULL;
3832 		break;
3833 	}
3834 
3835 	dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3836 
3837 	/* Enable USB2 LPM Capability */
3838 
3839 	if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3840 	    !dwc->usb2_gadget_lpm_disable &&
3841 	    (speed != DWC3_DSTS_SUPERSPEED) &&
3842 	    (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3843 		reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3844 		reg |= DWC3_DCFG_LPM_CAP;
3845 		dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3846 
3847 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3848 		reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3849 
3850 		reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3851 					    (dwc->is_utmi_l1_suspend << 4));
3852 
3853 		/*
3854 		 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3855 		 * DCFG.LPMCap is set, core responses with an ACK and the
3856 		 * BESL value in the LPM token is less than or equal to LPM
3857 		 * NYET threshold.
3858 		 */
3859 		WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3860 				"LPM Erratum not available on dwc3 revisions < 2.40a\n");
3861 
3862 		if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3863 			reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3864 
3865 		dwc3_gadget_dctl_write_safe(dwc, reg);
3866 	} else {
3867 		if (dwc->usb2_gadget_lpm_disable) {
3868 			reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3869 			reg &= ~DWC3_DCFG_LPM_CAP;
3870 			dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3871 		}
3872 
3873 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3874 		reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3875 		dwc3_gadget_dctl_write_safe(dwc, reg);
3876 	}
3877 
3878 	dep = dwc->eps[0];
3879 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3880 	if (ret) {
3881 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3882 		return;
3883 	}
3884 
3885 	dep = dwc->eps[1];
3886 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3887 	if (ret) {
3888 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3889 		return;
3890 	}
3891 
3892 	/*
3893 	 * Configure PHY via GUSB3PIPECTLn if required.
3894 	 *
3895 	 * Update GTXFIFOSIZn
3896 	 *
3897 	 * In both cases reset values should be sufficient.
3898 	 */
3899 }
3900 
3901 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3902 {
3903 	/*
3904 	 * TODO take core out of low power mode when that's
3905 	 * implemented.
3906 	 */
3907 
3908 	if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3909 		spin_unlock(&dwc->lock);
3910 		dwc->gadget_driver->resume(dwc->gadget);
3911 		spin_lock(&dwc->lock);
3912 	}
3913 }
3914 
3915 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3916 		unsigned int evtinfo)
3917 {
3918 	enum dwc3_link_state	next = evtinfo & DWC3_LINK_STATE_MASK;
3919 	unsigned int		pwropt;
3920 
3921 	/*
3922 	 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3923 	 * Hibernation mode enabled which would show up when device detects
3924 	 * host-initiated U3 exit.
3925 	 *
3926 	 * In that case, device will generate a Link State Change Interrupt
3927 	 * from U3 to RESUME which is only necessary if Hibernation is
3928 	 * configured in.
3929 	 *
3930 	 * There are no functional changes due to such spurious event and we
3931 	 * just need to ignore it.
3932 	 *
3933 	 * Refers to:
3934 	 *
3935 	 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3936 	 * operational mode
3937 	 */
3938 	pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3939 	if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3940 			(pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3941 		if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3942 				(next == DWC3_LINK_STATE_RESUME)) {
3943 			return;
3944 		}
3945 	}
3946 
3947 	/*
3948 	 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3949 	 * on the link partner, the USB session might do multiple entry/exit
3950 	 * of low power states before a transfer takes place.
3951 	 *
3952 	 * Due to this problem, we might experience lower throughput. The
3953 	 * suggested workaround is to disable DCTL[12:9] bits if we're
3954 	 * transitioning from U1/U2 to U0 and enable those bits again
3955 	 * after a transfer completes and there are no pending transfers
3956 	 * on any of the enabled endpoints.
3957 	 *
3958 	 * This is the first half of that workaround.
3959 	 *
3960 	 * Refers to:
3961 	 *
3962 	 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3963 	 * core send LGO_Ux entering U0
3964 	 */
3965 	if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3966 		if (next == DWC3_LINK_STATE_U0) {
3967 			u32	u1u2;
3968 			u32	reg;
3969 
3970 			switch (dwc->link_state) {
3971 			case DWC3_LINK_STATE_U1:
3972 			case DWC3_LINK_STATE_U2:
3973 				reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3974 				u1u2 = reg & (DWC3_DCTL_INITU2ENA
3975 						| DWC3_DCTL_ACCEPTU2ENA
3976 						| DWC3_DCTL_INITU1ENA
3977 						| DWC3_DCTL_ACCEPTU1ENA);
3978 
3979 				if (!dwc->u1u2)
3980 					dwc->u1u2 = reg & u1u2;
3981 
3982 				reg &= ~u1u2;
3983 
3984 				dwc3_gadget_dctl_write_safe(dwc, reg);
3985 				break;
3986 			default:
3987 				/* do nothing */
3988 				break;
3989 			}
3990 		}
3991 	}
3992 
3993 	switch (next) {
3994 	case DWC3_LINK_STATE_U1:
3995 		if (dwc->speed == USB_SPEED_SUPER)
3996 			dwc3_suspend_gadget(dwc);
3997 		break;
3998 	case DWC3_LINK_STATE_U2:
3999 	case DWC3_LINK_STATE_U3:
4000 		dwc3_suspend_gadget(dwc);
4001 		break;
4002 	case DWC3_LINK_STATE_RESUME:
4003 		dwc3_resume_gadget(dwc);
4004 		break;
4005 	default:
4006 		/* do nothing */
4007 		break;
4008 	}
4009 
4010 	dwc->link_state = next;
4011 }
4012 
4013 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4014 					  unsigned int evtinfo)
4015 {
4016 	enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4017 
4018 	if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
4019 		dwc3_suspend_gadget(dwc);
4020 
4021 	dwc->link_state = next;
4022 }
4023 
4024 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
4025 		unsigned int evtinfo)
4026 {
4027 	unsigned int is_ss = evtinfo & BIT(4);
4028 
4029 	/*
4030 	 * WORKAROUND: DWC3 revison 2.20a with hibernation support
4031 	 * have a known issue which can cause USB CV TD.9.23 to fail
4032 	 * randomly.
4033 	 *
4034 	 * Because of this issue, core could generate bogus hibernation
4035 	 * events which SW needs to ignore.
4036 	 *
4037 	 * Refers to:
4038 	 *
4039 	 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
4040 	 * Device Fallback from SuperSpeed
4041 	 */
4042 	if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
4043 		return;
4044 
4045 	/* enter hibernation here */
4046 }
4047 
4048 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4049 		const struct dwc3_event_devt *event)
4050 {
4051 	switch (event->type) {
4052 	case DWC3_DEVICE_EVENT_DISCONNECT:
4053 		dwc3_gadget_disconnect_interrupt(dwc);
4054 		break;
4055 	case DWC3_DEVICE_EVENT_RESET:
4056 		dwc3_gadget_reset_interrupt(dwc);
4057 		break;
4058 	case DWC3_DEVICE_EVENT_CONNECT_DONE:
4059 		dwc3_gadget_conndone_interrupt(dwc);
4060 		break;
4061 	case DWC3_DEVICE_EVENT_WAKEUP:
4062 		dwc3_gadget_wakeup_interrupt(dwc);
4063 		break;
4064 	case DWC3_DEVICE_EVENT_HIBER_REQ:
4065 		if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
4066 					"unexpected hibernation event\n"))
4067 			break;
4068 
4069 		dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
4070 		break;
4071 	case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4072 		dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4073 		break;
4074 	case DWC3_DEVICE_EVENT_SUSPEND:
4075 		/* It changed to be suspend event for version 2.30a and above */
4076 		if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4077 			/*
4078 			 * Ignore suspend event until the gadget enters into
4079 			 * USB_STATE_CONFIGURED state.
4080 			 */
4081 			if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4082 				dwc3_gadget_suspend_interrupt(dwc,
4083 						event->event_info);
4084 		}
4085 		break;
4086 	case DWC3_DEVICE_EVENT_SOF:
4087 	case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4088 	case DWC3_DEVICE_EVENT_CMD_CMPL:
4089 	case DWC3_DEVICE_EVENT_OVERFLOW:
4090 		break;
4091 	default:
4092 		dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4093 	}
4094 }
4095 
4096 static void dwc3_process_event_entry(struct dwc3 *dwc,
4097 		const union dwc3_event *event)
4098 {
4099 	trace_dwc3_event(event->raw, dwc);
4100 
4101 	if (!event->type.is_devspec)
4102 		dwc3_endpoint_interrupt(dwc, &event->depevt);
4103 	else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4104 		dwc3_gadget_interrupt(dwc, &event->devt);
4105 	else
4106 		dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4107 }
4108 
4109 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4110 {
4111 	struct dwc3 *dwc = evt->dwc;
4112 	irqreturn_t ret = IRQ_NONE;
4113 	int left;
4114 
4115 	left = evt->count;
4116 
4117 	if (!(evt->flags & DWC3_EVENT_PENDING))
4118 		return IRQ_NONE;
4119 
4120 	while (left > 0) {
4121 		union dwc3_event event;
4122 
4123 		event.raw = *(u32 *) (evt->cache + evt->lpos);
4124 
4125 		dwc3_process_event_entry(dwc, &event);
4126 
4127 		/*
4128 		 * FIXME we wrap around correctly to the next entry as
4129 		 * almost all entries are 4 bytes in size. There is one
4130 		 * entry which has 12 bytes which is a regular entry
4131 		 * followed by 8 bytes data. ATM I don't know how
4132 		 * things are organized if we get next to the a
4133 		 * boundary so I worry about that once we try to handle
4134 		 * that.
4135 		 */
4136 		evt->lpos = (evt->lpos + 4) % evt->length;
4137 		left -= 4;
4138 	}
4139 
4140 	evt->count = 0;
4141 	evt->flags &= ~DWC3_EVENT_PENDING;
4142 	ret = IRQ_HANDLED;
4143 
4144 	/* Unmask interrupt */
4145 	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4146 		    DWC3_GEVNTSIZ_SIZE(evt->length));
4147 
4148 	if (dwc->imod_interval) {
4149 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4150 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4151 	}
4152 
4153 	return ret;
4154 }
4155 
4156 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4157 {
4158 	struct dwc3_event_buffer *evt = _evt;
4159 	struct dwc3 *dwc = evt->dwc;
4160 	unsigned long flags;
4161 	irqreturn_t ret = IRQ_NONE;
4162 
4163 	spin_lock_irqsave(&dwc->lock, flags);
4164 	ret = dwc3_process_event_buf(evt);
4165 	spin_unlock_irqrestore(&dwc->lock, flags);
4166 
4167 	return ret;
4168 }
4169 
4170 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4171 {
4172 	struct dwc3 *dwc = evt->dwc;
4173 	u32 amount;
4174 	u32 count;
4175 
4176 	if (pm_runtime_suspended(dwc->dev)) {
4177 		pm_runtime_get(dwc->dev);
4178 		disable_irq_nosync(dwc->irq_gadget);
4179 		dwc->pending_events = true;
4180 		return IRQ_HANDLED;
4181 	}
4182 
4183 	/*
4184 	 * With PCIe legacy interrupt, test shows that top-half irq handler can
4185 	 * be called again after HW interrupt deassertion. Check if bottom-half
4186 	 * irq event handler completes before caching new event to prevent
4187 	 * losing events.
4188 	 */
4189 	if (evt->flags & DWC3_EVENT_PENDING)
4190 		return IRQ_HANDLED;
4191 
4192 	count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4193 	count &= DWC3_GEVNTCOUNT_MASK;
4194 	if (!count)
4195 		return IRQ_NONE;
4196 
4197 	evt->count = count;
4198 	evt->flags |= DWC3_EVENT_PENDING;
4199 
4200 	/* Mask interrupt */
4201 	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4202 		    DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4203 
4204 	amount = min(count, evt->length - evt->lpos);
4205 	memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4206 
4207 	if (amount < count)
4208 		memcpy(evt->cache, evt->buf, count - amount);
4209 
4210 	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4211 
4212 	return IRQ_WAKE_THREAD;
4213 }
4214 
4215 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4216 {
4217 	struct dwc3_event_buffer	*evt = _evt;
4218 
4219 	return dwc3_check_event_buf(evt);
4220 }
4221 
4222 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4223 {
4224 	struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4225 	int irq;
4226 
4227 	irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4228 	if (irq > 0)
4229 		goto out;
4230 
4231 	if (irq == -EPROBE_DEFER)
4232 		goto out;
4233 
4234 	irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4235 	if (irq > 0)
4236 		goto out;
4237 
4238 	if (irq == -EPROBE_DEFER)
4239 		goto out;
4240 
4241 	irq = platform_get_irq(dwc3_pdev, 0);
4242 	if (irq > 0)
4243 		goto out;
4244 
4245 	if (!irq)
4246 		irq = -EINVAL;
4247 
4248 out:
4249 	return irq;
4250 }
4251 
4252 static void dwc_gadget_release(struct device *dev)
4253 {
4254 	struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4255 
4256 	kfree(gadget);
4257 }
4258 
4259 /**
4260  * dwc3_gadget_init - initializes gadget related registers
4261  * @dwc: pointer to our controller context structure
4262  *
4263  * Returns 0 on success otherwise negative errno.
4264  */
4265 int dwc3_gadget_init(struct dwc3 *dwc)
4266 {
4267 	int ret;
4268 	int irq;
4269 	struct device *dev;
4270 
4271 	irq = dwc3_gadget_get_irq(dwc);
4272 	if (irq < 0) {
4273 		ret = irq;
4274 		goto err0;
4275 	}
4276 
4277 	dwc->irq_gadget = irq;
4278 
4279 	dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4280 					  sizeof(*dwc->ep0_trb) * 2,
4281 					  &dwc->ep0_trb_addr, GFP_KERNEL);
4282 	if (!dwc->ep0_trb) {
4283 		dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4284 		ret = -ENOMEM;
4285 		goto err0;
4286 	}
4287 
4288 	dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4289 	if (!dwc->setup_buf) {
4290 		ret = -ENOMEM;
4291 		goto err1;
4292 	}
4293 
4294 	dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4295 			&dwc->bounce_addr, GFP_KERNEL);
4296 	if (!dwc->bounce) {
4297 		ret = -ENOMEM;
4298 		goto err2;
4299 	}
4300 
4301 	init_completion(&dwc->ep0_in_setup);
4302 	dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4303 	if (!dwc->gadget) {
4304 		ret = -ENOMEM;
4305 		goto err3;
4306 	}
4307 
4308 
4309 	usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4310 	dev				= &dwc->gadget->dev;
4311 	dev->platform_data		= dwc;
4312 	dwc->gadget->ops		= &dwc3_gadget_ops;
4313 	dwc->gadget->speed		= USB_SPEED_UNKNOWN;
4314 	dwc->gadget->ssp_rate		= USB_SSP_GEN_UNKNOWN;
4315 	dwc->gadget->sg_supported	= true;
4316 	dwc->gadget->name		= "dwc3-gadget";
4317 	dwc->gadget->lpm_capable	= !dwc->usb2_gadget_lpm_disable;
4318 
4319 	/*
4320 	 * FIXME We might be setting max_speed to <SUPER, however versions
4321 	 * <2.20a of dwc3 have an issue with metastability (documented
4322 	 * elsewhere in this driver) which tells us we can't set max speed to
4323 	 * anything lower than SUPER.
4324 	 *
4325 	 * Because gadget.max_speed is only used by composite.c and function
4326 	 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4327 	 * to happen so we avoid sending SuperSpeed Capability descriptor
4328 	 * together with our BOS descriptor as that could confuse host into
4329 	 * thinking we can handle super speed.
4330 	 *
4331 	 * Note that, in fact, we won't even support GetBOS requests when speed
4332 	 * is less than super speed because we don't have means, yet, to tell
4333 	 * composite.c that we are USB 2.0 + LPM ECN.
4334 	 */
4335 	if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4336 	    !dwc->dis_metastability_quirk)
4337 		dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4338 				dwc->revision);
4339 
4340 	dwc->gadget->max_speed		= dwc->maximum_speed;
4341 	dwc->gadget->max_ssp_rate	= dwc->max_ssp_rate;
4342 
4343 	/*
4344 	 * REVISIT: Here we should clear all pending IRQs to be
4345 	 * sure we're starting from a well known location.
4346 	 */
4347 
4348 	ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4349 	if (ret)
4350 		goto err4;
4351 
4352 	ret = usb_add_gadget(dwc->gadget);
4353 	if (ret) {
4354 		dev_err(dwc->dev, "failed to add gadget\n");
4355 		goto err5;
4356 	}
4357 
4358 	if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4359 		dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4360 	else
4361 		dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4362 
4363 	return 0;
4364 
4365 err5:
4366 	dwc3_gadget_free_endpoints(dwc);
4367 err4:
4368 	usb_put_gadget(dwc->gadget);
4369 	dwc->gadget = NULL;
4370 err3:
4371 	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4372 			dwc->bounce_addr);
4373 
4374 err2:
4375 	kfree(dwc->setup_buf);
4376 
4377 err1:
4378 	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4379 			dwc->ep0_trb, dwc->ep0_trb_addr);
4380 
4381 err0:
4382 	return ret;
4383 }
4384 
4385 /* -------------------------------------------------------------------------- */
4386 
4387 void dwc3_gadget_exit(struct dwc3 *dwc)
4388 {
4389 	if (!dwc->gadget)
4390 		return;
4391 
4392 	usb_del_gadget(dwc->gadget);
4393 	dwc3_gadget_free_endpoints(dwc);
4394 	usb_put_gadget(dwc->gadget);
4395 	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4396 			  dwc->bounce_addr);
4397 	kfree(dwc->setup_buf);
4398 	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4399 			  dwc->ep0_trb, dwc->ep0_trb_addr);
4400 }
4401 
4402 int dwc3_gadget_suspend(struct dwc3 *dwc)
4403 {
4404 	if (!dwc->gadget_driver)
4405 		return 0;
4406 
4407 	dwc3_gadget_run_stop(dwc, false, false);
4408 	dwc3_disconnect_gadget(dwc);
4409 	__dwc3_gadget_stop(dwc);
4410 
4411 	return 0;
4412 }
4413 
4414 int dwc3_gadget_resume(struct dwc3 *dwc)
4415 {
4416 	int			ret;
4417 
4418 	if (!dwc->gadget_driver || !dwc->softconnect)
4419 		return 0;
4420 
4421 	ret = __dwc3_gadget_start(dwc);
4422 	if (ret < 0)
4423 		goto err0;
4424 
4425 	ret = dwc3_gadget_run_stop(dwc, true, false);
4426 	if (ret < 0)
4427 		goto err1;
4428 
4429 	return 0;
4430 
4431 err1:
4432 	__dwc3_gadget_stop(dwc);
4433 
4434 err0:
4435 	return ret;
4436 }
4437 
4438 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4439 {
4440 	if (dwc->pending_events) {
4441 		dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4442 		dwc->pending_events = false;
4443 		enable_irq(dwc->irq_gadget);
4444 	}
4445 }
4446