1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/list.h> 27 #include <linux/dma-mapping.h> 28 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/composite.h> 32 33 #include "core.h" 34 #include "debug.h" 35 #include "gadget.h" 36 #include "io.h" 37 38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 40 struct dwc3_ep *dep, struct dwc3_request *req); 41 42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 43 { 44 switch (state) { 45 case EP0_UNCONNECTED: 46 return "Unconnected"; 47 case EP0_SETUP_PHASE: 48 return "Setup Phase"; 49 case EP0_DATA_PHASE: 50 return "Data Phase"; 51 case EP0_STATUS_PHASE: 52 return "Status Phase"; 53 default: 54 return "UNKNOWN"; 55 } 56 } 57 58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 59 u32 len, u32 type, bool chain) 60 { 61 struct dwc3_gadget_ep_cmd_params params; 62 struct dwc3_trb *trb; 63 struct dwc3_ep *dep; 64 65 int ret; 66 67 dep = dwc->eps[epnum]; 68 if (dep->flags & DWC3_EP_BUSY) { 69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name); 70 return 0; 71 } 72 73 trb = &dwc->ep0_trb[dep->free_slot]; 74 75 if (chain) 76 dep->free_slot++; 77 78 trb->bpl = lower_32_bits(buf_dma); 79 trb->bph = upper_32_bits(buf_dma); 80 trb->size = len; 81 trb->ctrl = type; 82 83 trb->ctrl |= (DWC3_TRB_CTRL_HWO 84 | DWC3_TRB_CTRL_ISP_IMI); 85 86 if (chain) 87 trb->ctrl |= DWC3_TRB_CTRL_CHN; 88 else 89 trb->ctrl |= (DWC3_TRB_CTRL_IOC 90 | DWC3_TRB_CTRL_LST); 91 92 if (chain) 93 return 0; 94 95 memset(¶ms, 0, sizeof(params)); 96 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 97 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 98 99 trace_dwc3_prepare_trb(dep, trb); 100 101 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 102 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 103 if (ret < 0) { 104 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed", 105 dep->name); 106 return ret; 107 } 108 109 dep->flags |= DWC3_EP_BUSY; 110 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 111 dep->number); 112 113 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 114 115 return 0; 116 } 117 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 119 struct dwc3_request *req) 120 { 121 struct dwc3 *dwc = dep->dwc; 122 123 req->request.actual = 0; 124 req->request.status = -EINPROGRESS; 125 req->epnum = dep->number; 126 127 list_add_tail(&req->list, &dep->request_list); 128 129 /* 130 * Gadget driver might not be quick enough to queue a request 131 * before we get a Transfer Not Ready event on this endpoint. 132 * 133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 134 * flag is set, it's telling us that as soon as Gadget queues the 135 * required request, we should kick the transfer here because the 136 * IRQ we were waiting for is long gone. 137 */ 138 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 139 unsigned direction; 140 141 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 142 143 if (dwc->ep0state != EP0_DATA_PHASE) { 144 dev_WARN(dwc->dev, "Unexpected pending request\n"); 145 return 0; 146 } 147 148 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 149 150 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 151 DWC3_EP0_DIR_IN); 152 153 return 0; 154 } 155 156 /* 157 * In case gadget driver asked us to delay the STATUS phase, 158 * handle it here. 159 */ 160 if (dwc->delayed_status) { 161 unsigned direction; 162 163 direction = !dwc->ep0_expect_in; 164 dwc->delayed_status = false; 165 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 166 167 if (dwc->ep0state == EP0_STATUS_PHASE) 168 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 169 else 170 dwc3_trace(trace_dwc3_ep0, 171 "too early for delayed status"); 172 173 return 0; 174 } 175 176 /* 177 * Unfortunately we have uncovered a limitation wrt the Data Phase. 178 * 179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 180 * come before issueing Start Transfer command, but if we do, we will 181 * miss situations where the host starts another SETUP phase instead of 182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 183 * Layer Compliance Suite. 184 * 185 * The problem surfaces due to the fact that in case of back-to-back 186 * SETUP packets there will be no XferNotReady(DATA) generated and we 187 * will be stuck waiting for XferNotReady(DATA) forever. 188 * 189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 190 * it tells us to start Data Phase right away. It also mentions that if 191 * we receive a SETUP phase instead of the DATA phase, core will issue 192 * XferComplete for the DATA phase, before actually initiating it in 193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 194 * can only be used to print some debugging logs, as the core expects 195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 196 * just so it completes right away, without transferring anything and, 197 * only then, we can go back to the SETUP phase. 198 * 199 * Because of this scenario, SNPS decided to change the programming 200 * model of control transfers and support on-demand transfers only for 201 * the STATUS phase. To fix the issue we have now, we will always wait 202 * for gadget driver to queue the DATA phase's struct usb_request, then 203 * start it right away. 204 * 205 * If we're actually in a 2-stage transfer, we will wait for 206 * XferNotReady(STATUS). 207 */ 208 if (dwc->three_stage_setup) { 209 unsigned direction; 210 211 direction = dwc->ep0_expect_in; 212 dwc->ep0state = EP0_DATA_PHASE; 213 214 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 215 216 dep->flags &= ~DWC3_EP0_DIR_IN; 217 } 218 219 return 0; 220 } 221 222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 223 gfp_t gfp_flags) 224 { 225 struct dwc3_request *req = to_dwc3_request(request); 226 struct dwc3_ep *dep = to_dwc3_ep(ep); 227 struct dwc3 *dwc = dep->dwc; 228 229 unsigned long flags; 230 231 int ret; 232 233 spin_lock_irqsave(&dwc->lock, flags); 234 if (!dep->endpoint.desc) { 235 dwc3_trace(trace_dwc3_ep0, 236 "trying to queue request %p to disabled %s", 237 request, dep->name); 238 ret = -ESHUTDOWN; 239 goto out; 240 } 241 242 /* we share one TRB for ep0/1 */ 243 if (!list_empty(&dep->request_list)) { 244 ret = -EBUSY; 245 goto out; 246 } 247 248 dwc3_trace(trace_dwc3_ep0, 249 "queueing request %p to %s length %d state '%s'", 250 request, dep->name, request->length, 251 dwc3_ep0_state_string(dwc->ep0state)); 252 253 ret = __dwc3_gadget_ep0_queue(dep, req); 254 255 out: 256 spin_unlock_irqrestore(&dwc->lock, flags); 257 258 return ret; 259 } 260 261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 262 { 263 struct dwc3_ep *dep; 264 265 /* reinitialize physical ep1 */ 266 dep = dwc->eps[1]; 267 dep->flags = DWC3_EP_ENABLED; 268 269 /* stall is always issued on EP0 */ 270 dep = dwc->eps[0]; 271 __dwc3_gadget_ep_set_halt(dep, 1, false); 272 dep->flags = DWC3_EP_ENABLED; 273 dwc->delayed_status = false; 274 275 if (!list_empty(&dep->request_list)) { 276 struct dwc3_request *req; 277 278 req = next_request(&dep->request_list); 279 dwc3_gadget_giveback(dep, req, -ECONNRESET); 280 } 281 282 dwc->ep0state = EP0_SETUP_PHASE; 283 dwc3_ep0_out_start(dwc); 284 } 285 286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 287 { 288 struct dwc3_ep *dep = to_dwc3_ep(ep); 289 struct dwc3 *dwc = dep->dwc; 290 291 dwc3_ep0_stall_and_restart(dwc); 292 293 return 0; 294 } 295 296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 297 { 298 struct dwc3_ep *dep = to_dwc3_ep(ep); 299 struct dwc3 *dwc = dep->dwc; 300 unsigned long flags; 301 int ret; 302 303 spin_lock_irqsave(&dwc->lock, flags); 304 ret = __dwc3_gadget_ep0_set_halt(ep, value); 305 spin_unlock_irqrestore(&dwc->lock, flags); 306 307 return ret; 308 } 309 310 void dwc3_ep0_out_start(struct dwc3 *dwc) 311 { 312 int ret; 313 314 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 315 DWC3_TRBCTL_CONTROL_SETUP, false); 316 WARN_ON(ret < 0); 317 } 318 319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 320 { 321 struct dwc3_ep *dep; 322 u32 windex = le16_to_cpu(wIndex_le); 323 u32 epnum; 324 325 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 326 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 327 epnum |= 1; 328 329 dep = dwc->eps[epnum]; 330 if (dep->flags & DWC3_EP_ENABLED) 331 return dep; 332 333 return NULL; 334 } 335 336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 337 { 338 } 339 /* 340 * ch 9.4.5 341 */ 342 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 343 struct usb_ctrlrequest *ctrl) 344 { 345 struct dwc3_ep *dep; 346 u32 recip; 347 u32 reg; 348 u16 usb_status = 0; 349 __le16 *response_pkt; 350 351 recip = ctrl->bRequestType & USB_RECIP_MASK; 352 switch (recip) { 353 case USB_RECIP_DEVICE: 354 /* 355 * LTM will be set once we know how to set this in HW. 356 */ 357 usb_status |= dwc->gadget.is_selfpowered; 358 359 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 360 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 361 if (reg & DWC3_DCTL_INITU1ENA) 362 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 363 if (reg & DWC3_DCTL_INITU2ENA) 364 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 365 } 366 367 break; 368 369 case USB_RECIP_INTERFACE: 370 /* 371 * Function Remote Wake Capable D0 372 * Function Remote Wakeup D1 373 */ 374 break; 375 376 case USB_RECIP_ENDPOINT: 377 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 378 if (!dep) 379 return -EINVAL; 380 381 if (dep->flags & DWC3_EP_STALL) 382 usb_status = 1 << USB_ENDPOINT_HALT; 383 break; 384 default: 385 return -EINVAL; 386 } 387 388 response_pkt = (__le16 *) dwc->setup_buf; 389 *response_pkt = cpu_to_le16(usb_status); 390 391 dep = dwc->eps[0]; 392 dwc->ep0_usb_req.dep = dep; 393 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 394 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 395 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 396 397 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 398 } 399 400 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 401 struct usb_ctrlrequest *ctrl, int set) 402 { 403 struct dwc3_ep *dep; 404 u32 recip; 405 u32 wValue; 406 u32 wIndex; 407 u32 reg; 408 int ret; 409 enum usb_device_state state; 410 411 wValue = le16_to_cpu(ctrl->wValue); 412 wIndex = le16_to_cpu(ctrl->wIndex); 413 recip = ctrl->bRequestType & USB_RECIP_MASK; 414 state = dwc->gadget.state; 415 416 switch (recip) { 417 case USB_RECIP_DEVICE: 418 419 switch (wValue) { 420 case USB_DEVICE_REMOTE_WAKEUP: 421 break; 422 /* 423 * 9.4.1 says only only for SS, in AddressState only for 424 * default control pipe 425 */ 426 case USB_DEVICE_U1_ENABLE: 427 if (state != USB_STATE_CONFIGURED) 428 return -EINVAL; 429 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 430 return -EINVAL; 431 432 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 433 if (set) 434 reg |= DWC3_DCTL_INITU1ENA; 435 else 436 reg &= ~DWC3_DCTL_INITU1ENA; 437 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 438 break; 439 440 case USB_DEVICE_U2_ENABLE: 441 if (state != USB_STATE_CONFIGURED) 442 return -EINVAL; 443 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 444 return -EINVAL; 445 446 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 447 if (set) 448 reg |= DWC3_DCTL_INITU2ENA; 449 else 450 reg &= ~DWC3_DCTL_INITU2ENA; 451 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 452 break; 453 454 case USB_DEVICE_LTM_ENABLE: 455 return -EINVAL; 456 457 case USB_DEVICE_TEST_MODE: 458 if ((wIndex & 0xff) != 0) 459 return -EINVAL; 460 if (!set) 461 return -EINVAL; 462 463 dwc->test_mode_nr = wIndex >> 8; 464 dwc->test_mode = true; 465 break; 466 default: 467 return -EINVAL; 468 } 469 break; 470 471 case USB_RECIP_INTERFACE: 472 switch (wValue) { 473 case USB_INTRF_FUNC_SUSPEND: 474 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 475 /* XXX enable Low power suspend */ 476 ; 477 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 478 /* XXX enable remote wakeup */ 479 ; 480 break; 481 default: 482 return -EINVAL; 483 } 484 break; 485 486 case USB_RECIP_ENDPOINT: 487 switch (wValue) { 488 case USB_ENDPOINT_HALT: 489 dep = dwc3_wIndex_to_dep(dwc, wIndex); 490 if (!dep) 491 return -EINVAL; 492 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 493 break; 494 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 495 if (ret) 496 return -EINVAL; 497 break; 498 default: 499 return -EINVAL; 500 } 501 break; 502 503 default: 504 return -EINVAL; 505 } 506 507 return 0; 508 } 509 510 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 511 { 512 enum usb_device_state state = dwc->gadget.state; 513 u32 addr; 514 u32 reg; 515 516 addr = le16_to_cpu(ctrl->wValue); 517 if (addr > 127) { 518 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr); 519 return -EINVAL; 520 } 521 522 if (state == USB_STATE_CONFIGURED) { 523 dwc3_trace(trace_dwc3_ep0, 524 "trying to set address when configured"); 525 return -EINVAL; 526 } 527 528 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 529 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 530 reg |= DWC3_DCFG_DEVADDR(addr); 531 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 532 533 if (addr) 534 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 535 else 536 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 537 538 return 0; 539 } 540 541 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 542 { 543 int ret; 544 545 spin_unlock(&dwc->lock); 546 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 547 spin_lock(&dwc->lock); 548 return ret; 549 } 550 551 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 552 { 553 enum usb_device_state state = dwc->gadget.state; 554 u32 cfg; 555 int ret; 556 u32 reg; 557 558 dwc->start_config_issued = false; 559 cfg = le16_to_cpu(ctrl->wValue); 560 561 switch (state) { 562 case USB_STATE_DEFAULT: 563 return -EINVAL; 564 565 case USB_STATE_ADDRESS: 566 ret = dwc3_ep0_delegate_req(dwc, ctrl); 567 /* if the cfg matches and the cfg is non zero */ 568 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 569 570 /* 571 * only change state if set_config has already 572 * been processed. If gadget driver returns 573 * USB_GADGET_DELAYED_STATUS, we will wait 574 * to change the state on the next usb_ep_queue() 575 */ 576 if (ret == 0) 577 usb_gadget_set_state(&dwc->gadget, 578 USB_STATE_CONFIGURED); 579 580 /* 581 * Enable transition to U1/U2 state when 582 * nothing is pending from application. 583 */ 584 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 585 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 586 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 587 588 dwc->resize_fifos = true; 589 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET"); 590 } 591 break; 592 593 case USB_STATE_CONFIGURED: 594 ret = dwc3_ep0_delegate_req(dwc, ctrl); 595 if (!cfg && !ret) 596 usb_gadget_set_state(&dwc->gadget, 597 USB_STATE_ADDRESS); 598 break; 599 default: 600 ret = -EINVAL; 601 } 602 return ret; 603 } 604 605 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 606 { 607 struct dwc3_ep *dep = to_dwc3_ep(ep); 608 struct dwc3 *dwc = dep->dwc; 609 610 u32 param = 0; 611 u32 reg; 612 613 struct timing { 614 u8 u1sel; 615 u8 u1pel; 616 u16 u2sel; 617 u16 u2pel; 618 } __packed timing; 619 620 int ret; 621 622 memcpy(&timing, req->buf, sizeof(timing)); 623 624 dwc->u1sel = timing.u1sel; 625 dwc->u1pel = timing.u1pel; 626 dwc->u2sel = le16_to_cpu(timing.u2sel); 627 dwc->u2pel = le16_to_cpu(timing.u2pel); 628 629 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 630 if (reg & DWC3_DCTL_INITU2ENA) 631 param = dwc->u2pel; 632 if (reg & DWC3_DCTL_INITU1ENA) 633 param = dwc->u1pel; 634 635 /* 636 * According to Synopsys Databook, if parameter is 637 * greater than 125, a value of zero should be 638 * programmed in the register. 639 */ 640 if (param > 125) 641 param = 0; 642 643 /* now that we have the time, issue DGCMD Set Sel */ 644 ret = dwc3_send_gadget_generic_command(dwc, 645 DWC3_DGCMD_SET_PERIODIC_PAR, param); 646 WARN_ON(ret < 0); 647 } 648 649 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 650 { 651 struct dwc3_ep *dep; 652 enum usb_device_state state = dwc->gadget.state; 653 u16 wLength; 654 u16 wValue; 655 656 if (state == USB_STATE_DEFAULT) 657 return -EINVAL; 658 659 wValue = le16_to_cpu(ctrl->wValue); 660 wLength = le16_to_cpu(ctrl->wLength); 661 662 if (wLength != 6) { 663 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 664 wLength); 665 return -EINVAL; 666 } 667 668 /* 669 * To handle Set SEL we need to receive 6 bytes from Host. So let's 670 * queue a usb_request for 6 bytes. 671 * 672 * Remember, though, this controller can't handle non-wMaxPacketSize 673 * aligned transfers on the OUT direction, so we queue a request for 674 * wMaxPacketSize instead. 675 */ 676 dep = dwc->eps[0]; 677 dwc->ep0_usb_req.dep = dep; 678 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 679 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 680 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 681 682 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 683 } 684 685 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 686 { 687 u16 wLength; 688 u16 wValue; 689 u16 wIndex; 690 691 wValue = le16_to_cpu(ctrl->wValue); 692 wLength = le16_to_cpu(ctrl->wLength); 693 wIndex = le16_to_cpu(ctrl->wIndex); 694 695 if (wIndex || wLength) 696 return -EINVAL; 697 698 /* 699 * REVISIT It's unclear from Databook what to do with this 700 * value. For now, just cache it. 701 */ 702 dwc->isoch_delay = wValue; 703 704 return 0; 705 } 706 707 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 708 { 709 int ret; 710 711 switch (ctrl->bRequest) { 712 case USB_REQ_GET_STATUS: 713 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS"); 714 ret = dwc3_ep0_handle_status(dwc, ctrl); 715 break; 716 case USB_REQ_CLEAR_FEATURE: 717 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE"); 718 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 719 break; 720 case USB_REQ_SET_FEATURE: 721 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE"); 722 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 723 break; 724 case USB_REQ_SET_ADDRESS: 725 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS"); 726 ret = dwc3_ep0_set_address(dwc, ctrl); 727 break; 728 case USB_REQ_SET_CONFIGURATION: 729 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION"); 730 ret = dwc3_ep0_set_config(dwc, ctrl); 731 break; 732 case USB_REQ_SET_SEL: 733 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL"); 734 ret = dwc3_ep0_set_sel(dwc, ctrl); 735 break; 736 case USB_REQ_SET_ISOCH_DELAY: 737 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY"); 738 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 739 break; 740 case USB_REQ_SET_INTERFACE: 741 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_INTERFACE"); 742 dwc->start_config_issued = false; 743 /* Fall through */ 744 default: 745 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver"); 746 ret = dwc3_ep0_delegate_req(dwc, ctrl); 747 break; 748 } 749 750 return ret; 751 } 752 753 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 754 const struct dwc3_event_depevt *event) 755 { 756 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 757 int ret = -EINVAL; 758 u32 len; 759 760 if (!dwc->gadget_driver) 761 goto out; 762 763 trace_dwc3_ctrl_req(ctrl); 764 765 len = le16_to_cpu(ctrl->wLength); 766 if (!len) { 767 dwc->three_stage_setup = false; 768 dwc->ep0_expect_in = false; 769 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 770 } else { 771 dwc->three_stage_setup = true; 772 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 773 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 774 } 775 776 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 777 ret = dwc3_ep0_std_request(dwc, ctrl); 778 else 779 ret = dwc3_ep0_delegate_req(dwc, ctrl); 780 781 if (ret == USB_GADGET_DELAYED_STATUS) 782 dwc->delayed_status = true; 783 784 out: 785 if (ret < 0) 786 dwc3_ep0_stall_and_restart(dwc); 787 } 788 789 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 790 const struct dwc3_event_depevt *event) 791 { 792 struct dwc3_request *r = NULL; 793 struct usb_request *ur; 794 struct dwc3_trb *trb; 795 struct dwc3_ep *ep0; 796 unsigned transfer_size = 0; 797 unsigned maxp; 798 unsigned remaining_ur_length; 799 void *buf; 800 u32 transferred = 0; 801 u32 status; 802 u32 length; 803 u8 epnum; 804 805 epnum = event->endpoint_number; 806 ep0 = dwc->eps[0]; 807 808 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 809 810 trb = dwc->ep0_trb; 811 812 trace_dwc3_complete_trb(ep0, trb); 813 814 r = next_request(&ep0->request_list); 815 if (!r) 816 return; 817 818 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 819 if (status == DWC3_TRBSTS_SETUP_PENDING) { 820 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 821 822 if (r) 823 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 824 825 return; 826 } 827 828 ur = &r->request; 829 buf = ur->buf; 830 remaining_ur_length = ur->length; 831 832 length = trb->size & DWC3_TRB_SIZE_MASK; 833 834 maxp = ep0->endpoint.maxpacket; 835 836 if (dwc->ep0_bounced) { 837 /* 838 * Handle the first TRB before handling the bounce buffer if 839 * the request length is greater than the bounce buffer size 840 */ 841 if (ur->length > DWC3_EP0_BOUNCE_SIZE) { 842 transfer_size = ALIGN(ur->length - maxp, maxp); 843 transferred = transfer_size - length; 844 buf = (u8 *)buf + transferred; 845 ur->actual += transferred; 846 remaining_ur_length -= transferred; 847 848 trb++; 849 length = trb->size & DWC3_TRB_SIZE_MASK; 850 851 ep0->free_slot = 0; 852 } 853 854 transfer_size = roundup((ur->length - transfer_size), 855 maxp); 856 857 transferred = min_t(u32, remaining_ur_length, 858 transfer_size - length); 859 memcpy(buf, dwc->ep0_bounce, transferred); 860 } else { 861 transferred = ur->length - length; 862 } 863 864 ur->actual += transferred; 865 866 if ((epnum & 1) && ur->actual < ur->length) { 867 /* for some reason we did not get everything out */ 868 869 dwc3_ep0_stall_and_restart(dwc); 870 } else { 871 dwc3_gadget_giveback(ep0, r, 0); 872 873 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 874 ur->length && ur->zero) { 875 int ret; 876 877 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 878 879 ret = dwc3_ep0_start_trans(dwc, epnum, 880 dwc->ctrl_req_addr, 0, 881 DWC3_TRBCTL_CONTROL_DATA, false); 882 WARN_ON(ret < 0); 883 } 884 } 885 } 886 887 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 888 const struct dwc3_event_depevt *event) 889 { 890 struct dwc3_request *r; 891 struct dwc3_ep *dep; 892 struct dwc3_trb *trb; 893 u32 status; 894 895 dep = dwc->eps[0]; 896 trb = dwc->ep0_trb; 897 898 trace_dwc3_complete_trb(dep, trb); 899 900 if (!list_empty(&dep->request_list)) { 901 r = next_request(&dep->request_list); 902 903 dwc3_gadget_giveback(dep, r, 0); 904 } 905 906 if (dwc->test_mode) { 907 int ret; 908 909 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 910 if (ret < 0) { 911 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d", 912 dwc->test_mode_nr); 913 dwc3_ep0_stall_and_restart(dwc); 914 return; 915 } 916 } 917 918 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 919 if (status == DWC3_TRBSTS_SETUP_PENDING) 920 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 921 922 dwc->ep0state = EP0_SETUP_PHASE; 923 dwc3_ep0_out_start(dwc); 924 } 925 926 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 927 const struct dwc3_event_depevt *event) 928 { 929 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 930 931 dep->flags &= ~DWC3_EP_BUSY; 932 dep->resource_index = 0; 933 dwc->setup_packet_pending = false; 934 935 switch (dwc->ep0state) { 936 case EP0_SETUP_PHASE: 937 dwc3_trace(trace_dwc3_ep0, "Setup Phase"); 938 dwc3_ep0_inspect_setup(dwc, event); 939 break; 940 941 case EP0_DATA_PHASE: 942 dwc3_trace(trace_dwc3_ep0, "Data Phase"); 943 dwc3_ep0_complete_data(dwc, event); 944 break; 945 946 case EP0_STATUS_PHASE: 947 dwc3_trace(trace_dwc3_ep0, "Status Phase"); 948 dwc3_ep0_complete_status(dwc, event); 949 break; 950 default: 951 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 952 } 953 } 954 955 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 956 struct dwc3_ep *dep, struct dwc3_request *req) 957 { 958 int ret; 959 960 req->direction = !!dep->number; 961 962 if (req->request.length == 0) { 963 ret = dwc3_ep0_start_trans(dwc, dep->number, 964 dwc->ctrl_req_addr, 0, 965 DWC3_TRBCTL_CONTROL_DATA, false); 966 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 967 && (dep->number == 0)) { 968 u32 transfer_size = 0; 969 u32 maxpacket; 970 971 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 972 dep->number); 973 if (ret) { 974 dev_dbg(dwc->dev, "failed to map request\n"); 975 return; 976 } 977 978 maxpacket = dep->endpoint.maxpacket; 979 980 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) { 981 transfer_size = ALIGN(req->request.length - maxpacket, 982 maxpacket); 983 ret = dwc3_ep0_start_trans(dwc, dep->number, 984 req->request.dma, 985 transfer_size, 986 DWC3_TRBCTL_CONTROL_DATA, 987 true); 988 } 989 990 transfer_size = roundup((req->request.length - transfer_size), 991 maxpacket); 992 993 dwc->ep0_bounced = true; 994 995 ret = dwc3_ep0_start_trans(dwc, dep->number, 996 dwc->ep0_bounce_addr, transfer_size, 997 DWC3_TRBCTL_CONTROL_DATA, false); 998 } else { 999 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1000 dep->number); 1001 if (ret) { 1002 dev_dbg(dwc->dev, "failed to map request\n"); 1003 return; 1004 } 1005 1006 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 1007 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1008 false); 1009 } 1010 1011 WARN_ON(ret < 0); 1012 } 1013 1014 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1015 { 1016 struct dwc3 *dwc = dep->dwc; 1017 u32 type; 1018 1019 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1020 : DWC3_TRBCTL_CONTROL_STATUS2; 1021 1022 return dwc3_ep0_start_trans(dwc, dep->number, 1023 dwc->ctrl_req_addr, 0, type, false); 1024 } 1025 1026 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1027 { 1028 if (dwc->resize_fifos) { 1029 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs"); 1030 dwc3_gadget_resize_tx_fifos(dwc); 1031 dwc->resize_fifos = 0; 1032 } 1033 1034 WARN_ON(dwc3_ep0_start_control_status(dep)); 1035 } 1036 1037 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1038 const struct dwc3_event_depevt *event) 1039 { 1040 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1041 1042 __dwc3_ep0_do_control_status(dwc, dep); 1043 } 1044 1045 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1046 { 1047 struct dwc3_gadget_ep_cmd_params params; 1048 u32 cmd; 1049 int ret; 1050 1051 if (!dep->resource_index) 1052 return; 1053 1054 cmd = DWC3_DEPCMD_ENDTRANSFER; 1055 cmd |= DWC3_DEPCMD_CMDIOC; 1056 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1057 memset(¶ms, 0, sizeof(params)); 1058 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1059 WARN_ON_ONCE(ret); 1060 dep->resource_index = 0; 1061 } 1062 1063 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1064 const struct dwc3_event_depevt *event) 1065 { 1066 dwc->setup_packet_pending = true; 1067 1068 switch (event->status) { 1069 case DEPEVT_STATUS_CONTROL_DATA: 1070 dwc3_trace(trace_dwc3_ep0, "Control Data"); 1071 1072 /* 1073 * We already have a DATA transfer in the controller's cache, 1074 * if we receive a XferNotReady(DATA) we will ignore it, unless 1075 * it's for the wrong direction. 1076 * 1077 * In that case, we must issue END_TRANSFER command to the Data 1078 * Phase we already have started and issue SetStall on the 1079 * control endpoint. 1080 */ 1081 if (dwc->ep0_expect_in != event->endpoint_number) { 1082 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1083 1084 dwc3_trace(trace_dwc3_ep0, 1085 "Wrong direction for Data phase"); 1086 dwc3_ep0_end_control_data(dwc, dep); 1087 dwc3_ep0_stall_and_restart(dwc); 1088 return; 1089 } 1090 1091 break; 1092 1093 case DEPEVT_STATUS_CONTROL_STATUS: 1094 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1095 return; 1096 1097 dwc3_trace(trace_dwc3_ep0, "Control Status"); 1098 1099 dwc->ep0state = EP0_STATUS_PHASE; 1100 1101 if (dwc->delayed_status) { 1102 WARN_ON_ONCE(event->endpoint_number != 1); 1103 dwc3_trace(trace_dwc3_ep0, "Delayed Status"); 1104 return; 1105 } 1106 1107 dwc3_ep0_do_control_status(dwc, event); 1108 } 1109 } 1110 1111 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1112 const struct dwc3_event_depevt *event) 1113 { 1114 u8 epnum = event->endpoint_number; 1115 1116 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'", 1117 dwc3_ep_event_string(event->endpoint_event), 1118 epnum >> 1, (epnum & 1) ? "in" : "out", 1119 dwc3_ep0_state_string(dwc->ep0state)); 1120 1121 switch (event->endpoint_event) { 1122 case DWC3_DEPEVT_XFERCOMPLETE: 1123 dwc3_ep0_xfer_complete(dwc, event); 1124 break; 1125 1126 case DWC3_DEPEVT_XFERNOTREADY: 1127 dwc3_ep0_xfernotready(dwc, event); 1128 break; 1129 1130 case DWC3_DEPEVT_XFERINPROGRESS: 1131 case DWC3_DEPEVT_RXTXFIFOEVT: 1132 case DWC3_DEPEVT_STREAMEVT: 1133 case DWC3_DEPEVT_EPCMDCMPLT: 1134 break; 1135 } 1136 } 1137