1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/interrupt.h> 45 #include <linux/io.h> 46 #include <linux/list.h> 47 #include <linux/dma-mapping.h> 48 49 #include <linux/usb/ch9.h> 50 #include <linux/usb/gadget.h> 51 #include <linux/usb/composite.h> 52 53 #include "core.h" 54 #include "gadget.h" 55 #include "io.h" 56 57 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 58 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 59 struct dwc3_ep *dep, struct dwc3_request *req); 60 61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 62 { 63 switch (state) { 64 case EP0_UNCONNECTED: 65 return "Unconnected"; 66 case EP0_SETUP_PHASE: 67 return "Setup Phase"; 68 case EP0_DATA_PHASE: 69 return "Data Phase"; 70 case EP0_STATUS_PHASE: 71 return "Status Phase"; 72 default: 73 return "UNKNOWN"; 74 } 75 } 76 77 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 78 u32 len, u32 type) 79 { 80 struct dwc3_gadget_ep_cmd_params params; 81 struct dwc3_trb *trb; 82 struct dwc3_ep *dep; 83 84 int ret; 85 86 dep = dwc->eps[epnum]; 87 if (dep->flags & DWC3_EP_BUSY) { 88 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); 89 return 0; 90 } 91 92 trb = dwc->ep0_trb; 93 94 trb->bpl = lower_32_bits(buf_dma); 95 trb->bph = upper_32_bits(buf_dma); 96 trb->size = len; 97 trb->ctrl = type; 98 99 trb->ctrl |= (DWC3_TRB_CTRL_HWO 100 | DWC3_TRB_CTRL_LST 101 | DWC3_TRB_CTRL_IOC 102 | DWC3_TRB_CTRL_ISP_IMI); 103 104 memset(¶ms, 0, sizeof(params)); 105 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 106 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 107 108 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 109 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 110 if (ret < 0) { 111 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 112 return ret; 113 } 114 115 dep->flags |= DWC3_EP_BUSY; 116 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 117 dep->number); 118 119 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 120 121 return 0; 122 } 123 124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 125 struct dwc3_request *req) 126 { 127 struct dwc3 *dwc = dep->dwc; 128 129 req->request.actual = 0; 130 req->request.status = -EINPROGRESS; 131 req->epnum = dep->number; 132 133 list_add_tail(&req->list, &dep->request_list); 134 135 /* 136 * Gadget driver might not be quick enough to queue a request 137 * before we get a Transfer Not Ready event on this endpoint. 138 * 139 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 140 * flag is set, it's telling us that as soon as Gadget queues the 141 * required request, we should kick the transfer here because the 142 * IRQ we were waiting for is long gone. 143 */ 144 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 145 unsigned direction; 146 147 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 148 149 if (dwc->ep0state != EP0_DATA_PHASE) { 150 dev_WARN(dwc->dev, "Unexpected pending request\n"); 151 return 0; 152 } 153 154 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 155 156 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 157 DWC3_EP0_DIR_IN); 158 159 return 0; 160 } 161 162 /* 163 * In case gadget driver asked us to delay the STATUS phase, 164 * handle it here. 165 */ 166 if (dwc->delayed_status) { 167 unsigned direction; 168 169 direction = !dwc->ep0_expect_in; 170 dwc->delayed_status = false; 171 172 if (dwc->ep0state == EP0_STATUS_PHASE) 173 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 174 else 175 dev_dbg(dwc->dev, "too early for delayed status\n"); 176 177 return 0; 178 } 179 180 /* 181 * Unfortunately we have uncovered a limitation wrt the Data Phase. 182 * 183 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 184 * come before issueing Start Transfer command, but if we do, we will 185 * miss situations where the host starts another SETUP phase instead of 186 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 187 * Layer Compliance Suite. 188 * 189 * The problem surfaces due to the fact that in case of back-to-back 190 * SETUP packets there will be no XferNotReady(DATA) generated and we 191 * will be stuck waiting for XferNotReady(DATA) forever. 192 * 193 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 194 * it tells us to start Data Phase right away. It also mentions that if 195 * we receive a SETUP phase instead of the DATA phase, core will issue 196 * XferComplete for the DATA phase, before actually initiating it in 197 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 198 * can only be used to print some debugging logs, as the core expects 199 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 200 * just so it completes right away, without transferring anything and, 201 * only then, we can go back to the SETUP phase. 202 * 203 * Because of this scenario, SNPS decided to change the programming 204 * model of control transfers and support on-demand transfers only for 205 * the STATUS phase. To fix the issue we have now, we will always wait 206 * for gadget driver to queue the DATA phase's struct usb_request, then 207 * start it right away. 208 * 209 * If we're actually in a 2-stage transfer, we will wait for 210 * XferNotReady(STATUS). 211 */ 212 if (dwc->three_stage_setup) { 213 unsigned direction; 214 215 direction = dwc->ep0_expect_in; 216 dwc->ep0state = EP0_DATA_PHASE; 217 218 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 219 220 dep->flags &= ~DWC3_EP0_DIR_IN; 221 } 222 223 return 0; 224 } 225 226 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 227 gfp_t gfp_flags) 228 { 229 struct dwc3_request *req = to_dwc3_request(request); 230 struct dwc3_ep *dep = to_dwc3_ep(ep); 231 struct dwc3 *dwc = dep->dwc; 232 233 unsigned long flags; 234 235 int ret; 236 237 spin_lock_irqsave(&dwc->lock, flags); 238 if (!dep->endpoint.desc) { 239 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 240 request, dep->name); 241 ret = -ESHUTDOWN; 242 goto out; 243 } 244 245 /* we share one TRB for ep0/1 */ 246 if (!list_empty(&dep->request_list)) { 247 ret = -EBUSY; 248 goto out; 249 } 250 251 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", 252 request, dep->name, request->length, 253 dwc3_ep0_state_string(dwc->ep0state)); 254 255 ret = __dwc3_gadget_ep0_queue(dep, req); 256 257 out: 258 spin_unlock_irqrestore(&dwc->lock, flags); 259 260 return ret; 261 } 262 263 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 264 { 265 struct dwc3_ep *dep; 266 267 /* reinitialize physical ep1 */ 268 dep = dwc->eps[1]; 269 dep->flags = DWC3_EP_ENABLED; 270 271 /* stall is always issued on EP0 */ 272 dep = dwc->eps[0]; 273 __dwc3_gadget_ep_set_halt(dep, 1); 274 dep->flags = DWC3_EP_ENABLED; 275 dwc->delayed_status = false; 276 277 if (!list_empty(&dep->request_list)) { 278 struct dwc3_request *req; 279 280 req = next_request(&dep->request_list); 281 dwc3_gadget_giveback(dep, req, -ECONNRESET); 282 } 283 284 dwc->ep0state = EP0_SETUP_PHASE; 285 dwc3_ep0_out_start(dwc); 286 } 287 288 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 289 { 290 struct dwc3_ep *dep = to_dwc3_ep(ep); 291 struct dwc3 *dwc = dep->dwc; 292 293 dwc3_ep0_stall_and_restart(dwc); 294 295 return 0; 296 } 297 298 void dwc3_ep0_out_start(struct dwc3 *dwc) 299 { 300 int ret; 301 302 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 303 DWC3_TRBCTL_CONTROL_SETUP); 304 WARN_ON(ret < 0); 305 } 306 307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 308 { 309 struct dwc3_ep *dep; 310 u32 windex = le16_to_cpu(wIndex_le); 311 u32 epnum; 312 313 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 314 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 315 epnum |= 1; 316 317 dep = dwc->eps[epnum]; 318 if (dep->flags & DWC3_EP_ENABLED) 319 return dep; 320 321 return NULL; 322 } 323 324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 325 { 326 } 327 /* 328 * ch 9.4.5 329 */ 330 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 331 struct usb_ctrlrequest *ctrl) 332 { 333 struct dwc3_ep *dep; 334 u32 recip; 335 u32 reg; 336 u16 usb_status = 0; 337 __le16 *response_pkt; 338 339 recip = ctrl->bRequestType & USB_RECIP_MASK; 340 switch (recip) { 341 case USB_RECIP_DEVICE: 342 /* 343 * LTM will be set once we know how to set this in HW. 344 */ 345 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 346 347 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 348 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 349 if (reg & DWC3_DCTL_INITU1ENA) 350 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 351 if (reg & DWC3_DCTL_INITU2ENA) 352 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 353 } 354 355 break; 356 357 case USB_RECIP_INTERFACE: 358 /* 359 * Function Remote Wake Capable D0 360 * Function Remote Wakeup D1 361 */ 362 break; 363 364 case USB_RECIP_ENDPOINT: 365 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 366 if (!dep) 367 return -EINVAL; 368 369 if (dep->flags & DWC3_EP_STALL) 370 usb_status = 1 << USB_ENDPOINT_HALT; 371 break; 372 default: 373 return -EINVAL; 374 }; 375 376 response_pkt = (__le16 *) dwc->setup_buf; 377 *response_pkt = cpu_to_le16(usb_status); 378 379 dep = dwc->eps[0]; 380 dwc->ep0_usb_req.dep = dep; 381 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 382 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 383 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 384 385 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 386 } 387 388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 389 struct usb_ctrlrequest *ctrl, int set) 390 { 391 struct dwc3_ep *dep; 392 u32 recip; 393 u32 wValue; 394 u32 wIndex; 395 u32 reg; 396 int ret; 397 398 wValue = le16_to_cpu(ctrl->wValue); 399 wIndex = le16_to_cpu(ctrl->wIndex); 400 recip = ctrl->bRequestType & USB_RECIP_MASK; 401 switch (recip) { 402 case USB_RECIP_DEVICE: 403 404 switch (wValue) { 405 case USB_DEVICE_REMOTE_WAKEUP: 406 break; 407 /* 408 * 9.4.1 says only only for SS, in AddressState only for 409 * default control pipe 410 */ 411 case USB_DEVICE_U1_ENABLE: 412 if (dwc->dev_state != DWC3_CONFIGURED_STATE) 413 return -EINVAL; 414 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 415 return -EINVAL; 416 417 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 418 if (set) 419 reg |= DWC3_DCTL_INITU1ENA; 420 else 421 reg &= ~DWC3_DCTL_INITU1ENA; 422 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 423 break; 424 425 case USB_DEVICE_U2_ENABLE: 426 if (dwc->dev_state != DWC3_CONFIGURED_STATE) 427 return -EINVAL; 428 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 429 return -EINVAL; 430 431 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 432 if (set) 433 reg |= DWC3_DCTL_INITU2ENA; 434 else 435 reg &= ~DWC3_DCTL_INITU2ENA; 436 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 437 break; 438 439 case USB_DEVICE_LTM_ENABLE: 440 return -EINVAL; 441 break; 442 443 case USB_DEVICE_TEST_MODE: 444 if ((wIndex & 0xff) != 0) 445 return -EINVAL; 446 if (!set) 447 return -EINVAL; 448 449 dwc->test_mode_nr = wIndex >> 8; 450 dwc->test_mode = true; 451 break; 452 default: 453 return -EINVAL; 454 } 455 break; 456 457 case USB_RECIP_INTERFACE: 458 switch (wValue) { 459 case USB_INTRF_FUNC_SUSPEND: 460 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 461 /* XXX enable Low power suspend */ 462 ; 463 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 464 /* XXX enable remote wakeup */ 465 ; 466 break; 467 default: 468 return -EINVAL; 469 } 470 break; 471 472 case USB_RECIP_ENDPOINT: 473 switch (wValue) { 474 case USB_ENDPOINT_HALT: 475 dep = dwc3_wIndex_to_dep(dwc, wIndex); 476 if (!dep) 477 return -EINVAL; 478 ret = __dwc3_gadget_ep_set_halt(dep, set); 479 if (ret) 480 return -EINVAL; 481 break; 482 default: 483 return -EINVAL; 484 } 485 break; 486 487 default: 488 return -EINVAL; 489 }; 490 491 return 0; 492 } 493 494 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 495 { 496 u32 addr; 497 u32 reg; 498 499 addr = le16_to_cpu(ctrl->wValue); 500 if (addr > 127) { 501 dev_dbg(dwc->dev, "invalid device address %d\n", addr); 502 return -EINVAL; 503 } 504 505 if (dwc->dev_state == DWC3_CONFIGURED_STATE) { 506 dev_dbg(dwc->dev, "trying to set address when configured\n"); 507 return -EINVAL; 508 } 509 510 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 511 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 512 reg |= DWC3_DCFG_DEVADDR(addr); 513 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 514 515 if (addr) 516 dwc->dev_state = DWC3_ADDRESS_STATE; 517 else 518 dwc->dev_state = DWC3_DEFAULT_STATE; 519 520 return 0; 521 } 522 523 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 524 { 525 int ret; 526 527 spin_unlock(&dwc->lock); 528 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 529 spin_lock(&dwc->lock); 530 return ret; 531 } 532 533 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 534 { 535 u32 cfg; 536 int ret; 537 u32 reg; 538 539 dwc->start_config_issued = false; 540 cfg = le16_to_cpu(ctrl->wValue); 541 542 switch (dwc->dev_state) { 543 case DWC3_DEFAULT_STATE: 544 return -EINVAL; 545 break; 546 547 case DWC3_ADDRESS_STATE: 548 ret = dwc3_ep0_delegate_req(dwc, ctrl); 549 /* if the cfg matches and the cfg is non zero */ 550 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 551 dwc->dev_state = DWC3_CONFIGURED_STATE; 552 /* 553 * Enable transition to U1/U2 state when 554 * nothing is pending from application. 555 */ 556 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 557 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 558 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 559 560 dwc->resize_fifos = true; 561 dev_dbg(dwc->dev, "resize fifos flag SET\n"); 562 } 563 break; 564 565 case DWC3_CONFIGURED_STATE: 566 ret = dwc3_ep0_delegate_req(dwc, ctrl); 567 if (!cfg) 568 dwc->dev_state = DWC3_ADDRESS_STATE; 569 break; 570 default: 571 ret = -EINVAL; 572 } 573 return ret; 574 } 575 576 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 577 { 578 struct dwc3_ep *dep = to_dwc3_ep(ep); 579 struct dwc3 *dwc = dep->dwc; 580 581 u32 param = 0; 582 u32 reg; 583 584 struct timing { 585 u8 u1sel; 586 u8 u1pel; 587 u16 u2sel; 588 u16 u2pel; 589 } __packed timing; 590 591 int ret; 592 593 memcpy(&timing, req->buf, sizeof(timing)); 594 595 dwc->u1sel = timing.u1sel; 596 dwc->u1pel = timing.u1pel; 597 dwc->u2sel = le16_to_cpu(timing.u2sel); 598 dwc->u2pel = le16_to_cpu(timing.u2pel); 599 600 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 601 if (reg & DWC3_DCTL_INITU2ENA) 602 param = dwc->u2pel; 603 if (reg & DWC3_DCTL_INITU1ENA) 604 param = dwc->u1pel; 605 606 /* 607 * According to Synopsys Databook, if parameter is 608 * greater than 125, a value of zero should be 609 * programmed in the register. 610 */ 611 if (param > 125) 612 param = 0; 613 614 /* now that we have the time, issue DGCMD Set Sel */ 615 ret = dwc3_send_gadget_generic_command(dwc, 616 DWC3_DGCMD_SET_PERIODIC_PAR, param); 617 WARN_ON(ret < 0); 618 } 619 620 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 621 { 622 struct dwc3_ep *dep; 623 u16 wLength; 624 u16 wValue; 625 626 if (dwc->dev_state == DWC3_DEFAULT_STATE) 627 return -EINVAL; 628 629 wValue = le16_to_cpu(ctrl->wValue); 630 wLength = le16_to_cpu(ctrl->wLength); 631 632 if (wLength != 6) { 633 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 634 wLength); 635 return -EINVAL; 636 } 637 638 /* 639 * To handle Set SEL we need to receive 6 bytes from Host. So let's 640 * queue a usb_request for 6 bytes. 641 * 642 * Remember, though, this controller can't handle non-wMaxPacketSize 643 * aligned transfers on the OUT direction, so we queue a request for 644 * wMaxPacketSize instead. 645 */ 646 dep = dwc->eps[0]; 647 dwc->ep0_usb_req.dep = dep; 648 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 649 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 650 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 651 652 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 653 } 654 655 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 656 { 657 u16 wLength; 658 u16 wValue; 659 u16 wIndex; 660 661 wValue = le16_to_cpu(ctrl->wValue); 662 wLength = le16_to_cpu(ctrl->wLength); 663 wIndex = le16_to_cpu(ctrl->wIndex); 664 665 if (wIndex || wLength) 666 return -EINVAL; 667 668 /* 669 * REVISIT It's unclear from Databook what to do with this 670 * value. For now, just cache it. 671 */ 672 dwc->isoch_delay = wValue; 673 674 return 0; 675 } 676 677 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 678 { 679 int ret; 680 681 switch (ctrl->bRequest) { 682 case USB_REQ_GET_STATUS: 683 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); 684 ret = dwc3_ep0_handle_status(dwc, ctrl); 685 break; 686 case USB_REQ_CLEAR_FEATURE: 687 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); 688 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 689 break; 690 case USB_REQ_SET_FEATURE: 691 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); 692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 693 break; 694 case USB_REQ_SET_ADDRESS: 695 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); 696 ret = dwc3_ep0_set_address(dwc, ctrl); 697 break; 698 case USB_REQ_SET_CONFIGURATION: 699 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); 700 ret = dwc3_ep0_set_config(dwc, ctrl); 701 break; 702 case USB_REQ_SET_SEL: 703 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); 704 ret = dwc3_ep0_set_sel(dwc, ctrl); 705 break; 706 case USB_REQ_SET_ISOCH_DELAY: 707 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); 708 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 709 break; 710 default: 711 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); 712 ret = dwc3_ep0_delegate_req(dwc, ctrl); 713 break; 714 }; 715 716 return ret; 717 } 718 719 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 720 const struct dwc3_event_depevt *event) 721 { 722 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 723 int ret = -EINVAL; 724 u32 len; 725 726 if (!dwc->gadget_driver) 727 goto out; 728 729 len = le16_to_cpu(ctrl->wLength); 730 if (!len) { 731 dwc->three_stage_setup = false; 732 dwc->ep0_expect_in = false; 733 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 734 } else { 735 dwc->three_stage_setup = true; 736 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 737 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 738 } 739 740 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 741 ret = dwc3_ep0_std_request(dwc, ctrl); 742 else 743 ret = dwc3_ep0_delegate_req(dwc, ctrl); 744 745 if (ret == USB_GADGET_DELAYED_STATUS) 746 dwc->delayed_status = true; 747 748 out: 749 if (ret < 0) 750 dwc3_ep0_stall_and_restart(dwc); 751 } 752 753 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 754 const struct dwc3_event_depevt *event) 755 { 756 struct dwc3_request *r = NULL; 757 struct usb_request *ur; 758 struct dwc3_trb *trb; 759 struct dwc3_ep *ep0; 760 u32 transferred; 761 u32 status; 762 u32 length; 763 u8 epnum; 764 765 epnum = event->endpoint_number; 766 ep0 = dwc->eps[0]; 767 768 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 769 770 r = next_request(&ep0->request_list); 771 ur = &r->request; 772 773 trb = dwc->ep0_trb; 774 775 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 776 if (status == DWC3_TRBSTS_SETUP_PENDING) { 777 dev_dbg(dwc->dev, "Setup Pending received\n"); 778 779 if (r) 780 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 781 782 return; 783 } 784 785 length = trb->size & DWC3_TRB_SIZE_MASK; 786 787 if (dwc->ep0_bounced) { 788 unsigned transfer_size = ur->length; 789 unsigned maxp = ep0->endpoint.maxpacket; 790 791 transfer_size += (maxp - (transfer_size % maxp)); 792 transferred = min_t(u32, ur->length, 793 transfer_size - length); 794 memcpy(ur->buf, dwc->ep0_bounce, transferred); 795 } else { 796 transferred = ur->length - length; 797 } 798 799 ur->actual += transferred; 800 801 if ((epnum & 1) && ur->actual < ur->length) { 802 /* for some reason we did not get everything out */ 803 804 dwc3_ep0_stall_and_restart(dwc); 805 } else { 806 /* 807 * handle the case where we have to send a zero packet. This 808 * seems to be case when req.length > maxpacket. Could it be? 809 */ 810 if (r) 811 dwc3_gadget_giveback(ep0, r, 0); 812 } 813 } 814 815 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 816 const struct dwc3_event_depevt *event) 817 { 818 struct dwc3_request *r; 819 struct dwc3_ep *dep; 820 struct dwc3_trb *trb; 821 u32 status; 822 823 dep = dwc->eps[0]; 824 trb = dwc->ep0_trb; 825 826 if (!list_empty(&dep->request_list)) { 827 r = next_request(&dep->request_list); 828 829 dwc3_gadget_giveback(dep, r, 0); 830 } 831 832 if (dwc->test_mode) { 833 int ret; 834 835 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 836 if (ret < 0) { 837 dev_dbg(dwc->dev, "Invalid Test #%d\n", 838 dwc->test_mode_nr); 839 dwc3_ep0_stall_and_restart(dwc); 840 return; 841 } 842 } 843 844 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 845 if (status == DWC3_TRBSTS_SETUP_PENDING) 846 dev_dbg(dwc->dev, "Setup Pending received\n"); 847 848 dwc->ep0state = EP0_SETUP_PHASE; 849 dwc3_ep0_out_start(dwc); 850 } 851 852 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 853 const struct dwc3_event_depevt *event) 854 { 855 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 856 857 dep->flags &= ~DWC3_EP_BUSY; 858 dep->resource_index = 0; 859 dwc->setup_packet_pending = false; 860 861 switch (dwc->ep0state) { 862 case EP0_SETUP_PHASE: 863 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); 864 dwc3_ep0_inspect_setup(dwc, event); 865 break; 866 867 case EP0_DATA_PHASE: 868 dev_vdbg(dwc->dev, "Data Phase\n"); 869 dwc3_ep0_complete_data(dwc, event); 870 break; 871 872 case EP0_STATUS_PHASE: 873 dev_vdbg(dwc->dev, "Status Phase\n"); 874 dwc3_ep0_complete_status(dwc, event); 875 break; 876 default: 877 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 878 } 879 } 880 881 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 882 struct dwc3_ep *dep, struct dwc3_request *req) 883 { 884 int ret; 885 886 req->direction = !!dep->number; 887 888 if (req->request.length == 0) { 889 ret = dwc3_ep0_start_trans(dwc, dep->number, 890 dwc->ctrl_req_addr, 0, 891 DWC3_TRBCTL_CONTROL_DATA); 892 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 893 && (dep->number == 0)) { 894 u32 transfer_size; 895 896 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 897 dep->number); 898 if (ret) { 899 dev_dbg(dwc->dev, "failed to map request\n"); 900 return; 901 } 902 903 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); 904 905 transfer_size = roundup(req->request.length, 906 (u32) dep->endpoint.maxpacket); 907 908 dwc->ep0_bounced = true; 909 910 /* 911 * REVISIT in case request length is bigger than 912 * DWC3_EP0_BOUNCE_SIZE we will need two chained 913 * TRBs to handle the transfer. 914 */ 915 ret = dwc3_ep0_start_trans(dwc, dep->number, 916 dwc->ep0_bounce_addr, transfer_size, 917 DWC3_TRBCTL_CONTROL_DATA); 918 } else { 919 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 920 dep->number); 921 if (ret) { 922 dev_dbg(dwc->dev, "failed to map request\n"); 923 return; 924 } 925 926 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 927 req->request.length, DWC3_TRBCTL_CONTROL_DATA); 928 } 929 930 WARN_ON(ret < 0); 931 } 932 933 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 934 { 935 struct dwc3 *dwc = dep->dwc; 936 u32 type; 937 938 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 939 : DWC3_TRBCTL_CONTROL_STATUS2; 940 941 return dwc3_ep0_start_trans(dwc, dep->number, 942 dwc->ctrl_req_addr, 0, type); 943 } 944 945 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 946 { 947 if (dwc->resize_fifos) { 948 dev_dbg(dwc->dev, "starting to resize fifos\n"); 949 dwc3_gadget_resize_tx_fifos(dwc); 950 dwc->resize_fifos = 0; 951 } 952 953 WARN_ON(dwc3_ep0_start_control_status(dep)); 954 } 955 956 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 957 const struct dwc3_event_depevt *event) 958 { 959 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 960 961 __dwc3_ep0_do_control_status(dwc, dep); 962 } 963 964 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 965 { 966 struct dwc3_gadget_ep_cmd_params params; 967 u32 cmd; 968 int ret; 969 970 if (!dep->resource_index) 971 return; 972 973 cmd = DWC3_DEPCMD_ENDTRANSFER; 974 cmd |= DWC3_DEPCMD_CMDIOC; 975 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 976 memset(¶ms, 0, sizeof(params)); 977 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 978 WARN_ON_ONCE(ret); 979 dep->resource_index = 0; 980 } 981 982 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 983 const struct dwc3_event_depevt *event) 984 { 985 dwc->setup_packet_pending = true; 986 987 switch (event->status) { 988 case DEPEVT_STATUS_CONTROL_DATA: 989 dev_vdbg(dwc->dev, "Control Data\n"); 990 991 /* 992 * We already have a DATA transfer in the controller's cache, 993 * if we receive a XferNotReady(DATA) we will ignore it, unless 994 * it's for the wrong direction. 995 * 996 * In that case, we must issue END_TRANSFER command to the Data 997 * Phase we already have started and issue SetStall on the 998 * control endpoint. 999 */ 1000 if (dwc->ep0_expect_in != event->endpoint_number) { 1001 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1002 1003 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); 1004 dwc3_ep0_end_control_data(dwc, dep); 1005 dwc3_ep0_stall_and_restart(dwc); 1006 return; 1007 } 1008 1009 break; 1010 1011 case DEPEVT_STATUS_CONTROL_STATUS: 1012 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1013 return; 1014 1015 dev_vdbg(dwc->dev, "Control Status\n"); 1016 1017 dwc->ep0state = EP0_STATUS_PHASE; 1018 1019 if (dwc->delayed_status) { 1020 WARN_ON_ONCE(event->endpoint_number != 1); 1021 dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); 1022 return; 1023 } 1024 1025 dwc3_ep0_do_control_status(dwc, event); 1026 } 1027 } 1028 1029 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1030 const struct dwc3_event_depevt *event) 1031 { 1032 u8 epnum = event->endpoint_number; 1033 1034 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", 1035 dwc3_ep_event_string(event->endpoint_event), 1036 epnum >> 1, (epnum & 1) ? "in" : "out", 1037 dwc3_ep0_state_string(dwc->ep0state)); 1038 1039 switch (event->endpoint_event) { 1040 case DWC3_DEPEVT_XFERCOMPLETE: 1041 dwc3_ep0_xfer_complete(dwc, event); 1042 break; 1043 1044 case DWC3_DEPEVT_XFERNOTREADY: 1045 dwc3_ep0_xfernotready(dwc, event); 1046 break; 1047 1048 case DWC3_DEPEVT_XFERINPROGRESS: 1049 case DWC3_DEPEVT_RXTXFIFOEVT: 1050 case DWC3_DEPEVT_STREAMEVT: 1051 case DWC3_DEPEVT_EPCMDCMPLT: 1052 break; 1053 } 1054 } 1055