1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/list.h> 19 #include <linux/dma-mapping.h> 20 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <linux/usb/composite.h> 24 25 #include "core.h" 26 #include "debug.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, 34 struct usb_ctrlrequest *ctrl); 35 36 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 37 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 38 { 39 struct dwc3_trb *trb; 40 struct dwc3 *dwc; 41 42 dwc = dep->dwc; 43 trb = &dwc->ep0_trb[dep->trb_enqueue]; 44 45 if (chain) 46 dep->trb_enqueue++; 47 48 trb->bpl = lower_32_bits(buf_dma); 49 trb->bph = upper_32_bits(buf_dma); 50 trb->size = len; 51 trb->ctrl = type; 52 53 trb->ctrl |= (DWC3_TRB_CTRL_HWO 54 | DWC3_TRB_CTRL_ISP_IMI); 55 56 if (chain) 57 trb->ctrl |= DWC3_TRB_CTRL_CHN; 58 else 59 trb->ctrl |= (DWC3_TRB_CTRL_IOC 60 | DWC3_TRB_CTRL_LST); 61 62 trace_dwc3_prepare_trb(dep, trb); 63 } 64 65 static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 66 { 67 struct dwc3_gadget_ep_cmd_params params; 68 struct dwc3 *dwc; 69 int ret; 70 71 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 72 return 0; 73 74 dwc = dep->dwc; 75 76 memset(¶ms, 0, sizeof(params)); 77 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 78 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 79 80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 81 if (ret < 0) 82 return ret; 83 84 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 85 86 return 0; 87 } 88 89 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 90 struct dwc3_request *req) 91 { 92 struct dwc3 *dwc = dep->dwc; 93 94 req->request.actual = 0; 95 req->request.status = -EINPROGRESS; 96 req->epnum = dep->number; 97 req->status = DWC3_REQUEST_STATUS_QUEUED; 98 99 list_add_tail(&req->list, &dep->pending_list); 100 101 /* 102 * Gadget driver might not be quick enough to queue a request 103 * before we get a Transfer Not Ready event on this endpoint. 104 * 105 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 106 * flag is set, it's telling us that as soon as Gadget queues the 107 * required request, we should kick the transfer here because the 108 * IRQ we were waiting for is long gone. 109 */ 110 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 111 unsigned int direction; 112 113 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 114 115 if (dwc->ep0state != EP0_DATA_PHASE) { 116 dev_WARN(dwc->dev, "Unexpected pending request\n"); 117 return 0; 118 } 119 120 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 121 122 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 123 DWC3_EP0_DIR_IN); 124 125 return 0; 126 } 127 128 /* 129 * In case gadget driver asked us to delay the STATUS phase, 130 * handle it here. 131 */ 132 if (dwc->delayed_status) { 133 unsigned int direction; 134 135 direction = !dwc->ep0_expect_in; 136 dwc->delayed_status = false; 137 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); 138 139 if (dwc->ep0state == EP0_STATUS_PHASE) 140 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 141 142 return 0; 143 } 144 145 /* 146 * Unfortunately we have uncovered a limitation wrt the Data Phase. 147 * 148 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 149 * come before issuing Start Transfer command, but if we do, we will 150 * miss situations where the host starts another SETUP phase instead of 151 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 152 * Layer Compliance Suite. 153 * 154 * The problem surfaces due to the fact that in case of back-to-back 155 * SETUP packets there will be no XferNotReady(DATA) generated and we 156 * will be stuck waiting for XferNotReady(DATA) forever. 157 * 158 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 159 * it tells us to start Data Phase right away. It also mentions that if 160 * we receive a SETUP phase instead of the DATA phase, core will issue 161 * XferComplete for the DATA phase, before actually initiating it in 162 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 163 * can only be used to print some debugging logs, as the core expects 164 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 165 * just so it completes right away, without transferring anything and, 166 * only then, we can go back to the SETUP phase. 167 * 168 * Because of this scenario, SNPS decided to change the programming 169 * model of control transfers and support on-demand transfers only for 170 * the STATUS phase. To fix the issue we have now, we will always wait 171 * for gadget driver to queue the DATA phase's struct usb_request, then 172 * start it right away. 173 * 174 * If we're actually in a 2-stage transfer, we will wait for 175 * XferNotReady(STATUS). 176 */ 177 if (dwc->three_stage_setup) { 178 unsigned int direction; 179 180 direction = dwc->ep0_expect_in; 181 dwc->ep0state = EP0_DATA_PHASE; 182 183 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 184 185 dep->flags &= ~DWC3_EP0_DIR_IN; 186 } 187 188 return 0; 189 } 190 191 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 192 gfp_t gfp_flags) 193 { 194 struct dwc3_request *req = to_dwc3_request(request); 195 struct dwc3_ep *dep = to_dwc3_ep(ep); 196 struct dwc3 *dwc = dep->dwc; 197 198 unsigned long flags; 199 200 int ret; 201 202 spin_lock_irqsave(&dwc->lock, flags); 203 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { 204 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 205 dep->name); 206 ret = -ESHUTDOWN; 207 goto out; 208 } 209 210 /* we share one TRB for ep0/1 */ 211 if (!list_empty(&dep->pending_list)) { 212 ret = -EBUSY; 213 goto out; 214 } 215 216 ret = __dwc3_gadget_ep0_queue(dep, req); 217 218 out: 219 spin_unlock_irqrestore(&dwc->lock, flags); 220 221 return ret; 222 } 223 224 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 225 { 226 struct dwc3_ep *dep; 227 228 /* reinitialize physical ep1 */ 229 dep = dwc->eps[1]; 230 dep->flags &= DWC3_EP_RESOURCE_ALLOCATED; 231 dep->flags |= DWC3_EP_ENABLED; 232 233 /* stall is always issued on EP0 */ 234 dep = dwc->eps[0]; 235 __dwc3_gadget_ep_set_halt(dep, 1, false); 236 dep->flags &= DWC3_EP_RESOURCE_ALLOCATED | DWC3_EP_TRANSFER_STARTED; 237 dep->flags |= DWC3_EP_ENABLED; 238 dwc->delayed_status = false; 239 240 if (!list_empty(&dep->pending_list)) { 241 struct dwc3_request *req; 242 243 req = next_request(&dep->pending_list); 244 if (!dwc->connected) 245 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 246 else 247 dwc3_gadget_giveback(dep, req, -ECONNRESET); 248 } 249 250 dwc->eps[0]->trb_enqueue = 0; 251 dwc->eps[1]->trb_enqueue = 0; 252 dwc->ep0state = EP0_SETUP_PHASE; 253 dwc3_ep0_out_start(dwc); 254 } 255 256 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 257 { 258 struct dwc3_ep *dep = to_dwc3_ep(ep); 259 struct dwc3 *dwc = dep->dwc; 260 261 dwc3_ep0_stall_and_restart(dwc); 262 263 return 0; 264 } 265 266 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 267 { 268 struct dwc3_ep *dep = to_dwc3_ep(ep); 269 struct dwc3 *dwc = dep->dwc; 270 unsigned long flags; 271 int ret; 272 273 spin_lock_irqsave(&dwc->lock, flags); 274 ret = __dwc3_gadget_ep0_set_halt(ep, value); 275 spin_unlock_irqrestore(&dwc->lock, flags); 276 277 return ret; 278 } 279 280 void dwc3_ep0_out_start(struct dwc3 *dwc) 281 { 282 struct dwc3_ep *dep; 283 int ret; 284 int i; 285 286 complete(&dwc->ep0_in_setup); 287 288 dep = dwc->eps[0]; 289 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 290 DWC3_TRBCTL_CONTROL_SETUP, false); 291 ret = dwc3_ep0_start_trans(dep); 292 if (ret < 0) 293 dev_err(dwc->dev, "ep0 out start transfer failed: %d\n", ret); 294 295 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) { 296 struct dwc3_ep *dwc3_ep; 297 298 dwc3_ep = dwc->eps[i]; 299 if (!dwc3_ep) 300 continue; 301 302 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP)) 303 continue; 304 305 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP; 306 if (dwc->connected) 307 dwc3_stop_active_transfer(dwc3_ep, true, true); 308 else 309 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN); 310 } 311 } 312 313 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 314 { 315 struct dwc3_ep *dep; 316 u32 windex = le16_to_cpu(wIndex_le); 317 u32 epnum; 318 319 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 320 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 321 epnum |= 1; 322 323 dep = dwc->eps[epnum]; 324 if (dep == NULL) 325 return NULL; 326 327 if (dep->flags & DWC3_EP_ENABLED) 328 return dep; 329 330 return NULL; 331 } 332 333 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 334 { 335 } 336 /* 337 * ch 9.4.5 338 */ 339 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 340 struct usb_ctrlrequest *ctrl) 341 { 342 struct dwc3_ep *dep; 343 u32 recip; 344 u32 value; 345 u32 reg; 346 u16 usb_status = 0; 347 __le16 *response_pkt; 348 349 /* We don't support PTM_STATUS */ 350 value = le16_to_cpu(ctrl->wValue); 351 if (value != 0) 352 return -EINVAL; 353 354 recip = ctrl->bRequestType & USB_RECIP_MASK; 355 switch (recip) { 356 case USB_RECIP_DEVICE: 357 /* 358 * LTM will be set once we know how to set this in HW. 359 */ 360 usb_status |= dwc->gadget->is_selfpowered; 361 362 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 363 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 364 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 365 if (reg & DWC3_DCTL_INITU1ENA) 366 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 367 if (reg & DWC3_DCTL_INITU2ENA) 368 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 369 } else { 370 usb_status |= dwc->gadget->wakeup_armed << 371 USB_DEVICE_REMOTE_WAKEUP; 372 } 373 374 break; 375 376 case USB_RECIP_INTERFACE: 377 /* 378 * Function Remote Wake Capable D0 379 * Function Remote Wakeup D1 380 */ 381 return dwc3_ep0_delegate_req(dwc, ctrl); 382 383 case USB_RECIP_ENDPOINT: 384 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 385 if (!dep) 386 return -EINVAL; 387 388 if (dep->flags & DWC3_EP_STALL) 389 usb_status = 1 << USB_ENDPOINT_HALT; 390 break; 391 default: 392 return -EINVAL; 393 } 394 395 response_pkt = (__le16 *) dwc->setup_buf; 396 *response_pkt = cpu_to_le16(usb_status); 397 398 dep = dwc->eps[0]; 399 dwc->ep0_usb_req.dep = dep; 400 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 401 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 402 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 403 404 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 405 } 406 407 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 408 int set) 409 { 410 u32 reg; 411 412 if (state != USB_STATE_CONFIGURED) 413 return -EINVAL; 414 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 415 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 416 return -EINVAL; 417 if (set && dwc->dis_u1_entry_quirk) 418 return -EINVAL; 419 420 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 421 if (set) 422 reg |= DWC3_DCTL_INITU1ENA; 423 else 424 reg &= ~DWC3_DCTL_INITU1ENA; 425 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 426 427 return 0; 428 } 429 430 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 431 int set) 432 { 433 u32 reg; 434 435 436 if (state != USB_STATE_CONFIGURED) 437 return -EINVAL; 438 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 439 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 440 return -EINVAL; 441 if (set && dwc->dis_u2_entry_quirk) 442 return -EINVAL; 443 444 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 445 if (set) 446 reg |= DWC3_DCTL_INITU2ENA; 447 else 448 reg &= ~DWC3_DCTL_INITU2ENA; 449 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 450 451 return 0; 452 } 453 454 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 455 u32 wIndex, int set) 456 { 457 if ((wIndex & 0xff) != 0) 458 return -EINVAL; 459 if (!set) 460 return -EINVAL; 461 462 switch (wIndex >> 8) { 463 case USB_TEST_J: 464 case USB_TEST_K: 465 case USB_TEST_SE0_NAK: 466 case USB_TEST_PACKET: 467 case USB_TEST_FORCE_ENABLE: 468 dwc->test_mode_nr = wIndex >> 8; 469 dwc->test_mode = true; 470 break; 471 default: 472 return -EINVAL; 473 } 474 475 return 0; 476 } 477 478 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 479 struct usb_ctrlrequest *ctrl, int set) 480 { 481 enum usb_device_state state; 482 u32 wValue; 483 u32 wIndex; 484 int ret = 0; 485 486 wValue = le16_to_cpu(ctrl->wValue); 487 wIndex = le16_to_cpu(ctrl->wIndex); 488 state = dwc->gadget->state; 489 490 switch (wValue) { 491 case USB_DEVICE_REMOTE_WAKEUP: 492 if (dwc->wakeup_configured) 493 dwc->gadget->wakeup_armed = set; 494 else 495 ret = -EINVAL; 496 break; 497 /* 498 * 9.4.1 says only for SS, in AddressState only for 499 * default control pipe 500 */ 501 case USB_DEVICE_U1_ENABLE: 502 ret = dwc3_ep0_handle_u1(dwc, state, set); 503 break; 504 case USB_DEVICE_U2_ENABLE: 505 ret = dwc3_ep0_handle_u2(dwc, state, set); 506 break; 507 case USB_DEVICE_LTM_ENABLE: 508 ret = -EINVAL; 509 break; 510 case USB_DEVICE_TEST_MODE: 511 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 512 break; 513 default: 514 ret = -EINVAL; 515 } 516 517 return ret; 518 } 519 520 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 521 struct usb_ctrlrequest *ctrl, int set) 522 { 523 u32 wValue; 524 int ret = 0; 525 526 wValue = le16_to_cpu(ctrl->wValue); 527 528 switch (wValue) { 529 case USB_INTRF_FUNC_SUSPEND: 530 ret = dwc3_ep0_delegate_req(dwc, ctrl); 531 break; 532 default: 533 ret = -EINVAL; 534 } 535 536 return ret; 537 } 538 539 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 540 struct usb_ctrlrequest *ctrl, int set) 541 { 542 struct dwc3_ep *dep; 543 u32 wValue; 544 int ret; 545 546 wValue = le16_to_cpu(ctrl->wValue); 547 548 switch (wValue) { 549 case USB_ENDPOINT_HALT: 550 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 551 if (!dep) 552 return -EINVAL; 553 554 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 555 break; 556 557 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 558 if (ret) 559 return -EINVAL; 560 561 /* ClearFeature(Halt) may need delayed status */ 562 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) 563 return USB_GADGET_DELAYED_STATUS; 564 565 break; 566 default: 567 return -EINVAL; 568 } 569 570 return 0; 571 } 572 573 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 574 struct usb_ctrlrequest *ctrl, int set) 575 { 576 u32 recip; 577 int ret; 578 579 recip = ctrl->bRequestType & USB_RECIP_MASK; 580 581 switch (recip) { 582 case USB_RECIP_DEVICE: 583 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 584 break; 585 case USB_RECIP_INTERFACE: 586 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 587 break; 588 case USB_RECIP_ENDPOINT: 589 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 590 break; 591 default: 592 ret = -EINVAL; 593 } 594 595 return ret; 596 } 597 598 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 599 { 600 enum usb_device_state state = dwc->gadget->state; 601 u32 addr; 602 u32 reg; 603 604 addr = le16_to_cpu(ctrl->wValue); 605 if (addr > 127) { 606 dev_err(dwc->dev, "invalid device address %d\n", addr); 607 return -EINVAL; 608 } 609 610 if (state == USB_STATE_CONFIGURED) { 611 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 612 return -EINVAL; 613 } 614 615 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 616 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 617 reg |= DWC3_DCFG_DEVADDR(addr); 618 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 619 620 if (addr) 621 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); 622 else 623 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); 624 625 return 0; 626 } 627 628 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 629 { 630 int ret = -EINVAL; 631 632 if (dwc->async_callbacks) { 633 spin_unlock(&dwc->lock); 634 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); 635 spin_lock(&dwc->lock); 636 } 637 return ret; 638 } 639 640 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 641 { 642 enum usb_device_state state = dwc->gadget->state; 643 u32 cfg; 644 int ret; 645 u32 reg; 646 647 cfg = le16_to_cpu(ctrl->wValue); 648 649 switch (state) { 650 case USB_STATE_DEFAULT: 651 return -EINVAL; 652 653 case USB_STATE_ADDRESS: 654 dwc3_gadget_start_config(dwc, 2); 655 dwc3_gadget_clear_tx_fifos(dwc); 656 657 ret = dwc3_ep0_delegate_req(dwc, ctrl); 658 /* if the cfg matches and the cfg is non zero */ 659 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 660 661 /* 662 * only change state if set_config has already 663 * been processed. If gadget driver returns 664 * USB_GADGET_DELAYED_STATUS, we will wait 665 * to change the state on the next usb_ep_queue() 666 */ 667 if (ret == 0) 668 usb_gadget_set_state(dwc->gadget, 669 USB_STATE_CONFIGURED); 670 671 /* 672 * Enable transition to U1/U2 state when 673 * nothing is pending from application. 674 */ 675 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 676 if (!dwc->dis_u1_entry_quirk) 677 reg |= DWC3_DCTL_ACCEPTU1ENA; 678 if (!dwc->dis_u2_entry_quirk) 679 reg |= DWC3_DCTL_ACCEPTU2ENA; 680 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 681 } 682 break; 683 684 case USB_STATE_CONFIGURED: 685 ret = dwc3_ep0_delegate_req(dwc, ctrl); 686 if (!cfg && !ret) 687 usb_gadget_set_state(dwc->gadget, 688 USB_STATE_ADDRESS); 689 break; 690 default: 691 ret = -EINVAL; 692 } 693 return ret; 694 } 695 696 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 697 { 698 struct dwc3_ep *dep = to_dwc3_ep(ep); 699 struct dwc3 *dwc = dep->dwc; 700 701 u32 param = 0; 702 u32 reg; 703 704 struct timing { 705 u8 u1sel; 706 u8 u1pel; 707 __le16 u2sel; 708 __le16 u2pel; 709 } __packed timing; 710 711 int ret; 712 713 memcpy(&timing, req->buf, sizeof(timing)); 714 715 dwc->u1sel = timing.u1sel; 716 dwc->u1pel = timing.u1pel; 717 dwc->u2sel = le16_to_cpu(timing.u2sel); 718 dwc->u2pel = le16_to_cpu(timing.u2pel); 719 720 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 721 if (reg & DWC3_DCTL_INITU2ENA) 722 param = dwc->u2pel; 723 if (reg & DWC3_DCTL_INITU1ENA) 724 param = dwc->u1pel; 725 726 /* 727 * According to Synopsys Databook, if parameter is 728 * greater than 125, a value of zero should be 729 * programmed in the register. 730 */ 731 if (param > 125) 732 param = 0; 733 734 /* now that we have the time, issue DGCMD Set Sel */ 735 ret = dwc3_send_gadget_generic_command(dwc, 736 DWC3_DGCMD_SET_PERIODIC_PAR, param); 737 WARN_ON(ret < 0); 738 } 739 740 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 741 { 742 struct dwc3_ep *dep; 743 enum usb_device_state state = dwc->gadget->state; 744 u16 wLength; 745 746 if (state == USB_STATE_DEFAULT) 747 return -EINVAL; 748 749 wLength = le16_to_cpu(ctrl->wLength); 750 751 if (wLength != 6) { 752 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 753 wLength); 754 return -EINVAL; 755 } 756 757 /* 758 * To handle Set SEL we need to receive 6 bytes from Host. So let's 759 * queue a usb_request for 6 bytes. 760 * 761 * Remember, though, this controller can't handle non-wMaxPacketSize 762 * aligned transfers on the OUT direction, so we queue a request for 763 * wMaxPacketSize instead. 764 */ 765 dep = dwc->eps[0]; 766 dwc->ep0_usb_req.dep = dep; 767 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 768 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 769 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 770 771 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 772 } 773 774 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 775 { 776 u16 wLength; 777 u16 wValue; 778 u16 wIndex; 779 780 wValue = le16_to_cpu(ctrl->wValue); 781 wLength = le16_to_cpu(ctrl->wLength); 782 wIndex = le16_to_cpu(ctrl->wIndex); 783 784 if (wIndex || wLength) 785 return -EINVAL; 786 787 dwc->gadget->isoch_delay = wValue; 788 789 return 0; 790 } 791 792 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 793 { 794 int ret; 795 796 switch (ctrl->bRequest) { 797 case USB_REQ_GET_STATUS: 798 ret = dwc3_ep0_handle_status(dwc, ctrl); 799 break; 800 case USB_REQ_CLEAR_FEATURE: 801 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 802 break; 803 case USB_REQ_SET_FEATURE: 804 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 805 break; 806 case USB_REQ_SET_ADDRESS: 807 ret = dwc3_ep0_set_address(dwc, ctrl); 808 break; 809 case USB_REQ_SET_CONFIGURATION: 810 ret = dwc3_ep0_set_config(dwc, ctrl); 811 break; 812 case USB_REQ_SET_SEL: 813 ret = dwc3_ep0_set_sel(dwc, ctrl); 814 break; 815 case USB_REQ_SET_ISOCH_DELAY: 816 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 817 break; 818 default: 819 ret = dwc3_ep0_delegate_req(dwc, ctrl); 820 break; 821 } 822 823 return ret; 824 } 825 826 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 827 const struct dwc3_event_depevt *event) 828 { 829 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 830 int ret = -EINVAL; 831 u32 len; 832 833 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected) 834 goto out; 835 836 trace_dwc3_ctrl_req(ctrl); 837 838 len = le16_to_cpu(ctrl->wLength); 839 if (!len) { 840 dwc->three_stage_setup = false; 841 dwc->ep0_expect_in = false; 842 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 843 } else { 844 dwc->three_stage_setup = true; 845 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 846 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 847 } 848 849 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 850 ret = dwc3_ep0_std_request(dwc, ctrl); 851 else 852 ret = dwc3_ep0_delegate_req(dwc, ctrl); 853 854 if (ret == USB_GADGET_DELAYED_STATUS) 855 dwc->delayed_status = true; 856 857 out: 858 if (ret < 0) 859 dwc3_ep0_stall_and_restart(dwc); 860 } 861 862 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 863 const struct dwc3_event_depevt *event) 864 { 865 struct dwc3_request *r; 866 struct usb_request *ur; 867 struct dwc3_trb *trb; 868 struct dwc3_ep *ep0; 869 u32 transferred = 0; 870 u32 status; 871 u32 length; 872 u8 epnum; 873 874 epnum = event->endpoint_number; 875 ep0 = dwc->eps[0]; 876 877 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 878 trb = dwc->ep0_trb; 879 trace_dwc3_complete_trb(ep0, trb); 880 881 r = next_request(&ep0->pending_list); 882 if (!r) 883 return; 884 885 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 886 if (status == DWC3_TRBSTS_SETUP_PENDING) { 887 dwc->setup_packet_pending = true; 888 if (r) 889 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 890 891 return; 892 } 893 894 ur = &r->request; 895 896 length = trb->size & DWC3_TRB_SIZE_MASK; 897 transferred = ur->length - length; 898 ur->actual += transferred; 899 900 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 901 ur->length && ur->zero) || dwc->ep0_bounced) { 902 trb++; 903 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 904 trace_dwc3_complete_trb(ep0, trb); 905 906 if (r->direction) 907 dwc->eps[1]->trb_enqueue = 0; 908 else 909 dwc->eps[0]->trb_enqueue = 0; 910 911 dwc->ep0_bounced = false; 912 } 913 914 if ((epnum & 1) && ur->actual < ur->length) 915 dwc3_ep0_stall_and_restart(dwc); 916 else 917 dwc3_gadget_giveback(ep0, r, 0); 918 } 919 920 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 921 const struct dwc3_event_depevt *event) 922 { 923 struct dwc3_request *r; 924 struct dwc3_ep *dep; 925 struct dwc3_trb *trb; 926 u32 status; 927 928 dep = dwc->eps[0]; 929 trb = dwc->ep0_trb; 930 931 trace_dwc3_complete_trb(dep, trb); 932 933 if (!list_empty(&dep->pending_list)) { 934 r = next_request(&dep->pending_list); 935 936 dwc3_gadget_giveback(dep, r, 0); 937 } 938 939 if (dwc->test_mode) { 940 int ret; 941 942 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 943 if (ret < 0) { 944 dev_err(dwc->dev, "invalid test #%d\n", 945 dwc->test_mode_nr); 946 dwc3_ep0_stall_and_restart(dwc); 947 return; 948 } 949 } 950 951 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 952 if (status == DWC3_TRBSTS_SETUP_PENDING) 953 dwc->setup_packet_pending = true; 954 955 dwc->ep0state = EP0_SETUP_PHASE; 956 dwc3_ep0_out_start(dwc); 957 } 958 959 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 960 const struct dwc3_event_depevt *event) 961 { 962 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 963 964 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 965 dep->resource_index = 0; 966 dwc->setup_packet_pending = false; 967 968 switch (dwc->ep0state) { 969 case EP0_SETUP_PHASE: 970 dwc3_ep0_inspect_setup(dwc, event); 971 break; 972 973 case EP0_DATA_PHASE: 974 dwc3_ep0_complete_data(dwc, event); 975 break; 976 977 case EP0_STATUS_PHASE: 978 dwc3_ep0_complete_status(dwc, event); 979 break; 980 default: 981 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 982 } 983 } 984 985 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 986 struct dwc3_ep *dep, struct dwc3_request *req) 987 { 988 unsigned int trb_length = 0; 989 int ret; 990 991 req->direction = !!dep->number; 992 993 if (req->request.length == 0) { 994 if (!req->direction) 995 trb_length = dep->endpoint.maxpacket; 996 997 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, 998 DWC3_TRBCTL_CONTROL_DATA, false); 999 ret = dwc3_ep0_start_trans(dep); 1000 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 1001 && (dep->number == 0)) { 1002 u32 maxpacket; 1003 u32 rem; 1004 1005 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1006 &req->request, dep->number); 1007 if (ret) 1008 return; 1009 1010 maxpacket = dep->endpoint.maxpacket; 1011 rem = req->request.length % maxpacket; 1012 dwc->ep0_bounced = true; 1013 1014 /* prepare normal TRB */ 1015 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1016 req->request.length, 1017 DWC3_TRBCTL_CONTROL_DATA, 1018 true); 1019 1020 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1021 1022 /* Now prepare one extra TRB to align transfer size */ 1023 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1024 maxpacket - rem, 1025 DWC3_TRBCTL_CONTROL_DATA, 1026 false); 1027 ret = dwc3_ep0_start_trans(dep); 1028 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 1029 req->request.length && req->request.zero) { 1030 1031 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1032 &req->request, dep->number); 1033 if (ret) 1034 return; 1035 1036 /* prepare normal TRB */ 1037 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1038 req->request.length, 1039 DWC3_TRBCTL_CONTROL_DATA, 1040 true); 1041 1042 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1043 1044 if (!req->direction) 1045 trb_length = dep->endpoint.maxpacket; 1046 1047 /* Now prepare one extra TRB to align transfer size */ 1048 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1049 trb_length, DWC3_TRBCTL_CONTROL_DATA, 1050 false); 1051 ret = dwc3_ep0_start_trans(dep); 1052 } else { 1053 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1054 &req->request, dep->number); 1055 if (ret) 1056 return; 1057 1058 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1059 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1060 false); 1061 1062 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1063 1064 ret = dwc3_ep0_start_trans(dep); 1065 } 1066 1067 if (ret < 0) 1068 dev_err(dwc->dev, 1069 "ep0 data phase start transfer failed: %d\n", ret); 1070 } 1071 1072 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1073 { 1074 struct dwc3 *dwc = dep->dwc; 1075 u32 type; 1076 1077 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1078 : DWC3_TRBCTL_CONTROL_STATUS2; 1079 1080 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1081 return dwc3_ep0_start_trans(dep); 1082 } 1083 1084 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1085 { 1086 int ret; 1087 1088 ret = dwc3_ep0_start_control_status(dep); 1089 if (ret) 1090 dev_err(dwc->dev, 1091 "ep0 status phase start transfer failed: %d\n", ret); 1092 } 1093 1094 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1095 const struct dwc3_event_depevt *event) 1096 { 1097 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1098 1099 __dwc3_ep0_do_control_status(dwc, dep); 1100 } 1101 1102 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) 1103 { 1104 unsigned int direction = !dwc->ep0_expect_in; 1105 1106 dwc->delayed_status = false; 1107 dwc->clear_stall_protocol = 0; 1108 1109 if (dwc->ep0state != EP0_STATUS_PHASE) 1110 return; 1111 1112 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 1113 } 1114 1115 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1116 { 1117 struct dwc3_gadget_ep_cmd_params params; 1118 u32 cmd; 1119 int ret; 1120 1121 /* 1122 * For status/DATA OUT stage, TRB will be queued on ep0 out 1123 * endpoint for which resource index is zero. Hence allow 1124 * queuing ENDXFER command for ep0 out endpoint. 1125 */ 1126 if (!dep->resource_index && dep->number) 1127 return; 1128 1129 cmd = DWC3_DEPCMD_ENDTRANSFER; 1130 cmd |= DWC3_DEPCMD_CMDIOC; 1131 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1132 memset(¶ms, 0, sizeof(params)); 1133 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1134 if (ret) 1135 dev_err_ratelimited(dwc->dev, 1136 "ep0 data phase end transfer failed: %d\n", ret); 1137 1138 dep->resource_index = 0; 1139 } 1140 1141 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1142 const struct dwc3_event_depevt *event) 1143 { 1144 switch (event->status) { 1145 case DEPEVT_STATUS_CONTROL_DATA: 1146 if (!dwc->softconnect || !dwc->connected) 1147 return; 1148 /* 1149 * We already have a DATA transfer in the controller's cache, 1150 * if we receive a XferNotReady(DATA) we will ignore it, unless 1151 * it's for the wrong direction. 1152 * 1153 * In that case, we must issue END_TRANSFER command to the Data 1154 * Phase we already have started and issue SetStall on the 1155 * control endpoint. 1156 */ 1157 if (dwc->ep0_expect_in != event->endpoint_number) { 1158 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1159 1160 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1161 dwc3_ep0_end_control_data(dwc, dep); 1162 dwc3_ep0_stall_and_restart(dwc); 1163 return; 1164 } 1165 1166 break; 1167 1168 case DEPEVT_STATUS_CONTROL_STATUS: 1169 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1170 return; 1171 1172 if (dwc->setup_packet_pending) { 1173 dwc3_ep0_stall_and_restart(dwc); 1174 return; 1175 } 1176 1177 dwc->ep0state = EP0_STATUS_PHASE; 1178 1179 if (dwc->delayed_status) { 1180 struct dwc3_ep *dep = dwc->eps[0]; 1181 1182 WARN_ON_ONCE(event->endpoint_number != 1); 1183 /* 1184 * We should handle the delay STATUS phase here if the 1185 * request for handling delay STATUS has been queued 1186 * into the list. 1187 */ 1188 if (!list_empty(&dep->pending_list)) { 1189 dwc->delayed_status = false; 1190 usb_gadget_set_state(dwc->gadget, 1191 USB_STATE_CONFIGURED); 1192 dwc3_ep0_do_control_status(dwc, event); 1193 } 1194 1195 return; 1196 } 1197 1198 dwc3_ep0_do_control_status(dwc, event); 1199 } 1200 } 1201 1202 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1203 const struct dwc3_event_depevt *event) 1204 { 1205 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1206 u8 cmd; 1207 1208 switch (event->endpoint_event) { 1209 case DWC3_DEPEVT_XFERCOMPLETE: 1210 dwc3_ep0_xfer_complete(dwc, event); 1211 break; 1212 1213 case DWC3_DEPEVT_XFERNOTREADY: 1214 dwc3_ep0_xfernotready(dwc, event); 1215 break; 1216 1217 case DWC3_DEPEVT_XFERINPROGRESS: 1218 case DWC3_DEPEVT_RXTXFIFOEVT: 1219 case DWC3_DEPEVT_STREAMEVT: 1220 break; 1221 case DWC3_DEPEVT_EPCMDCMPLT: 1222 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 1223 1224 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 1225 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; 1226 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 1227 } 1228 break; 1229 default: 1230 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event); 1231 break; 1232 } 1233 } 1234