1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 of 12 * the License as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/list.h> 28 #include <linux/dma-mapping.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/composite.h> 33 34 #include "core.h" 35 #include "debug.h" 36 #include "gadget.h" 37 #include "io.h" 38 39 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 40 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 41 struct dwc3_ep *dep, struct dwc3_request *req); 42 43 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 44 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 45 { 46 struct dwc3_trb *trb; 47 struct dwc3 *dwc; 48 49 dwc = dep->dwc; 50 trb = &dwc->ep0_trb[dep->trb_enqueue]; 51 52 if (chain) 53 dep->trb_enqueue++; 54 55 trb->bpl = lower_32_bits(buf_dma); 56 trb->bph = upper_32_bits(buf_dma); 57 trb->size = len; 58 trb->ctrl = type; 59 60 trb->ctrl |= (DWC3_TRB_CTRL_HWO 61 | DWC3_TRB_CTRL_ISP_IMI); 62 63 if (chain) 64 trb->ctrl |= DWC3_TRB_CTRL_CHN; 65 else 66 trb->ctrl |= (DWC3_TRB_CTRL_IOC 67 | DWC3_TRB_CTRL_LST); 68 69 trace_dwc3_prepare_trb(dep, trb); 70 } 71 72 static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 73 { 74 struct dwc3_gadget_ep_cmd_params params; 75 struct dwc3 *dwc; 76 int ret; 77 78 if (dep->flags & DWC3_EP_BUSY) 79 return 0; 80 81 dwc = dep->dwc; 82 83 memset(¶ms, 0, sizeof(params)); 84 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 85 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 86 87 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 88 if (ret < 0) 89 return ret; 90 91 dep->flags |= DWC3_EP_BUSY; 92 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); 93 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 94 95 return 0; 96 } 97 98 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 99 struct dwc3_request *req) 100 { 101 struct dwc3 *dwc = dep->dwc; 102 103 req->request.actual = 0; 104 req->request.status = -EINPROGRESS; 105 req->epnum = dep->number; 106 107 list_add_tail(&req->list, &dep->pending_list); 108 109 /* 110 * Gadget driver might not be quick enough to queue a request 111 * before we get a Transfer Not Ready event on this endpoint. 112 * 113 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 114 * flag is set, it's telling us that as soon as Gadget queues the 115 * required request, we should kick the transfer here because the 116 * IRQ we were waiting for is long gone. 117 */ 118 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 119 unsigned direction; 120 121 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 122 123 if (dwc->ep0state != EP0_DATA_PHASE) { 124 dev_WARN(dwc->dev, "Unexpected pending request\n"); 125 return 0; 126 } 127 128 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 129 130 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 131 DWC3_EP0_DIR_IN); 132 133 return 0; 134 } 135 136 /* 137 * In case gadget driver asked us to delay the STATUS phase, 138 * handle it here. 139 */ 140 if (dwc->delayed_status) { 141 unsigned direction; 142 143 direction = !dwc->ep0_expect_in; 144 dwc->delayed_status = false; 145 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 146 147 if (dwc->ep0state == EP0_STATUS_PHASE) 148 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 149 150 return 0; 151 } 152 153 /* 154 * Unfortunately we have uncovered a limitation wrt the Data Phase. 155 * 156 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 157 * come before issueing Start Transfer command, but if we do, we will 158 * miss situations where the host starts another SETUP phase instead of 159 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 160 * Layer Compliance Suite. 161 * 162 * The problem surfaces due to the fact that in case of back-to-back 163 * SETUP packets there will be no XferNotReady(DATA) generated and we 164 * will be stuck waiting for XferNotReady(DATA) forever. 165 * 166 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 167 * it tells us to start Data Phase right away. It also mentions that if 168 * we receive a SETUP phase instead of the DATA phase, core will issue 169 * XferComplete for the DATA phase, before actually initiating it in 170 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 171 * can only be used to print some debugging logs, as the core expects 172 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 173 * just so it completes right away, without transferring anything and, 174 * only then, we can go back to the SETUP phase. 175 * 176 * Because of this scenario, SNPS decided to change the programming 177 * model of control transfers and support on-demand transfers only for 178 * the STATUS phase. To fix the issue we have now, we will always wait 179 * for gadget driver to queue the DATA phase's struct usb_request, then 180 * start it right away. 181 * 182 * If we're actually in a 2-stage transfer, we will wait for 183 * XferNotReady(STATUS). 184 */ 185 if (dwc->three_stage_setup) { 186 unsigned direction; 187 188 direction = dwc->ep0_expect_in; 189 dwc->ep0state = EP0_DATA_PHASE; 190 191 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 192 193 dep->flags &= ~DWC3_EP0_DIR_IN; 194 } 195 196 return 0; 197 } 198 199 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 200 gfp_t gfp_flags) 201 { 202 struct dwc3_request *req = to_dwc3_request(request); 203 struct dwc3_ep *dep = to_dwc3_ep(ep); 204 struct dwc3 *dwc = dep->dwc; 205 206 unsigned long flags; 207 208 int ret; 209 210 spin_lock_irqsave(&dwc->lock, flags); 211 if (!dep->endpoint.desc) { 212 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 213 dep->name); 214 ret = -ESHUTDOWN; 215 goto out; 216 } 217 218 /* we share one TRB for ep0/1 */ 219 if (!list_empty(&dep->pending_list)) { 220 ret = -EBUSY; 221 goto out; 222 } 223 224 ret = __dwc3_gadget_ep0_queue(dep, req); 225 226 out: 227 spin_unlock_irqrestore(&dwc->lock, flags); 228 229 return ret; 230 } 231 232 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 233 { 234 struct dwc3_ep *dep; 235 236 /* reinitialize physical ep1 */ 237 dep = dwc->eps[1]; 238 dep->flags = DWC3_EP_ENABLED; 239 240 /* stall is always issued on EP0 */ 241 dep = dwc->eps[0]; 242 __dwc3_gadget_ep_set_halt(dep, 1, false); 243 dep->flags = DWC3_EP_ENABLED; 244 dwc->delayed_status = false; 245 246 if (!list_empty(&dep->pending_list)) { 247 struct dwc3_request *req; 248 249 req = next_request(&dep->pending_list); 250 dwc3_gadget_giveback(dep, req, -ECONNRESET); 251 } 252 253 dwc->ep0state = EP0_SETUP_PHASE; 254 dwc3_ep0_out_start(dwc); 255 } 256 257 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 258 { 259 struct dwc3_ep *dep = to_dwc3_ep(ep); 260 struct dwc3 *dwc = dep->dwc; 261 262 dwc3_ep0_stall_and_restart(dwc); 263 264 return 0; 265 } 266 267 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 268 { 269 struct dwc3_ep *dep = to_dwc3_ep(ep); 270 struct dwc3 *dwc = dep->dwc; 271 unsigned long flags; 272 int ret; 273 274 spin_lock_irqsave(&dwc->lock, flags); 275 ret = __dwc3_gadget_ep0_set_halt(ep, value); 276 spin_unlock_irqrestore(&dwc->lock, flags); 277 278 return ret; 279 } 280 281 void dwc3_ep0_out_start(struct dwc3 *dwc) 282 { 283 struct dwc3_ep *dep; 284 int ret; 285 286 complete(&dwc->ep0_in_setup); 287 288 dep = dwc->eps[0]; 289 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 290 DWC3_TRBCTL_CONTROL_SETUP, false); 291 ret = dwc3_ep0_start_trans(dep); 292 WARN_ON(ret < 0); 293 } 294 295 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 296 { 297 struct dwc3_ep *dep; 298 u32 windex = le16_to_cpu(wIndex_le); 299 u32 epnum; 300 301 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 302 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 303 epnum |= 1; 304 305 dep = dwc->eps[epnum]; 306 if (dep->flags & DWC3_EP_ENABLED) 307 return dep; 308 309 return NULL; 310 } 311 312 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 313 { 314 } 315 /* 316 * ch 9.4.5 317 */ 318 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 319 struct usb_ctrlrequest *ctrl) 320 { 321 struct dwc3_ep *dep; 322 u32 recip; 323 u32 value; 324 u32 reg; 325 u16 usb_status = 0; 326 __le16 *response_pkt; 327 328 /* We don't support PTM_STATUS */ 329 value = le16_to_cpu(ctrl->wValue); 330 if (value != 0) 331 return -EINVAL; 332 333 recip = ctrl->bRequestType & USB_RECIP_MASK; 334 switch (recip) { 335 case USB_RECIP_DEVICE: 336 /* 337 * LTM will be set once we know how to set this in HW. 338 */ 339 usb_status |= dwc->gadget.is_selfpowered; 340 341 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 342 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 343 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 344 if (reg & DWC3_DCTL_INITU1ENA) 345 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 346 if (reg & DWC3_DCTL_INITU2ENA) 347 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 348 } 349 350 break; 351 352 case USB_RECIP_INTERFACE: 353 /* 354 * Function Remote Wake Capable D0 355 * Function Remote Wakeup D1 356 */ 357 break; 358 359 case USB_RECIP_ENDPOINT: 360 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 361 if (!dep) 362 return -EINVAL; 363 364 if (dep->flags & DWC3_EP_STALL) 365 usb_status = 1 << USB_ENDPOINT_HALT; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 response_pkt = (__le16 *) dwc->setup_buf; 372 *response_pkt = cpu_to_le16(usb_status); 373 374 dep = dwc->eps[0]; 375 dwc->ep0_usb_req.dep = dep; 376 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 377 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 378 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 379 380 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 381 } 382 383 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 384 int set) 385 { 386 u32 reg; 387 388 if (state != USB_STATE_CONFIGURED) 389 return -EINVAL; 390 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 391 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 392 return -EINVAL; 393 394 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 395 if (set) 396 reg |= DWC3_DCTL_INITU1ENA; 397 else 398 reg &= ~DWC3_DCTL_INITU1ENA; 399 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 400 401 return 0; 402 } 403 404 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 405 int set) 406 { 407 u32 reg; 408 409 410 if (state != USB_STATE_CONFIGURED) 411 return -EINVAL; 412 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 413 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 414 return -EINVAL; 415 416 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 417 if (set) 418 reg |= DWC3_DCTL_INITU2ENA; 419 else 420 reg &= ~DWC3_DCTL_INITU2ENA; 421 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 422 423 return 0; 424 } 425 426 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 427 u32 wIndex, int set) 428 { 429 if ((wIndex & 0xff) != 0) 430 return -EINVAL; 431 if (!set) 432 return -EINVAL; 433 434 switch (wIndex >> 8) { 435 case TEST_J: 436 case TEST_K: 437 case TEST_SE0_NAK: 438 case TEST_PACKET: 439 case TEST_FORCE_EN: 440 dwc->test_mode_nr = wIndex >> 8; 441 dwc->test_mode = true; 442 break; 443 default: 444 return -EINVAL; 445 } 446 447 return 0; 448 } 449 450 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 451 struct usb_ctrlrequest *ctrl, int set) 452 { 453 enum usb_device_state state; 454 u32 wValue; 455 u32 wIndex; 456 int ret = 0; 457 458 wValue = le16_to_cpu(ctrl->wValue); 459 wIndex = le16_to_cpu(ctrl->wIndex); 460 state = dwc->gadget.state; 461 462 switch (wValue) { 463 case USB_DEVICE_REMOTE_WAKEUP: 464 break; 465 /* 466 * 9.4.1 says only only for SS, in AddressState only for 467 * default control pipe 468 */ 469 case USB_DEVICE_U1_ENABLE: 470 ret = dwc3_ep0_handle_u1(dwc, state, set); 471 break; 472 case USB_DEVICE_U2_ENABLE: 473 ret = dwc3_ep0_handle_u2(dwc, state, set); 474 break; 475 case USB_DEVICE_LTM_ENABLE: 476 ret = -EINVAL; 477 break; 478 case USB_DEVICE_TEST_MODE: 479 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 480 break; 481 default: 482 ret = -EINVAL; 483 } 484 485 return ret; 486 } 487 488 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 489 struct usb_ctrlrequest *ctrl, int set) 490 { 491 u32 wValue; 492 int ret = 0; 493 494 wValue = le16_to_cpu(ctrl->wValue); 495 496 switch (wValue) { 497 case USB_INTRF_FUNC_SUSPEND: 498 /* 499 * REVISIT: Ideally we would enable some low power mode here, 500 * however it's unclear what we should be doing here. 501 * 502 * For now, we're not doing anything, just making sure we return 503 * 0 so USB Command Verifier tests pass without any errors. 504 */ 505 break; 506 default: 507 ret = -EINVAL; 508 } 509 510 return ret; 511 } 512 513 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 514 struct usb_ctrlrequest *ctrl, int set) 515 { 516 struct dwc3_ep *dep; 517 u32 wValue; 518 int ret; 519 520 wValue = le16_to_cpu(ctrl->wValue); 521 522 switch (wValue) { 523 case USB_ENDPOINT_HALT: 524 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 525 if (!dep) 526 return -EINVAL; 527 528 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 529 break; 530 531 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 532 if (ret) 533 return -EINVAL; 534 break; 535 default: 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 543 struct usb_ctrlrequest *ctrl, int set) 544 { 545 u32 recip; 546 int ret; 547 548 recip = ctrl->bRequestType & USB_RECIP_MASK; 549 550 switch (recip) { 551 case USB_RECIP_DEVICE: 552 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 553 break; 554 case USB_RECIP_INTERFACE: 555 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 556 break; 557 case USB_RECIP_ENDPOINT: 558 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 559 break; 560 default: 561 ret = -EINVAL; 562 } 563 564 return ret; 565 } 566 567 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 568 { 569 enum usb_device_state state = dwc->gadget.state; 570 u32 addr; 571 u32 reg; 572 573 addr = le16_to_cpu(ctrl->wValue); 574 if (addr > 127) { 575 dev_err(dwc->dev, "invalid device address %d\n", addr); 576 return -EINVAL; 577 } 578 579 if (state == USB_STATE_CONFIGURED) { 580 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 581 return -EINVAL; 582 } 583 584 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 585 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 586 reg |= DWC3_DCFG_DEVADDR(addr); 587 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 588 589 if (addr) 590 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 591 else 592 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 593 594 return 0; 595 } 596 597 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 598 { 599 int ret; 600 601 spin_unlock(&dwc->lock); 602 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 603 spin_lock(&dwc->lock); 604 return ret; 605 } 606 607 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 608 { 609 enum usb_device_state state = dwc->gadget.state; 610 u32 cfg; 611 int ret; 612 u32 reg; 613 614 cfg = le16_to_cpu(ctrl->wValue); 615 616 switch (state) { 617 case USB_STATE_DEFAULT: 618 return -EINVAL; 619 620 case USB_STATE_ADDRESS: 621 ret = dwc3_ep0_delegate_req(dwc, ctrl); 622 /* if the cfg matches and the cfg is non zero */ 623 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 624 625 /* 626 * only change state if set_config has already 627 * been processed. If gadget driver returns 628 * USB_GADGET_DELAYED_STATUS, we will wait 629 * to change the state on the next usb_ep_queue() 630 */ 631 if (ret == 0) 632 usb_gadget_set_state(&dwc->gadget, 633 USB_STATE_CONFIGURED); 634 635 /* 636 * Enable transition to U1/U2 state when 637 * nothing is pending from application. 638 */ 639 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 640 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 641 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 642 } 643 break; 644 645 case USB_STATE_CONFIGURED: 646 ret = dwc3_ep0_delegate_req(dwc, ctrl); 647 if (!cfg && !ret) 648 usb_gadget_set_state(&dwc->gadget, 649 USB_STATE_ADDRESS); 650 break; 651 default: 652 ret = -EINVAL; 653 } 654 return ret; 655 } 656 657 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 658 { 659 struct dwc3_ep *dep = to_dwc3_ep(ep); 660 struct dwc3 *dwc = dep->dwc; 661 662 u32 param = 0; 663 u32 reg; 664 665 struct timing { 666 u8 u1sel; 667 u8 u1pel; 668 __le16 u2sel; 669 __le16 u2pel; 670 } __packed timing; 671 672 int ret; 673 674 memcpy(&timing, req->buf, sizeof(timing)); 675 676 dwc->u1sel = timing.u1sel; 677 dwc->u1pel = timing.u1pel; 678 dwc->u2sel = le16_to_cpu(timing.u2sel); 679 dwc->u2pel = le16_to_cpu(timing.u2pel); 680 681 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 682 if (reg & DWC3_DCTL_INITU2ENA) 683 param = dwc->u2pel; 684 if (reg & DWC3_DCTL_INITU1ENA) 685 param = dwc->u1pel; 686 687 /* 688 * According to Synopsys Databook, if parameter is 689 * greater than 125, a value of zero should be 690 * programmed in the register. 691 */ 692 if (param > 125) 693 param = 0; 694 695 /* now that we have the time, issue DGCMD Set Sel */ 696 ret = dwc3_send_gadget_generic_command(dwc, 697 DWC3_DGCMD_SET_PERIODIC_PAR, param); 698 WARN_ON(ret < 0); 699 } 700 701 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 702 { 703 struct dwc3_ep *dep; 704 enum usb_device_state state = dwc->gadget.state; 705 u16 wLength; 706 707 if (state == USB_STATE_DEFAULT) 708 return -EINVAL; 709 710 wLength = le16_to_cpu(ctrl->wLength); 711 712 if (wLength != 6) { 713 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 714 wLength); 715 return -EINVAL; 716 } 717 718 /* 719 * To handle Set SEL we need to receive 6 bytes from Host. So let's 720 * queue a usb_request for 6 bytes. 721 * 722 * Remember, though, this controller can't handle non-wMaxPacketSize 723 * aligned transfers on the OUT direction, so we queue a request for 724 * wMaxPacketSize instead. 725 */ 726 dep = dwc->eps[0]; 727 dwc->ep0_usb_req.dep = dep; 728 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 729 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 730 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 731 732 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 733 } 734 735 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 736 { 737 u16 wLength; 738 u16 wValue; 739 u16 wIndex; 740 741 wValue = le16_to_cpu(ctrl->wValue); 742 wLength = le16_to_cpu(ctrl->wLength); 743 wIndex = le16_to_cpu(ctrl->wIndex); 744 745 if (wIndex || wLength) 746 return -EINVAL; 747 748 /* 749 * REVISIT It's unclear from Databook what to do with this 750 * value. For now, just cache it. 751 */ 752 dwc->isoch_delay = wValue; 753 754 return 0; 755 } 756 757 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 758 { 759 int ret; 760 761 switch (ctrl->bRequest) { 762 case USB_REQ_GET_STATUS: 763 ret = dwc3_ep0_handle_status(dwc, ctrl); 764 break; 765 case USB_REQ_CLEAR_FEATURE: 766 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 767 break; 768 case USB_REQ_SET_FEATURE: 769 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 770 break; 771 case USB_REQ_SET_ADDRESS: 772 ret = dwc3_ep0_set_address(dwc, ctrl); 773 break; 774 case USB_REQ_SET_CONFIGURATION: 775 ret = dwc3_ep0_set_config(dwc, ctrl); 776 break; 777 case USB_REQ_SET_SEL: 778 ret = dwc3_ep0_set_sel(dwc, ctrl); 779 break; 780 case USB_REQ_SET_ISOCH_DELAY: 781 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 782 break; 783 default: 784 ret = dwc3_ep0_delegate_req(dwc, ctrl); 785 break; 786 } 787 788 return ret; 789 } 790 791 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 792 const struct dwc3_event_depevt *event) 793 { 794 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 795 int ret = -EINVAL; 796 u32 len; 797 798 if (!dwc->gadget_driver) 799 goto out; 800 801 trace_dwc3_ctrl_req(ctrl); 802 803 len = le16_to_cpu(ctrl->wLength); 804 if (!len) { 805 dwc->three_stage_setup = false; 806 dwc->ep0_expect_in = false; 807 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 808 } else { 809 dwc->three_stage_setup = true; 810 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 811 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 812 } 813 814 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 815 ret = dwc3_ep0_std_request(dwc, ctrl); 816 else 817 ret = dwc3_ep0_delegate_req(dwc, ctrl); 818 819 if (ret == USB_GADGET_DELAYED_STATUS) 820 dwc->delayed_status = true; 821 822 out: 823 if (ret < 0) 824 dwc3_ep0_stall_and_restart(dwc); 825 } 826 827 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 828 const struct dwc3_event_depevt *event) 829 { 830 struct dwc3_request *r = NULL; 831 struct usb_request *ur; 832 struct dwc3_trb *trb; 833 struct dwc3_ep *ep0; 834 u32 transferred = 0; 835 u32 status; 836 u32 length; 837 u8 epnum; 838 839 epnum = event->endpoint_number; 840 ep0 = dwc->eps[0]; 841 842 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 843 trb = dwc->ep0_trb; 844 trace_dwc3_complete_trb(ep0, trb); 845 846 r = next_request(&ep0->pending_list); 847 if (!r) 848 return; 849 850 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 851 if (status == DWC3_TRBSTS_SETUP_PENDING) { 852 dwc->setup_packet_pending = true; 853 if (r) 854 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 855 856 return; 857 } 858 859 ur = &r->request; 860 861 length = trb->size & DWC3_TRB_SIZE_MASK; 862 transferred = ur->length - length; 863 ur->actual += transferred; 864 865 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 866 ur->length && ur->zero) || dwc->ep0_bounced) { 867 trb++; 868 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 869 trace_dwc3_complete_trb(ep0, trb); 870 ep0->trb_enqueue = 0; 871 dwc->ep0_bounced = false; 872 } 873 874 if ((epnum & 1) && ur->actual < ur->length) 875 dwc3_ep0_stall_and_restart(dwc); 876 else 877 dwc3_gadget_giveback(ep0, r, 0); 878 } 879 880 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 881 const struct dwc3_event_depevt *event) 882 { 883 struct dwc3_request *r; 884 struct dwc3_ep *dep; 885 struct dwc3_trb *trb; 886 u32 status; 887 888 dep = dwc->eps[0]; 889 trb = dwc->ep0_trb; 890 891 trace_dwc3_complete_trb(dep, trb); 892 893 if (!list_empty(&dep->pending_list)) { 894 r = next_request(&dep->pending_list); 895 896 dwc3_gadget_giveback(dep, r, 0); 897 } 898 899 if (dwc->test_mode) { 900 int ret; 901 902 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 903 if (ret < 0) { 904 dev_err(dwc->dev, "invalid test #%d\n", 905 dwc->test_mode_nr); 906 dwc3_ep0_stall_and_restart(dwc); 907 return; 908 } 909 } 910 911 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 912 if (status == DWC3_TRBSTS_SETUP_PENDING) 913 dwc->setup_packet_pending = true; 914 915 dwc->ep0state = EP0_SETUP_PHASE; 916 dwc3_ep0_out_start(dwc); 917 } 918 919 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 920 const struct dwc3_event_depevt *event) 921 { 922 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 923 924 dep->flags &= ~DWC3_EP_BUSY; 925 dep->resource_index = 0; 926 dwc->setup_packet_pending = false; 927 928 switch (dwc->ep0state) { 929 case EP0_SETUP_PHASE: 930 dwc3_ep0_inspect_setup(dwc, event); 931 break; 932 933 case EP0_DATA_PHASE: 934 dwc3_ep0_complete_data(dwc, event); 935 break; 936 937 case EP0_STATUS_PHASE: 938 dwc3_ep0_complete_status(dwc, event); 939 break; 940 default: 941 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 942 } 943 } 944 945 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 946 struct dwc3_ep *dep, struct dwc3_request *req) 947 { 948 int ret; 949 950 req->direction = !!dep->number; 951 952 if (req->request.length == 0) { 953 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, 954 DWC3_TRBCTL_CONTROL_DATA, false); 955 ret = dwc3_ep0_start_trans(dep); 956 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 957 && (dep->number == 0)) { 958 u32 maxpacket; 959 u32 rem; 960 961 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 962 &req->request, dep->number); 963 if (ret) 964 return; 965 966 maxpacket = dep->endpoint.maxpacket; 967 rem = req->request.length % maxpacket; 968 dwc->ep0_bounced = true; 969 970 /* prepare normal TRB */ 971 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 972 req->request.length, 973 DWC3_TRBCTL_CONTROL_DATA, 974 true); 975 976 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 977 978 /* Now prepare one extra TRB to align transfer size */ 979 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 980 maxpacket - rem, 981 DWC3_TRBCTL_CONTROL_DATA, 982 false); 983 ret = dwc3_ep0_start_trans(dep); 984 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 985 req->request.length && req->request.zero) { 986 u32 maxpacket; 987 988 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 989 &req->request, dep->number); 990 if (ret) 991 return; 992 993 maxpacket = dep->endpoint.maxpacket; 994 995 /* prepare normal TRB */ 996 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 997 req->request.length, 998 DWC3_TRBCTL_CONTROL_DATA, 999 true); 1000 1001 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1002 1003 /* Now prepare one extra TRB to align transfer size */ 1004 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1005 0, DWC3_TRBCTL_CONTROL_DATA, 1006 false); 1007 ret = dwc3_ep0_start_trans(dep); 1008 } else { 1009 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1010 &req->request, dep->number); 1011 if (ret) 1012 return; 1013 1014 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1015 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1016 false); 1017 1018 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1019 1020 ret = dwc3_ep0_start_trans(dep); 1021 } 1022 1023 WARN_ON(ret < 0); 1024 } 1025 1026 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1027 { 1028 struct dwc3 *dwc = dep->dwc; 1029 u32 type; 1030 1031 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1032 : DWC3_TRBCTL_CONTROL_STATUS2; 1033 1034 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1035 return dwc3_ep0_start_trans(dep); 1036 } 1037 1038 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1039 { 1040 WARN_ON(dwc3_ep0_start_control_status(dep)); 1041 } 1042 1043 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1044 const struct dwc3_event_depevt *event) 1045 { 1046 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1047 1048 __dwc3_ep0_do_control_status(dwc, dep); 1049 } 1050 1051 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1052 { 1053 struct dwc3_gadget_ep_cmd_params params; 1054 u32 cmd; 1055 int ret; 1056 1057 if (!dep->resource_index) 1058 return; 1059 1060 cmd = DWC3_DEPCMD_ENDTRANSFER; 1061 cmd |= DWC3_DEPCMD_CMDIOC; 1062 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1063 memset(¶ms, 0, sizeof(params)); 1064 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1065 WARN_ON_ONCE(ret); 1066 dep->resource_index = 0; 1067 } 1068 1069 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1070 const struct dwc3_event_depevt *event) 1071 { 1072 switch (event->status) { 1073 case DEPEVT_STATUS_CONTROL_DATA: 1074 /* 1075 * We already have a DATA transfer in the controller's cache, 1076 * if we receive a XferNotReady(DATA) we will ignore it, unless 1077 * it's for the wrong direction. 1078 * 1079 * In that case, we must issue END_TRANSFER command to the Data 1080 * Phase we already have started and issue SetStall on the 1081 * control endpoint. 1082 */ 1083 if (dwc->ep0_expect_in != event->endpoint_number) { 1084 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1085 1086 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1087 dwc3_ep0_end_control_data(dwc, dep); 1088 dwc3_ep0_stall_and_restart(dwc); 1089 return; 1090 } 1091 1092 break; 1093 1094 case DEPEVT_STATUS_CONTROL_STATUS: 1095 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1096 return; 1097 1098 dwc->ep0state = EP0_STATUS_PHASE; 1099 1100 if (dwc->delayed_status) { 1101 struct dwc3_ep *dep = dwc->eps[0]; 1102 1103 WARN_ON_ONCE(event->endpoint_number != 1); 1104 /* 1105 * We should handle the delay STATUS phase here if the 1106 * request for handling delay STATUS has been queued 1107 * into the list. 1108 */ 1109 if (!list_empty(&dep->pending_list)) { 1110 dwc->delayed_status = false; 1111 usb_gadget_set_state(&dwc->gadget, 1112 USB_STATE_CONFIGURED); 1113 dwc3_ep0_do_control_status(dwc, event); 1114 } 1115 1116 return; 1117 } 1118 1119 dwc3_ep0_do_control_status(dwc, event); 1120 } 1121 } 1122 1123 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1124 const struct dwc3_event_depevt *event) 1125 { 1126 switch (event->endpoint_event) { 1127 case DWC3_DEPEVT_XFERCOMPLETE: 1128 dwc3_ep0_xfer_complete(dwc, event); 1129 break; 1130 1131 case DWC3_DEPEVT_XFERNOTREADY: 1132 dwc3_ep0_xfernotready(dwc, event); 1133 break; 1134 1135 case DWC3_DEPEVT_XFERINPROGRESS: 1136 case DWC3_DEPEVT_RXTXFIFOEVT: 1137 case DWC3_DEPEVT_STREAMEVT: 1138 case DWC3_DEPEVT_EPCMDCMPLT: 1139 break; 1140 } 1141 } 1142