xref: /linux/drivers/usb/dwc3/ep0.c (revision 5860800e8696d2cbbd1a0dd60b433549d176e668)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/list.h>
19 #include <linux/dma-mapping.h>
20 
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <linux/usb/composite.h>
24 
25 #include "core.h"
26 #include "debug.h"
27 #include "gadget.h"
28 #include "io.h"
29 
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 		struct dwc3_ep *dep, struct dwc3_request *req);
33 
34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 		dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36 {
37 	struct dwc3_trb			*trb;
38 	struct dwc3			*dwc;
39 
40 	dwc = dep->dwc;
41 	trb = &dwc->ep0_trb[dep->trb_enqueue];
42 
43 	if (chain)
44 		dep->trb_enqueue++;
45 
46 	trb->bpl = lower_32_bits(buf_dma);
47 	trb->bph = upper_32_bits(buf_dma);
48 	trb->size = len;
49 	trb->ctrl = type;
50 
51 	trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 			| DWC3_TRB_CTRL_ISP_IMI);
53 
54 	if (chain)
55 		trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 	else
57 		trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 				| DWC3_TRB_CTRL_LST);
59 
60 	trace_dwc3_prepare_trb(dep, trb);
61 }
62 
63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64 {
65 	struct dwc3_gadget_ep_cmd_params params;
66 	struct dwc3			*dwc;
67 	int				ret;
68 
69 	if (dep->flags & DWC3_EP_TRANSFER_STARTED)
70 		return 0;
71 
72 	dwc = dep->dwc;
73 
74 	memset(&params, 0, sizeof(params));
75 	params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 	params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77 
78 	ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
79 	if (ret < 0)
80 		return ret;
81 
82 	dwc->ep0_next_event = DWC3_EP0_COMPLETE;
83 
84 	return 0;
85 }
86 
87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 		struct dwc3_request *req)
89 {
90 	struct dwc3		*dwc = dep->dwc;
91 
92 	req->request.actual	= 0;
93 	req->request.status	= -EINPROGRESS;
94 	req->epnum		= dep->number;
95 
96 	list_add_tail(&req->list, &dep->pending_list);
97 
98 	/*
99 	 * Gadget driver might not be quick enough to queue a request
100 	 * before we get a Transfer Not Ready event on this endpoint.
101 	 *
102 	 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 	 * flag is set, it's telling us that as soon as Gadget queues the
104 	 * required request, we should kick the transfer here because the
105 	 * IRQ we were waiting for is long gone.
106 	 */
107 	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 		unsigned int direction;
109 
110 		direction = !!(dep->flags & DWC3_EP0_DIR_IN);
111 
112 		if (dwc->ep0state != EP0_DATA_PHASE) {
113 			dev_WARN(dwc->dev, "Unexpected pending request\n");
114 			return 0;
115 		}
116 
117 		__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
118 
119 		dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
120 				DWC3_EP0_DIR_IN);
121 
122 		return 0;
123 	}
124 
125 	/*
126 	 * In case gadget driver asked us to delay the STATUS phase,
127 	 * handle it here.
128 	 */
129 	if (dwc->delayed_status) {
130 		unsigned int direction;
131 
132 		direction = !dwc->ep0_expect_in;
133 		dwc->delayed_status = false;
134 		usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
135 
136 		if (dwc->ep0state == EP0_STATUS_PHASE)
137 			__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
138 
139 		return 0;
140 	}
141 
142 	/*
143 	 * Unfortunately we have uncovered a limitation wrt the Data Phase.
144 	 *
145 	 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 	 * come before issueing Start Transfer command, but if we do, we will
147 	 * miss situations where the host starts another SETUP phase instead of
148 	 * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
149 	 * Layer Compliance Suite.
150 	 *
151 	 * The problem surfaces due to the fact that in case of back-to-back
152 	 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 	 * will be stuck waiting for XferNotReady(DATA) forever.
154 	 *
155 	 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 	 * it tells us to start Data Phase right away. It also mentions that if
157 	 * we receive a SETUP phase instead of the DATA phase, core will issue
158 	 * XferComplete for the DATA phase, before actually initiating it in
159 	 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 	 * can only be used to print some debugging logs, as the core expects
161 	 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 	 * just so it completes right away, without transferring anything and,
163 	 * only then, we can go back to the SETUP phase.
164 	 *
165 	 * Because of this scenario, SNPS decided to change the programming
166 	 * model of control transfers and support on-demand transfers only for
167 	 * the STATUS phase. To fix the issue we have now, we will always wait
168 	 * for gadget driver to queue the DATA phase's struct usb_request, then
169 	 * start it right away.
170 	 *
171 	 * If we're actually in a 2-stage transfer, we will wait for
172 	 * XferNotReady(STATUS).
173 	 */
174 	if (dwc->three_stage_setup) {
175 		unsigned int direction;
176 
177 		direction = dwc->ep0_expect_in;
178 		dwc->ep0state = EP0_DATA_PHASE;
179 
180 		__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
181 
182 		dep->flags &= ~DWC3_EP0_DIR_IN;
183 	}
184 
185 	return 0;
186 }
187 
188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
189 		gfp_t gfp_flags)
190 {
191 	struct dwc3_request		*req = to_dwc3_request(request);
192 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
193 	struct dwc3			*dwc = dep->dwc;
194 
195 	unsigned long			flags;
196 
197 	int				ret;
198 
199 	spin_lock_irqsave(&dwc->lock, flags);
200 	if (!dep->endpoint.desc || !dwc->pullups_connected) {
201 		dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
202 				dep->name);
203 		ret = -ESHUTDOWN;
204 		goto out;
205 	}
206 
207 	/* we share one TRB for ep0/1 */
208 	if (!list_empty(&dep->pending_list)) {
209 		ret = -EBUSY;
210 		goto out;
211 	}
212 
213 	ret = __dwc3_gadget_ep0_queue(dep, req);
214 
215 out:
216 	spin_unlock_irqrestore(&dwc->lock, flags);
217 
218 	return ret;
219 }
220 
221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
222 {
223 	struct dwc3_ep		*dep;
224 
225 	/* reinitialize physical ep1 */
226 	dep = dwc->eps[1];
227 	dep->flags = DWC3_EP_ENABLED;
228 
229 	/* stall is always issued on EP0 */
230 	dep = dwc->eps[0];
231 	__dwc3_gadget_ep_set_halt(dep, 1, false);
232 	dep->flags = DWC3_EP_ENABLED;
233 	dwc->delayed_status = false;
234 
235 	if (!list_empty(&dep->pending_list)) {
236 		struct dwc3_request	*req;
237 
238 		req = next_request(&dep->pending_list);
239 		dwc3_gadget_giveback(dep, req, -ECONNRESET);
240 	}
241 
242 	dwc->ep0state = EP0_SETUP_PHASE;
243 	dwc3_ep0_out_start(dwc);
244 }
245 
246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
247 {
248 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
249 	struct dwc3			*dwc = dep->dwc;
250 
251 	dwc3_ep0_stall_and_restart(dwc);
252 
253 	return 0;
254 }
255 
256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
257 {
258 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
259 	struct dwc3			*dwc = dep->dwc;
260 	unsigned long			flags;
261 	int				ret;
262 
263 	spin_lock_irqsave(&dwc->lock, flags);
264 	ret = __dwc3_gadget_ep0_set_halt(ep, value);
265 	spin_unlock_irqrestore(&dwc->lock, flags);
266 
267 	return ret;
268 }
269 
270 void dwc3_ep0_out_start(struct dwc3 *dwc)
271 {
272 	struct dwc3_ep			*dep;
273 	int				ret;
274 	int                             i;
275 
276 	complete(&dwc->ep0_in_setup);
277 
278 	dep = dwc->eps[0];
279 	dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
280 			DWC3_TRBCTL_CONTROL_SETUP, false);
281 	ret = dwc3_ep0_start_trans(dep);
282 	WARN_ON(ret < 0);
283 	for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
284 		struct dwc3_ep *dwc3_ep;
285 
286 		dwc3_ep = dwc->eps[i];
287 		if (!dwc3_ep)
288 			continue;
289 
290 		if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
291 			continue;
292 
293 		dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
294 		dwc3_stop_active_transfer(dwc3_ep, true, true);
295 	}
296 }
297 
298 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
299 {
300 	struct dwc3_ep		*dep;
301 	u32			windex = le16_to_cpu(wIndex_le);
302 	u32			epnum;
303 
304 	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
305 	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
306 		epnum |= 1;
307 
308 	dep = dwc->eps[epnum];
309 	if (dep == NULL)
310 		return NULL;
311 
312 	if (dep->flags & DWC3_EP_ENABLED)
313 		return dep;
314 
315 	return NULL;
316 }
317 
318 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
319 {
320 }
321 /*
322  * ch 9.4.5
323  */
324 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
325 		struct usb_ctrlrequest *ctrl)
326 {
327 	struct dwc3_ep		*dep;
328 	u32			recip;
329 	u32			value;
330 	u32			reg;
331 	u16			usb_status = 0;
332 	__le16			*response_pkt;
333 
334 	/* We don't support PTM_STATUS */
335 	value = le16_to_cpu(ctrl->wValue);
336 	if (value != 0)
337 		return -EINVAL;
338 
339 	recip = ctrl->bRequestType & USB_RECIP_MASK;
340 	switch (recip) {
341 	case USB_RECIP_DEVICE:
342 		/*
343 		 * LTM will be set once we know how to set this in HW.
344 		 */
345 		usb_status |= dwc->gadget->is_selfpowered;
346 
347 		if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
348 		    (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
349 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
350 			if (reg & DWC3_DCTL_INITU1ENA)
351 				usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
352 			if (reg & DWC3_DCTL_INITU2ENA)
353 				usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
354 		}
355 
356 		break;
357 
358 	case USB_RECIP_INTERFACE:
359 		/*
360 		 * Function Remote Wake Capable	D0
361 		 * Function Remote Wakeup	D1
362 		 */
363 		break;
364 
365 	case USB_RECIP_ENDPOINT:
366 		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
367 		if (!dep)
368 			return -EINVAL;
369 
370 		if (dep->flags & DWC3_EP_STALL)
371 			usb_status = 1 << USB_ENDPOINT_HALT;
372 		break;
373 	default:
374 		return -EINVAL;
375 	}
376 
377 	response_pkt = (__le16 *) dwc->setup_buf;
378 	*response_pkt = cpu_to_le16(usb_status);
379 
380 	dep = dwc->eps[0];
381 	dwc->ep0_usb_req.dep = dep;
382 	dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
383 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
384 	dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
385 
386 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
387 }
388 
389 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
390 		int set)
391 {
392 	u32 reg;
393 
394 	if (state != USB_STATE_CONFIGURED)
395 		return -EINVAL;
396 	if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
397 			(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
398 		return -EINVAL;
399 	if (set && dwc->dis_u1_entry_quirk)
400 		return -EINVAL;
401 
402 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
403 	if (set)
404 		reg |= DWC3_DCTL_INITU1ENA;
405 	else
406 		reg &= ~DWC3_DCTL_INITU1ENA;
407 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
408 
409 	return 0;
410 }
411 
412 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
413 		int set)
414 {
415 	u32 reg;
416 
417 
418 	if (state != USB_STATE_CONFIGURED)
419 		return -EINVAL;
420 	if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
421 			(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
422 		return -EINVAL;
423 	if (set && dwc->dis_u2_entry_quirk)
424 		return -EINVAL;
425 
426 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
427 	if (set)
428 		reg |= DWC3_DCTL_INITU2ENA;
429 	else
430 		reg &= ~DWC3_DCTL_INITU2ENA;
431 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
432 
433 	return 0;
434 }
435 
436 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
437 		u32 wIndex, int set)
438 {
439 	if ((wIndex & 0xff) != 0)
440 		return -EINVAL;
441 	if (!set)
442 		return -EINVAL;
443 
444 	switch (wIndex >> 8) {
445 	case USB_TEST_J:
446 	case USB_TEST_K:
447 	case USB_TEST_SE0_NAK:
448 	case USB_TEST_PACKET:
449 	case USB_TEST_FORCE_ENABLE:
450 		dwc->test_mode_nr = wIndex >> 8;
451 		dwc->test_mode = true;
452 		break;
453 	default:
454 		return -EINVAL;
455 	}
456 
457 	return 0;
458 }
459 
460 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
461 		struct usb_ctrlrequest *ctrl, int set)
462 {
463 	enum usb_device_state	state;
464 	u32			wValue;
465 	u32			wIndex;
466 	int			ret = 0;
467 
468 	wValue = le16_to_cpu(ctrl->wValue);
469 	wIndex = le16_to_cpu(ctrl->wIndex);
470 	state = dwc->gadget->state;
471 
472 	switch (wValue) {
473 	case USB_DEVICE_REMOTE_WAKEUP:
474 		break;
475 	/*
476 	 * 9.4.1 says only only for SS, in AddressState only for
477 	 * default control pipe
478 	 */
479 	case USB_DEVICE_U1_ENABLE:
480 		ret = dwc3_ep0_handle_u1(dwc, state, set);
481 		break;
482 	case USB_DEVICE_U2_ENABLE:
483 		ret = dwc3_ep0_handle_u2(dwc, state, set);
484 		break;
485 	case USB_DEVICE_LTM_ENABLE:
486 		ret = -EINVAL;
487 		break;
488 	case USB_DEVICE_TEST_MODE:
489 		ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
490 		break;
491 	default:
492 		ret = -EINVAL;
493 	}
494 
495 	return ret;
496 }
497 
498 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
499 		struct usb_ctrlrequest *ctrl, int set)
500 {
501 	u32			wValue;
502 	int			ret = 0;
503 
504 	wValue = le16_to_cpu(ctrl->wValue);
505 
506 	switch (wValue) {
507 	case USB_INTRF_FUNC_SUSPEND:
508 		/*
509 		 * REVISIT: Ideally we would enable some low power mode here,
510 		 * however it's unclear what we should be doing here.
511 		 *
512 		 * For now, we're not doing anything, just making sure we return
513 		 * 0 so USB Command Verifier tests pass without any errors.
514 		 */
515 		break;
516 	default:
517 		ret = -EINVAL;
518 	}
519 
520 	return ret;
521 }
522 
523 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
524 		struct usb_ctrlrequest *ctrl, int set)
525 {
526 	struct dwc3_ep		*dep;
527 	u32			wValue;
528 	int			ret;
529 
530 	wValue = le16_to_cpu(ctrl->wValue);
531 
532 	switch (wValue) {
533 	case USB_ENDPOINT_HALT:
534 		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
535 		if (!dep)
536 			return -EINVAL;
537 
538 		if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
539 			break;
540 
541 		ret = __dwc3_gadget_ep_set_halt(dep, set, true);
542 		if (ret)
543 			return -EINVAL;
544 
545 		/* ClearFeature(Halt) may need delayed status */
546 		if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
547 			return USB_GADGET_DELAYED_STATUS;
548 
549 		break;
550 	default:
551 		return -EINVAL;
552 	}
553 
554 	return 0;
555 }
556 
557 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
558 		struct usb_ctrlrequest *ctrl, int set)
559 {
560 	u32			recip;
561 	int			ret;
562 
563 	recip = ctrl->bRequestType & USB_RECIP_MASK;
564 
565 	switch (recip) {
566 	case USB_RECIP_DEVICE:
567 		ret = dwc3_ep0_handle_device(dwc, ctrl, set);
568 		break;
569 	case USB_RECIP_INTERFACE:
570 		ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
571 		break;
572 	case USB_RECIP_ENDPOINT:
573 		ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
574 		break;
575 	default:
576 		ret = -EINVAL;
577 	}
578 
579 	return ret;
580 }
581 
582 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
583 {
584 	enum usb_device_state state = dwc->gadget->state;
585 	u32 addr;
586 	u32 reg;
587 
588 	addr = le16_to_cpu(ctrl->wValue);
589 	if (addr > 127) {
590 		dev_err(dwc->dev, "invalid device address %d\n", addr);
591 		return -EINVAL;
592 	}
593 
594 	if (state == USB_STATE_CONFIGURED) {
595 		dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
596 		return -EINVAL;
597 	}
598 
599 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
600 	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
601 	reg |= DWC3_DCFG_DEVADDR(addr);
602 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
603 
604 	if (addr)
605 		usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
606 	else
607 		usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
608 
609 	return 0;
610 }
611 
612 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
613 {
614 	int ret = -EINVAL;
615 
616 	if (dwc->async_callbacks) {
617 		spin_unlock(&dwc->lock);
618 		ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
619 		spin_lock(&dwc->lock);
620 	}
621 	return ret;
622 }
623 
624 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
625 {
626 	enum usb_device_state state = dwc->gadget->state;
627 	u32 cfg;
628 	int ret;
629 	u32 reg;
630 
631 	cfg = le16_to_cpu(ctrl->wValue);
632 
633 	switch (state) {
634 	case USB_STATE_DEFAULT:
635 		return -EINVAL;
636 
637 	case USB_STATE_ADDRESS:
638 		dwc3_gadget_clear_tx_fifos(dwc);
639 
640 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
641 		/* if the cfg matches and the cfg is non zero */
642 		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
643 
644 			/*
645 			 * only change state if set_config has already
646 			 * been processed. If gadget driver returns
647 			 * USB_GADGET_DELAYED_STATUS, we will wait
648 			 * to change the state on the next usb_ep_queue()
649 			 */
650 			if (ret == 0)
651 				usb_gadget_set_state(dwc->gadget,
652 						USB_STATE_CONFIGURED);
653 
654 			/*
655 			 * Enable transition to U1/U2 state when
656 			 * nothing is pending from application.
657 			 */
658 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
659 			if (!dwc->dis_u1_entry_quirk)
660 				reg |= DWC3_DCTL_ACCEPTU1ENA;
661 			if (!dwc->dis_u2_entry_quirk)
662 				reg |= DWC3_DCTL_ACCEPTU2ENA;
663 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
664 		}
665 		break;
666 
667 	case USB_STATE_CONFIGURED:
668 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
669 		if (!cfg && !ret)
670 			usb_gadget_set_state(dwc->gadget,
671 					USB_STATE_ADDRESS);
672 		break;
673 	default:
674 		ret = -EINVAL;
675 	}
676 	return ret;
677 }
678 
679 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
680 {
681 	struct dwc3_ep	*dep = to_dwc3_ep(ep);
682 	struct dwc3	*dwc = dep->dwc;
683 
684 	u32		param = 0;
685 	u32		reg;
686 
687 	struct timing {
688 		u8	u1sel;
689 		u8	u1pel;
690 		__le16	u2sel;
691 		__le16	u2pel;
692 	} __packed timing;
693 
694 	int		ret;
695 
696 	memcpy(&timing, req->buf, sizeof(timing));
697 
698 	dwc->u1sel = timing.u1sel;
699 	dwc->u1pel = timing.u1pel;
700 	dwc->u2sel = le16_to_cpu(timing.u2sel);
701 	dwc->u2pel = le16_to_cpu(timing.u2pel);
702 
703 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
704 	if (reg & DWC3_DCTL_INITU2ENA)
705 		param = dwc->u2pel;
706 	if (reg & DWC3_DCTL_INITU1ENA)
707 		param = dwc->u1pel;
708 
709 	/*
710 	 * According to Synopsys Databook, if parameter is
711 	 * greater than 125, a value of zero should be
712 	 * programmed in the register.
713 	 */
714 	if (param > 125)
715 		param = 0;
716 
717 	/* now that we have the time, issue DGCMD Set Sel */
718 	ret = dwc3_send_gadget_generic_command(dwc,
719 			DWC3_DGCMD_SET_PERIODIC_PAR, param);
720 	WARN_ON(ret < 0);
721 }
722 
723 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
724 {
725 	struct dwc3_ep	*dep;
726 	enum usb_device_state state = dwc->gadget->state;
727 	u16		wLength;
728 
729 	if (state == USB_STATE_DEFAULT)
730 		return -EINVAL;
731 
732 	wLength = le16_to_cpu(ctrl->wLength);
733 
734 	if (wLength != 6) {
735 		dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
736 				wLength);
737 		return -EINVAL;
738 	}
739 
740 	/*
741 	 * To handle Set SEL we need to receive 6 bytes from Host. So let's
742 	 * queue a usb_request for 6 bytes.
743 	 *
744 	 * Remember, though, this controller can't handle non-wMaxPacketSize
745 	 * aligned transfers on the OUT direction, so we queue a request for
746 	 * wMaxPacketSize instead.
747 	 */
748 	dep = dwc->eps[0];
749 	dwc->ep0_usb_req.dep = dep;
750 	dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
751 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
752 	dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
753 
754 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
755 }
756 
757 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
758 {
759 	u16		wLength;
760 	u16		wValue;
761 	u16		wIndex;
762 
763 	wValue = le16_to_cpu(ctrl->wValue);
764 	wLength = le16_to_cpu(ctrl->wLength);
765 	wIndex = le16_to_cpu(ctrl->wIndex);
766 
767 	if (wIndex || wLength)
768 		return -EINVAL;
769 
770 	dwc->gadget->isoch_delay = wValue;
771 
772 	return 0;
773 }
774 
775 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
776 {
777 	int ret;
778 
779 	switch (ctrl->bRequest) {
780 	case USB_REQ_GET_STATUS:
781 		ret = dwc3_ep0_handle_status(dwc, ctrl);
782 		break;
783 	case USB_REQ_CLEAR_FEATURE:
784 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
785 		break;
786 	case USB_REQ_SET_FEATURE:
787 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
788 		break;
789 	case USB_REQ_SET_ADDRESS:
790 		ret = dwc3_ep0_set_address(dwc, ctrl);
791 		break;
792 	case USB_REQ_SET_CONFIGURATION:
793 		ret = dwc3_ep0_set_config(dwc, ctrl);
794 		break;
795 	case USB_REQ_SET_SEL:
796 		ret = dwc3_ep0_set_sel(dwc, ctrl);
797 		break;
798 	case USB_REQ_SET_ISOCH_DELAY:
799 		ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
800 		break;
801 	default:
802 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
803 		break;
804 	}
805 
806 	return ret;
807 }
808 
809 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
810 		const struct dwc3_event_depevt *event)
811 {
812 	struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
813 	int ret = -EINVAL;
814 	u32 len;
815 
816 	if (!dwc->gadget_driver || !dwc->connected)
817 		goto out;
818 
819 	trace_dwc3_ctrl_req(ctrl);
820 
821 	len = le16_to_cpu(ctrl->wLength);
822 	if (!len) {
823 		dwc->three_stage_setup = false;
824 		dwc->ep0_expect_in = false;
825 		dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
826 	} else {
827 		dwc->three_stage_setup = true;
828 		dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
829 		dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
830 	}
831 
832 	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
833 		ret = dwc3_ep0_std_request(dwc, ctrl);
834 	else
835 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
836 
837 	if (ret == USB_GADGET_DELAYED_STATUS)
838 		dwc->delayed_status = true;
839 
840 out:
841 	if (ret < 0)
842 		dwc3_ep0_stall_and_restart(dwc);
843 }
844 
845 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
846 		const struct dwc3_event_depevt *event)
847 {
848 	struct dwc3_request	*r;
849 	struct usb_request	*ur;
850 	struct dwc3_trb		*trb;
851 	struct dwc3_ep		*ep0;
852 	u32			transferred = 0;
853 	u32			status;
854 	u32			length;
855 	u8			epnum;
856 
857 	epnum = event->endpoint_number;
858 	ep0 = dwc->eps[0];
859 
860 	dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
861 	trb = dwc->ep0_trb;
862 	trace_dwc3_complete_trb(ep0, trb);
863 
864 	r = next_request(&ep0->pending_list);
865 	if (!r)
866 		return;
867 
868 	status = DWC3_TRB_SIZE_TRBSTS(trb->size);
869 	if (status == DWC3_TRBSTS_SETUP_PENDING) {
870 		dwc->setup_packet_pending = true;
871 		if (r)
872 			dwc3_gadget_giveback(ep0, r, -ECONNRESET);
873 
874 		return;
875 	}
876 
877 	ur = &r->request;
878 
879 	length = trb->size & DWC3_TRB_SIZE_MASK;
880 	transferred = ur->length - length;
881 	ur->actual += transferred;
882 
883 	if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
884 	     ur->length && ur->zero) || dwc->ep0_bounced) {
885 		trb++;
886 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
887 		trace_dwc3_complete_trb(ep0, trb);
888 
889 		if (r->direction)
890 			dwc->eps[1]->trb_enqueue = 0;
891 		else
892 			dwc->eps[0]->trb_enqueue = 0;
893 
894 		dwc->ep0_bounced = false;
895 	}
896 
897 	if ((epnum & 1) && ur->actual < ur->length)
898 		dwc3_ep0_stall_and_restart(dwc);
899 	else
900 		dwc3_gadget_giveback(ep0, r, 0);
901 }
902 
903 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
904 		const struct dwc3_event_depevt *event)
905 {
906 	struct dwc3_request	*r;
907 	struct dwc3_ep		*dep;
908 	struct dwc3_trb		*trb;
909 	u32			status;
910 
911 	dep = dwc->eps[0];
912 	trb = dwc->ep0_trb;
913 
914 	trace_dwc3_complete_trb(dep, trb);
915 
916 	if (!list_empty(&dep->pending_list)) {
917 		r = next_request(&dep->pending_list);
918 
919 		dwc3_gadget_giveback(dep, r, 0);
920 	}
921 
922 	if (dwc->test_mode) {
923 		int ret;
924 
925 		ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
926 		if (ret < 0) {
927 			dev_err(dwc->dev, "invalid test #%d\n",
928 					dwc->test_mode_nr);
929 			dwc3_ep0_stall_and_restart(dwc);
930 			return;
931 		}
932 	}
933 
934 	status = DWC3_TRB_SIZE_TRBSTS(trb->size);
935 	if (status == DWC3_TRBSTS_SETUP_PENDING)
936 		dwc->setup_packet_pending = true;
937 
938 	dwc->ep0state = EP0_SETUP_PHASE;
939 	dwc3_ep0_out_start(dwc);
940 }
941 
942 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
943 			const struct dwc3_event_depevt *event)
944 {
945 	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];
946 
947 	dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
948 	dep->resource_index = 0;
949 	dwc->setup_packet_pending = false;
950 
951 	switch (dwc->ep0state) {
952 	case EP0_SETUP_PHASE:
953 		dwc3_ep0_inspect_setup(dwc, event);
954 		break;
955 
956 	case EP0_DATA_PHASE:
957 		dwc3_ep0_complete_data(dwc, event);
958 		break;
959 
960 	case EP0_STATUS_PHASE:
961 		dwc3_ep0_complete_status(dwc, event);
962 		break;
963 	default:
964 		WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
965 	}
966 }
967 
968 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
969 		struct dwc3_ep *dep, struct dwc3_request *req)
970 {
971 	unsigned int		trb_length = 0;
972 	int			ret;
973 
974 	req->direction = !!dep->number;
975 
976 	if (req->request.length == 0) {
977 		if (!req->direction)
978 			trb_length = dep->endpoint.maxpacket;
979 
980 		dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
981 				DWC3_TRBCTL_CONTROL_DATA, false);
982 		ret = dwc3_ep0_start_trans(dep);
983 	} else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
984 			&& (dep->number == 0)) {
985 		u32	maxpacket;
986 		u32	rem;
987 
988 		ret = usb_gadget_map_request_by_dev(dwc->sysdev,
989 				&req->request, dep->number);
990 		if (ret)
991 			return;
992 
993 		maxpacket = dep->endpoint.maxpacket;
994 		rem = req->request.length % maxpacket;
995 		dwc->ep0_bounced = true;
996 
997 		/* prepare normal TRB */
998 		dwc3_ep0_prepare_one_trb(dep, req->request.dma,
999 					 req->request.length,
1000 					 DWC3_TRBCTL_CONTROL_DATA,
1001 					 true);
1002 
1003 		req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1004 
1005 		/* Now prepare one extra TRB to align transfer size */
1006 		dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1007 					 maxpacket - rem,
1008 					 DWC3_TRBCTL_CONTROL_DATA,
1009 					 false);
1010 		ret = dwc3_ep0_start_trans(dep);
1011 	} else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1012 		   req->request.length && req->request.zero) {
1013 
1014 		ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1015 				&req->request, dep->number);
1016 		if (ret)
1017 			return;
1018 
1019 		/* prepare normal TRB */
1020 		dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1021 					 req->request.length,
1022 					 DWC3_TRBCTL_CONTROL_DATA,
1023 					 true);
1024 
1025 		req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1026 
1027 		if (!req->direction)
1028 			trb_length = dep->endpoint.maxpacket;
1029 
1030 		/* Now prepare one extra TRB to align transfer size */
1031 		dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1032 					 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1033 					 false);
1034 		ret = dwc3_ep0_start_trans(dep);
1035 	} else {
1036 		ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1037 				&req->request, dep->number);
1038 		if (ret)
1039 			return;
1040 
1041 		dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1042 				req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1043 				false);
1044 
1045 		req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1046 
1047 		ret = dwc3_ep0_start_trans(dep);
1048 	}
1049 
1050 	WARN_ON(ret < 0);
1051 }
1052 
1053 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1054 {
1055 	struct dwc3		*dwc = dep->dwc;
1056 	u32			type;
1057 
1058 	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1059 		: DWC3_TRBCTL_CONTROL_STATUS2;
1060 
1061 	dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1062 	return dwc3_ep0_start_trans(dep);
1063 }
1064 
1065 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1066 {
1067 	WARN_ON(dwc3_ep0_start_control_status(dep));
1068 }
1069 
1070 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1071 		const struct dwc3_event_depevt *event)
1072 {
1073 	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];
1074 
1075 	__dwc3_ep0_do_control_status(dwc, dep);
1076 }
1077 
1078 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1079 {
1080 	unsigned int direction = !dwc->ep0_expect_in;
1081 
1082 	dwc->delayed_status = false;
1083 	dwc->clear_stall_protocol = 0;
1084 
1085 	if (dwc->ep0state != EP0_STATUS_PHASE)
1086 		return;
1087 
1088 	__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1089 }
1090 
1091 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1092 {
1093 	struct dwc3_gadget_ep_cmd_params params;
1094 	u32			cmd;
1095 	int			ret;
1096 
1097 	/*
1098 	 * For status/DATA OUT stage, TRB will be queued on ep0 out
1099 	 * endpoint for which resource index is zero. Hence allow
1100 	 * queuing ENDXFER command for ep0 out endpoint.
1101 	 */
1102 	if (!dep->resource_index && dep->number)
1103 		return;
1104 
1105 	cmd = DWC3_DEPCMD_ENDTRANSFER;
1106 	cmd |= DWC3_DEPCMD_CMDIOC;
1107 	cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1108 	memset(&params, 0, sizeof(params));
1109 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1110 	WARN_ON_ONCE(ret);
1111 	dep->resource_index = 0;
1112 }
1113 
1114 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1115 		const struct dwc3_event_depevt *event)
1116 {
1117 	switch (event->status) {
1118 	case DEPEVT_STATUS_CONTROL_DATA:
1119 		/*
1120 		 * We already have a DATA transfer in the controller's cache,
1121 		 * if we receive a XferNotReady(DATA) we will ignore it, unless
1122 		 * it's for the wrong direction.
1123 		 *
1124 		 * In that case, we must issue END_TRANSFER command to the Data
1125 		 * Phase we already have started and issue SetStall on the
1126 		 * control endpoint.
1127 		 */
1128 		if (dwc->ep0_expect_in != event->endpoint_number) {
1129 			struct dwc3_ep	*dep = dwc->eps[dwc->ep0_expect_in];
1130 
1131 			dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1132 			dwc3_ep0_end_control_data(dwc, dep);
1133 			dwc3_ep0_stall_and_restart(dwc);
1134 			return;
1135 		}
1136 
1137 		break;
1138 
1139 	case DEPEVT_STATUS_CONTROL_STATUS:
1140 		if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1141 			return;
1142 
1143 		dwc->ep0state = EP0_STATUS_PHASE;
1144 
1145 		if (dwc->delayed_status) {
1146 			struct dwc3_ep *dep = dwc->eps[0];
1147 
1148 			WARN_ON_ONCE(event->endpoint_number != 1);
1149 			/*
1150 			 * We should handle the delay STATUS phase here if the
1151 			 * request for handling delay STATUS has been queued
1152 			 * into the list.
1153 			 */
1154 			if (!list_empty(&dep->pending_list)) {
1155 				dwc->delayed_status = false;
1156 				usb_gadget_set_state(dwc->gadget,
1157 						     USB_STATE_CONFIGURED);
1158 				dwc3_ep0_do_control_status(dwc, event);
1159 			}
1160 
1161 			return;
1162 		}
1163 
1164 		dwc3_ep0_do_control_status(dwc, event);
1165 	}
1166 }
1167 
1168 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1169 		const struct dwc3_event_depevt *event)
1170 {
1171 	struct dwc3_ep	*dep = dwc->eps[event->endpoint_number];
1172 	u8		cmd;
1173 
1174 	switch (event->endpoint_event) {
1175 	case DWC3_DEPEVT_XFERCOMPLETE:
1176 		dwc3_ep0_xfer_complete(dwc, event);
1177 		break;
1178 
1179 	case DWC3_DEPEVT_XFERNOTREADY:
1180 		dwc3_ep0_xfernotready(dwc, event);
1181 		break;
1182 
1183 	case DWC3_DEPEVT_XFERINPROGRESS:
1184 	case DWC3_DEPEVT_RXTXFIFOEVT:
1185 	case DWC3_DEPEVT_STREAMEVT:
1186 		break;
1187 	case DWC3_DEPEVT_EPCMDCMPLT:
1188 		cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1189 
1190 		if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1191 			dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1192 			dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1193 		}
1194 		break;
1195 	}
1196 }
1197