1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/list.h> 19 #include <linux/dma-mapping.h> 20 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <linux/usb/composite.h> 24 25 #include "core.h" 26 #include "debug.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, 34 struct usb_ctrlrequest *ctrl); 35 36 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 37 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 38 { 39 struct dwc3_trb *trb; 40 struct dwc3 *dwc; 41 42 dwc = dep->dwc; 43 trb = &dwc->ep0_trb[dep->trb_enqueue]; 44 45 if (chain) 46 dep->trb_enqueue++; 47 48 trb->bpl = lower_32_bits(buf_dma); 49 trb->bph = upper_32_bits(buf_dma); 50 trb->size = len; 51 trb->ctrl = type; 52 53 trb->ctrl |= (DWC3_TRB_CTRL_HWO 54 | DWC3_TRB_CTRL_ISP_IMI); 55 56 if (chain) 57 trb->ctrl |= DWC3_TRB_CTRL_CHN; 58 else 59 trb->ctrl |= (DWC3_TRB_CTRL_IOC 60 | DWC3_TRB_CTRL_LST); 61 62 trace_dwc3_prepare_trb(dep, trb); 63 } 64 65 static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 66 { 67 struct dwc3_gadget_ep_cmd_params params; 68 struct dwc3 *dwc; 69 int ret; 70 71 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 72 return 0; 73 74 dwc = dep->dwc; 75 76 memset(¶ms, 0, sizeof(params)); 77 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 78 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 79 80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 81 if (ret < 0) 82 return ret; 83 84 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 85 86 return 0; 87 } 88 89 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 90 struct dwc3_request *req) 91 { 92 struct dwc3 *dwc = dep->dwc; 93 94 req->request.actual = 0; 95 req->request.status = -EINPROGRESS; 96 req->epnum = dep->number; 97 req->status = DWC3_REQUEST_STATUS_QUEUED; 98 99 list_add_tail(&req->list, &dep->pending_list); 100 101 /* 102 * Gadget driver might not be quick enough to queue a request 103 * before we get a Transfer Not Ready event on this endpoint. 104 * 105 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 106 * flag is set, it's telling us that as soon as Gadget queues the 107 * required request, we should kick the transfer here because the 108 * IRQ we were waiting for is long gone. 109 */ 110 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 111 unsigned int direction; 112 113 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 114 115 if (dwc->ep0state != EP0_DATA_PHASE) { 116 dev_WARN(dwc->dev, "Unexpected pending request\n"); 117 return 0; 118 } 119 120 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 121 122 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 123 DWC3_EP0_DIR_IN); 124 125 return 0; 126 } 127 128 /* 129 * In case gadget driver asked us to delay the STATUS phase, 130 * handle it here. 131 */ 132 if (dwc->delayed_status) { 133 unsigned int direction; 134 135 direction = !dwc->ep0_expect_in; 136 dwc->delayed_status = false; 137 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); 138 139 if (dwc->ep0state == EP0_STATUS_PHASE) 140 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 141 142 return 0; 143 } 144 145 /* 146 * Unfortunately we have uncovered a limitation wrt the Data Phase. 147 * 148 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 149 * come before issuing Start Transfer command, but if we do, we will 150 * miss situations where the host starts another SETUP phase instead of 151 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 152 * Layer Compliance Suite. 153 * 154 * The problem surfaces due to the fact that in case of back-to-back 155 * SETUP packets there will be no XferNotReady(DATA) generated and we 156 * will be stuck waiting for XferNotReady(DATA) forever. 157 * 158 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 159 * it tells us to start Data Phase right away. It also mentions that if 160 * we receive a SETUP phase instead of the DATA phase, core will issue 161 * XferComplete for the DATA phase, before actually initiating it in 162 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 163 * can only be used to print some debugging logs, as the core expects 164 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 165 * just so it completes right away, without transferring anything and, 166 * only then, we can go back to the SETUP phase. 167 * 168 * Because of this scenario, SNPS decided to change the programming 169 * model of control transfers and support on-demand transfers only for 170 * the STATUS phase. To fix the issue we have now, we will always wait 171 * for gadget driver to queue the DATA phase's struct usb_request, then 172 * start it right away. 173 * 174 * If we're actually in a 2-stage transfer, we will wait for 175 * XferNotReady(STATUS). 176 */ 177 if (dwc->three_stage_setup) { 178 unsigned int direction; 179 180 direction = dwc->ep0_expect_in; 181 dwc->ep0state = EP0_DATA_PHASE; 182 183 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 184 185 dep->flags &= ~DWC3_EP0_DIR_IN; 186 } 187 188 return 0; 189 } 190 191 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 192 gfp_t gfp_flags) 193 { 194 struct dwc3_request *req = to_dwc3_request(request); 195 struct dwc3_ep *dep = to_dwc3_ep(ep); 196 struct dwc3 *dwc = dep->dwc; 197 198 unsigned long flags; 199 200 int ret; 201 202 spin_lock_irqsave(&dwc->lock, flags); 203 if (dwc->err_state != DWC3_ERR_NONE) { 204 ret = -ESHUTDOWN; 205 goto out; 206 } 207 208 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { 209 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 210 dep->name); 211 ret = -ESHUTDOWN; 212 goto out; 213 } 214 215 /* we share one TRB for ep0/1 */ 216 if (!list_empty(&dep->pending_list)) { 217 ret = -EBUSY; 218 goto out; 219 } 220 221 ret = __dwc3_gadget_ep0_queue(dep, req); 222 223 out: 224 spin_unlock_irqrestore(&dwc->lock, flags); 225 226 return ret; 227 } 228 229 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 230 { 231 struct dwc3_ep *dep; 232 233 /* reinitialize physical ep1 */ 234 dep = dwc->eps[1]; 235 dep->flags &= DWC3_EP_RESOURCE_ALLOCATED; 236 dep->flags |= DWC3_EP_ENABLED; 237 238 /* stall is always issued on EP0 */ 239 dep = dwc->eps[0]; 240 __dwc3_gadget_ep_set_halt(dep, 1, false); 241 dep->flags &= DWC3_EP_RESOURCE_ALLOCATED | DWC3_EP_TRANSFER_STARTED; 242 dep->flags |= DWC3_EP_ENABLED; 243 dwc->delayed_status = false; 244 245 if (!list_empty(&dep->pending_list)) { 246 struct dwc3_request *req; 247 248 req = next_request(&dep->pending_list); 249 if (!dwc->connected) 250 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 251 else 252 dwc3_gadget_giveback(dep, req, -ECONNRESET); 253 } 254 255 dwc->eps[0]->trb_enqueue = 0; 256 dwc->eps[1]->trb_enqueue = 0; 257 dwc->ep0state = EP0_SETUP_PHASE; 258 dwc3_ep0_out_start(dwc); 259 } 260 261 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 262 { 263 struct dwc3_ep *dep = to_dwc3_ep(ep); 264 struct dwc3 *dwc = dep->dwc; 265 266 dwc3_ep0_stall_and_restart(dwc); 267 268 return 0; 269 } 270 271 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 272 { 273 struct dwc3_ep *dep = to_dwc3_ep(ep); 274 struct dwc3 *dwc = dep->dwc; 275 unsigned long flags; 276 int ret; 277 278 spin_lock_irqsave(&dwc->lock, flags); 279 if (dwc->err_state != DWC3_ERR_NONE) { 280 spin_unlock_irqrestore(&dwc->lock, flags); 281 return -ESHUTDOWN; 282 } 283 ret = __dwc3_gadget_ep0_set_halt(ep, value); 284 spin_unlock_irqrestore(&dwc->lock, flags); 285 286 return ret; 287 } 288 289 void dwc3_ep0_out_start(struct dwc3 *dwc) 290 { 291 struct dwc3_ep *dep; 292 int ret; 293 int i; 294 295 complete(&dwc->ep0_in_setup); 296 297 dep = dwc->eps[0]; 298 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 299 DWC3_TRBCTL_CONTROL_SETUP, false); 300 ret = dwc3_ep0_start_trans(dep); 301 if (ret < 0) 302 dev_err(dwc->dev, "ep0 out start transfer failed: %d\n", ret); 303 304 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) { 305 struct dwc3_ep *dwc3_ep; 306 307 dwc3_ep = dwc->eps[i]; 308 if (!dwc3_ep) 309 continue; 310 311 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP)) 312 continue; 313 314 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP; 315 if (dwc->connected) 316 dwc3_stop_active_transfer(dwc3_ep, false, true); 317 else 318 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN); 319 } 320 } 321 322 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 323 { 324 struct dwc3_ep *dep; 325 u32 windex = le16_to_cpu(wIndex_le); 326 u32 epnum; 327 328 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 329 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 330 epnum |= 1; 331 332 dep = dwc->eps[epnum]; 333 if (dep == NULL) 334 return NULL; 335 336 if (dep->flags & DWC3_EP_ENABLED) 337 return dep; 338 339 return NULL; 340 } 341 342 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 343 { 344 } 345 /* 346 * ch 9.4.5 347 */ 348 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 349 struct usb_ctrlrequest *ctrl) 350 { 351 struct dwc3_ep *dep; 352 u32 recip; 353 u32 value; 354 u32 reg; 355 u16 usb_status = 0; 356 __le16 *response_pkt; 357 358 /* We don't support PTM_STATUS */ 359 value = le16_to_cpu(ctrl->wValue); 360 if (value != 0) 361 return -EINVAL; 362 363 recip = ctrl->bRequestType & USB_RECIP_MASK; 364 switch (recip) { 365 case USB_RECIP_DEVICE: 366 /* 367 * LTM will be set once we know how to set this in HW. 368 */ 369 usb_status |= dwc->gadget->is_selfpowered; 370 371 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 372 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 373 reg = dwc3_readl(dwc, DWC3_DCTL); 374 if (reg & DWC3_DCTL_INITU1ENA) 375 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 376 if (reg & DWC3_DCTL_INITU2ENA) 377 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 378 } else { 379 usb_status |= dwc->gadget->wakeup_armed << 380 USB_DEVICE_REMOTE_WAKEUP; 381 } 382 383 break; 384 385 case USB_RECIP_INTERFACE: 386 /* 387 * Function Remote Wake Capable D0 388 * Function Remote Wakeup D1 389 */ 390 return dwc3_ep0_delegate_req(dwc, ctrl); 391 392 case USB_RECIP_ENDPOINT: 393 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 394 if (!dep) 395 return -EINVAL; 396 397 if (dep->flags & DWC3_EP_STALL) 398 usb_status = 1 << USB_ENDPOINT_HALT; 399 break; 400 default: 401 return -EINVAL; 402 } 403 404 response_pkt = (__le16 *) dwc->setup_buf; 405 *response_pkt = cpu_to_le16(usb_status); 406 407 dep = dwc->eps[0]; 408 dwc->ep0_usb_req.dep = dep; 409 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 410 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 411 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 412 413 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 414 } 415 416 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 417 int set) 418 { 419 u32 reg; 420 421 if (state != USB_STATE_CONFIGURED) 422 return -EINVAL; 423 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 424 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 425 return -EINVAL; 426 if (set && dwc->dis_u1_entry_quirk) 427 return -EINVAL; 428 429 reg = dwc3_readl(dwc, DWC3_DCTL); 430 if (set) 431 reg |= DWC3_DCTL_INITU1ENA; 432 else 433 reg &= ~DWC3_DCTL_INITU1ENA; 434 dwc3_writel(dwc, DWC3_DCTL, reg); 435 436 return 0; 437 } 438 439 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 440 int set) 441 { 442 u32 reg; 443 444 445 if (state != USB_STATE_CONFIGURED) 446 return -EINVAL; 447 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 448 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 449 return -EINVAL; 450 if (set && dwc->dis_u2_entry_quirk) 451 return -EINVAL; 452 453 reg = dwc3_readl(dwc, DWC3_DCTL); 454 if (set) 455 reg |= DWC3_DCTL_INITU2ENA; 456 else 457 reg &= ~DWC3_DCTL_INITU2ENA; 458 dwc3_writel(dwc, DWC3_DCTL, reg); 459 460 return 0; 461 } 462 463 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 464 u32 wIndex, int set) 465 { 466 if ((wIndex & 0xff) != 0) 467 return -EINVAL; 468 if (!set) 469 return -EINVAL; 470 471 switch (wIndex >> 8) { 472 case USB_TEST_J: 473 case USB_TEST_K: 474 case USB_TEST_SE0_NAK: 475 case USB_TEST_PACKET: 476 case USB_TEST_FORCE_ENABLE: 477 dwc->test_mode_nr = wIndex >> 8; 478 dwc->test_mode = true; 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 488 struct usb_ctrlrequest *ctrl, int set) 489 { 490 enum usb_device_state state; 491 u32 wValue; 492 u32 wIndex; 493 int ret = 0; 494 495 wValue = le16_to_cpu(ctrl->wValue); 496 wIndex = le16_to_cpu(ctrl->wIndex); 497 state = dwc->gadget->state; 498 499 switch (wValue) { 500 case USB_DEVICE_REMOTE_WAKEUP: 501 if (dwc->wakeup_configured) 502 dwc->gadget->wakeup_armed = set; 503 else 504 ret = -EINVAL; 505 break; 506 /* 507 * 9.4.1 says only for SS, in AddressState only for 508 * default control pipe 509 */ 510 case USB_DEVICE_U1_ENABLE: 511 ret = dwc3_ep0_handle_u1(dwc, state, set); 512 break; 513 case USB_DEVICE_U2_ENABLE: 514 ret = dwc3_ep0_handle_u2(dwc, state, set); 515 break; 516 case USB_DEVICE_LTM_ENABLE: 517 ret = -EINVAL; 518 break; 519 case USB_DEVICE_TEST_MODE: 520 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 521 break; 522 default: 523 ret = -EINVAL; 524 } 525 526 return ret; 527 } 528 529 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 530 struct usb_ctrlrequest *ctrl, int set) 531 { 532 u32 wValue; 533 int ret = 0; 534 535 wValue = le16_to_cpu(ctrl->wValue); 536 537 switch (wValue) { 538 case USB_INTRF_FUNC_SUSPEND: 539 ret = dwc3_ep0_delegate_req(dwc, ctrl); 540 break; 541 default: 542 ret = -EINVAL; 543 } 544 545 return ret; 546 } 547 548 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 549 struct usb_ctrlrequest *ctrl, int set) 550 { 551 struct dwc3_ep *dep; 552 u32 wValue; 553 int ret; 554 555 wValue = le16_to_cpu(ctrl->wValue); 556 557 switch (wValue) { 558 case USB_ENDPOINT_HALT: 559 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 560 if (!dep) 561 return -EINVAL; 562 563 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 564 break; 565 566 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 567 if (ret) 568 return -EINVAL; 569 570 /* ClearFeature(Halt) may need delayed status */ 571 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) 572 return USB_GADGET_DELAYED_STATUS; 573 574 break; 575 default: 576 return -EINVAL; 577 } 578 579 return 0; 580 } 581 582 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 583 struct usb_ctrlrequest *ctrl, int set) 584 { 585 u32 recip; 586 int ret; 587 588 recip = ctrl->bRequestType & USB_RECIP_MASK; 589 590 switch (recip) { 591 case USB_RECIP_DEVICE: 592 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 593 break; 594 case USB_RECIP_INTERFACE: 595 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 596 break; 597 case USB_RECIP_ENDPOINT: 598 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 599 break; 600 default: 601 ret = -EINVAL; 602 } 603 604 return ret; 605 } 606 607 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 608 { 609 enum usb_device_state state = dwc->gadget->state; 610 u32 addr; 611 u32 reg; 612 613 addr = le16_to_cpu(ctrl->wValue); 614 if (addr > 127) { 615 dev_err(dwc->dev, "invalid device address %d\n", addr); 616 return -EINVAL; 617 } 618 619 if (state == USB_STATE_CONFIGURED) { 620 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 621 return -EINVAL; 622 } 623 624 reg = dwc3_readl(dwc, DWC3_DCFG); 625 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 626 reg |= DWC3_DCFG_DEVADDR(addr); 627 dwc3_writel(dwc, DWC3_DCFG, reg); 628 629 if (addr) 630 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); 631 else 632 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); 633 634 return 0; 635 } 636 637 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 638 { 639 int ret = -EINVAL; 640 641 if (dwc->async_callbacks) { 642 spin_unlock(&dwc->lock); 643 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); 644 spin_lock(&dwc->lock); 645 } 646 return ret; 647 } 648 649 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 650 { 651 enum usb_device_state state = dwc->gadget->state; 652 u32 cfg; 653 int ret; 654 u32 reg; 655 656 cfg = le16_to_cpu(ctrl->wValue); 657 658 switch (state) { 659 case USB_STATE_DEFAULT: 660 return -EINVAL; 661 662 case USB_STATE_ADDRESS: 663 dwc3_gadget_start_config(dwc, 2); 664 dwc3_gadget_clear_tx_fifos(dwc); 665 666 ret = dwc3_ep0_delegate_req(dwc, ctrl); 667 /* if the cfg matches and the cfg is non zero */ 668 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 669 670 /* 671 * only change state if set_config has already 672 * been processed. If gadget driver returns 673 * USB_GADGET_DELAYED_STATUS, we will wait 674 * to change the state on the next usb_ep_queue() 675 */ 676 if (ret == 0) 677 usb_gadget_set_state(dwc->gadget, 678 USB_STATE_CONFIGURED); 679 680 /* 681 * Enable transition to U1/U2 state when 682 * nothing is pending from application. 683 */ 684 reg = dwc3_readl(dwc, DWC3_DCTL); 685 if (!dwc->dis_u1_entry_quirk) 686 reg |= DWC3_DCTL_ACCEPTU1ENA; 687 if (!dwc->dis_u2_entry_quirk) 688 reg |= DWC3_DCTL_ACCEPTU2ENA; 689 dwc3_writel(dwc, DWC3_DCTL, reg); 690 } 691 break; 692 693 case USB_STATE_CONFIGURED: 694 ret = dwc3_ep0_delegate_req(dwc, ctrl); 695 if (!cfg && !ret) 696 usb_gadget_set_state(dwc->gadget, 697 USB_STATE_ADDRESS); 698 break; 699 default: 700 ret = -EINVAL; 701 } 702 return ret; 703 } 704 705 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 706 { 707 struct dwc3_ep *dep = to_dwc3_ep(ep); 708 struct dwc3 *dwc = dep->dwc; 709 710 u32 param = 0; 711 u32 reg; 712 713 struct timing { 714 u8 u1sel; 715 u8 u1pel; 716 __le16 u2sel; 717 __le16 u2pel; 718 } __packed timing; 719 720 int ret; 721 722 memcpy(&timing, req->buf, sizeof(timing)); 723 724 dwc->u1sel = timing.u1sel; 725 dwc->u1pel = timing.u1pel; 726 dwc->u2sel = le16_to_cpu(timing.u2sel); 727 dwc->u2pel = le16_to_cpu(timing.u2pel); 728 729 reg = dwc3_readl(dwc, DWC3_DCTL); 730 if (reg & DWC3_DCTL_INITU2ENA) 731 param = dwc->u2pel; 732 if (reg & DWC3_DCTL_INITU1ENA) 733 param = dwc->u1pel; 734 735 /* 736 * According to Synopsys Databook, if parameter is 737 * greater than 125, a value of zero should be 738 * programmed in the register. 739 */ 740 if (param > 125) 741 param = 0; 742 743 /* now that we have the time, issue DGCMD Set Sel */ 744 ret = dwc3_send_gadget_generic_command(dwc, 745 DWC3_DGCMD_SET_PERIODIC_PAR, param); 746 WARN_ON(ret < 0); 747 } 748 749 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 750 { 751 struct dwc3_ep *dep; 752 enum usb_device_state state = dwc->gadget->state; 753 u16 wLength; 754 755 if (state == USB_STATE_DEFAULT) 756 return -EINVAL; 757 758 wLength = le16_to_cpu(ctrl->wLength); 759 760 if (wLength != 6) { 761 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 762 wLength); 763 return -EINVAL; 764 } 765 766 /* 767 * To handle Set SEL we need to receive 6 bytes from Host. So let's 768 * queue a usb_request for 6 bytes. 769 * 770 * Remember, though, this controller can't handle non-wMaxPacketSize 771 * aligned transfers on the OUT direction, so we queue a request for 772 * wMaxPacketSize instead. 773 */ 774 dep = dwc->eps[0]; 775 dwc->ep0_usb_req.dep = dep; 776 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 777 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 778 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 779 780 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 781 } 782 783 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 784 { 785 u16 wLength; 786 u16 wValue; 787 u16 wIndex; 788 789 wValue = le16_to_cpu(ctrl->wValue); 790 wLength = le16_to_cpu(ctrl->wLength); 791 wIndex = le16_to_cpu(ctrl->wIndex); 792 793 if (wIndex || wLength) 794 return -EINVAL; 795 796 dwc->gadget->isoch_delay = wValue; 797 798 return 0; 799 } 800 801 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 802 { 803 int ret; 804 805 switch (ctrl->bRequest) { 806 case USB_REQ_GET_STATUS: 807 ret = dwc3_ep0_handle_status(dwc, ctrl); 808 break; 809 case USB_REQ_CLEAR_FEATURE: 810 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 811 break; 812 case USB_REQ_SET_FEATURE: 813 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 814 break; 815 case USB_REQ_SET_ADDRESS: 816 ret = dwc3_ep0_set_address(dwc, ctrl); 817 break; 818 case USB_REQ_SET_CONFIGURATION: 819 ret = dwc3_ep0_set_config(dwc, ctrl); 820 break; 821 case USB_REQ_SET_SEL: 822 ret = dwc3_ep0_set_sel(dwc, ctrl); 823 break; 824 case USB_REQ_SET_ISOCH_DELAY: 825 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 826 break; 827 default: 828 ret = dwc3_ep0_delegate_req(dwc, ctrl); 829 break; 830 } 831 832 return ret; 833 } 834 835 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 836 const struct dwc3_event_depevt *event) 837 { 838 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 839 int ret = -EINVAL; 840 u32 len; 841 842 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected) 843 goto out; 844 845 trace_dwc3_ctrl_req(dwc, ctrl); 846 847 len = le16_to_cpu(ctrl->wLength); 848 if (!len) { 849 dwc->three_stage_setup = false; 850 dwc->ep0_expect_in = false; 851 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 852 } else { 853 dwc->three_stage_setup = true; 854 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 855 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 856 } 857 858 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 859 ret = dwc3_ep0_std_request(dwc, ctrl); 860 else 861 ret = dwc3_ep0_delegate_req(dwc, ctrl); 862 863 if (ret == USB_GADGET_DELAYED_STATUS) 864 dwc->delayed_status = true; 865 866 out: 867 if (ret < 0) 868 dwc3_ep0_stall_and_restart(dwc); 869 } 870 871 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 872 const struct dwc3_event_depevt *event) 873 { 874 struct dwc3_request *r; 875 struct usb_request *ur; 876 struct dwc3_trb *trb; 877 struct dwc3_ep *ep0; 878 u32 transferred = 0; 879 u32 status; 880 u32 length; 881 u8 epnum; 882 883 epnum = event->endpoint_number; 884 ep0 = dwc->eps[0]; 885 886 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 887 trb = dwc->ep0_trb; 888 trace_dwc3_complete_trb(ep0, trb); 889 890 r = next_request(&ep0->pending_list); 891 if (!r) 892 return; 893 894 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 895 if (status == DWC3_TRBSTS_SETUP_PENDING) { 896 dwc->setup_packet_pending = true; 897 if (r) 898 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 899 900 return; 901 } 902 903 ur = &r->request; 904 905 length = trb->size & DWC3_TRB_SIZE_MASK; 906 transferred = ur->length - length; 907 ur->actual += transferred; 908 909 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 910 ur->length && ur->zero) || dwc->ep0_bounced) { 911 trb++; 912 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 913 trace_dwc3_complete_trb(ep0, trb); 914 915 if (r->direction) 916 dwc->eps[1]->trb_enqueue = 0; 917 else 918 dwc->eps[0]->trb_enqueue = 0; 919 920 dwc->ep0_bounced = false; 921 } 922 923 if ((epnum & 1) && ur->actual < ur->length) 924 dwc3_ep0_stall_and_restart(dwc); 925 else 926 dwc3_gadget_giveback(ep0, r, 0); 927 } 928 929 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 930 const struct dwc3_event_depevt *event) 931 { 932 struct dwc3_request *r; 933 struct dwc3_ep *dep; 934 struct dwc3_trb *trb; 935 u32 status; 936 937 dep = dwc->eps[0]; 938 trb = dwc->ep0_trb; 939 940 trace_dwc3_complete_trb(dep, trb); 941 942 if (!list_empty(&dep->pending_list)) { 943 r = next_request(&dep->pending_list); 944 945 dwc3_gadget_giveback(dep, r, 0); 946 } 947 948 if (dwc->test_mode) { 949 int ret; 950 951 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 952 if (ret < 0) { 953 dev_err(dwc->dev, "invalid test #%d\n", 954 dwc->test_mode_nr); 955 dwc3_ep0_stall_and_restart(dwc); 956 return; 957 } 958 } 959 960 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 961 if (status == DWC3_TRBSTS_SETUP_PENDING) 962 dwc->setup_packet_pending = true; 963 964 dwc->ep0state = EP0_SETUP_PHASE; 965 dwc3_ep0_out_start(dwc); 966 } 967 968 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 969 const struct dwc3_event_depevt *event) 970 { 971 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 972 973 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 974 dep->resource_index = 0; 975 dwc->setup_packet_pending = false; 976 977 switch (dwc->ep0state) { 978 case EP0_SETUP_PHASE: 979 dwc3_ep0_inspect_setup(dwc, event); 980 break; 981 982 case EP0_DATA_PHASE: 983 dwc3_ep0_complete_data(dwc, event); 984 break; 985 986 case EP0_STATUS_PHASE: 987 dwc3_ep0_complete_status(dwc, event); 988 break; 989 default: 990 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 991 } 992 } 993 994 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 995 struct dwc3_ep *dep, struct dwc3_request *req) 996 { 997 unsigned int trb_length = 0; 998 int ret; 999 1000 req->direction = !!dep->number; 1001 1002 if (req->request.length == 0) { 1003 if (!req->direction) 1004 trb_length = dep->endpoint.maxpacket; 1005 1006 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, 1007 DWC3_TRBCTL_CONTROL_DATA, false); 1008 ret = dwc3_ep0_start_trans(dep); 1009 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 1010 && (dep->number == 0)) { 1011 u32 maxpacket; 1012 u32 rem; 1013 1014 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1015 &req->request, dep->number); 1016 if (ret) 1017 return; 1018 1019 maxpacket = dep->endpoint.maxpacket; 1020 rem = req->request.length % maxpacket; 1021 dwc->ep0_bounced = true; 1022 1023 /* prepare normal TRB */ 1024 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1025 req->request.length, 1026 DWC3_TRBCTL_CONTROL_DATA, 1027 true); 1028 1029 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1030 1031 /* Now prepare one extra TRB to align transfer size */ 1032 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1033 maxpacket - rem, 1034 DWC3_TRBCTL_CONTROL_DATA, 1035 false); 1036 ret = dwc3_ep0_start_trans(dep); 1037 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 1038 req->request.length && req->request.zero) { 1039 1040 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1041 &req->request, dep->number); 1042 if (ret) 1043 return; 1044 1045 /* prepare normal TRB */ 1046 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1047 req->request.length, 1048 DWC3_TRBCTL_CONTROL_DATA, 1049 true); 1050 1051 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1052 1053 if (!req->direction) 1054 trb_length = dep->endpoint.maxpacket; 1055 1056 /* Now prepare one extra TRB to align transfer size */ 1057 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1058 trb_length, DWC3_TRBCTL_CONTROL_DATA, 1059 false); 1060 ret = dwc3_ep0_start_trans(dep); 1061 } else { 1062 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1063 &req->request, dep->number); 1064 if (ret) 1065 return; 1066 1067 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1068 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1069 false); 1070 1071 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1072 1073 ret = dwc3_ep0_start_trans(dep); 1074 } 1075 1076 if (ret < 0) 1077 dev_err(dwc->dev, 1078 "ep0 data phase start transfer failed: %d\n", ret); 1079 } 1080 1081 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1082 { 1083 struct dwc3 *dwc = dep->dwc; 1084 u32 type; 1085 1086 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1087 : DWC3_TRBCTL_CONTROL_STATUS2; 1088 1089 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1090 return dwc3_ep0_start_trans(dep); 1091 } 1092 1093 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1094 { 1095 int ret; 1096 1097 ret = dwc3_ep0_start_control_status(dep); 1098 if (ret) 1099 dev_err(dwc->dev, 1100 "ep0 status phase start transfer failed: %d\n", ret); 1101 } 1102 1103 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1104 const struct dwc3_event_depevt *event) 1105 { 1106 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1107 1108 __dwc3_ep0_do_control_status(dwc, dep); 1109 } 1110 1111 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) 1112 { 1113 unsigned int direction = !dwc->ep0_expect_in; 1114 1115 dwc->delayed_status = false; 1116 dwc->clear_stall_protocol = 0; 1117 1118 if (dwc->ep0state != EP0_STATUS_PHASE) 1119 return; 1120 1121 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 1122 } 1123 1124 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1125 { 1126 struct dwc3_gadget_ep_cmd_params params; 1127 u32 cmd; 1128 int ret; 1129 1130 /* 1131 * For status/DATA OUT stage, TRB will be queued on ep0 out 1132 * endpoint for which resource index is zero. Hence allow 1133 * queuing ENDXFER command for ep0 out endpoint. 1134 */ 1135 if (!dep->resource_index && dep->number) 1136 return; 1137 1138 cmd = DWC3_DEPCMD_ENDTRANSFER; 1139 cmd |= DWC3_DEPCMD_CMDIOC; 1140 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1141 memset(¶ms, 0, sizeof(params)); 1142 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1143 if (ret) 1144 dev_err_ratelimited(dwc->dev, 1145 "ep0 data phase end transfer failed: %d\n", ret); 1146 1147 dep->resource_index = 0; 1148 } 1149 1150 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1151 const struct dwc3_event_depevt *event) 1152 { 1153 switch (event->status) { 1154 case DEPEVT_STATUS_CONTROL_DATA: 1155 if (!dwc->softconnect || !dwc->connected) 1156 return; 1157 /* 1158 * We already have a DATA transfer in the controller's cache, 1159 * if we receive a XferNotReady(DATA) we will ignore it, unless 1160 * it's for the wrong direction. 1161 * 1162 * In that case, we must issue END_TRANSFER command to the Data 1163 * Phase we already have started and issue SetStall on the 1164 * control endpoint. 1165 */ 1166 if (dwc->ep0_expect_in != event->endpoint_number) { 1167 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1168 1169 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1170 dwc3_ep0_end_control_data(dwc, dep); 1171 dwc3_ep0_stall_and_restart(dwc); 1172 return; 1173 } 1174 1175 break; 1176 1177 case DEPEVT_STATUS_CONTROL_STATUS: 1178 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1179 return; 1180 1181 if (dwc->setup_packet_pending) { 1182 dwc3_ep0_stall_and_restart(dwc); 1183 return; 1184 } 1185 1186 dwc->ep0state = EP0_STATUS_PHASE; 1187 1188 if (dwc->delayed_status) { 1189 struct dwc3_ep *dep = dwc->eps[0]; 1190 1191 WARN_ON_ONCE(event->endpoint_number != 1); 1192 /* 1193 * We should handle the delay STATUS phase here if the 1194 * request for handling delay STATUS has been queued 1195 * into the list. 1196 */ 1197 if (!list_empty(&dep->pending_list)) { 1198 dwc->delayed_status = false; 1199 usb_gadget_set_state(dwc->gadget, 1200 USB_STATE_CONFIGURED); 1201 dwc3_ep0_do_control_status(dwc, event); 1202 } 1203 1204 return; 1205 } 1206 1207 dwc3_ep0_do_control_status(dwc, event); 1208 } 1209 } 1210 1211 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1212 const struct dwc3_event_depevt *event) 1213 { 1214 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1215 u8 cmd; 1216 1217 switch (event->endpoint_event) { 1218 case DWC3_DEPEVT_XFERCOMPLETE: 1219 dwc3_ep0_xfer_complete(dwc, event); 1220 break; 1221 1222 case DWC3_DEPEVT_XFERNOTREADY: 1223 dwc3_ep0_xfernotready(dwc, event); 1224 break; 1225 1226 case DWC3_DEPEVT_XFERINPROGRESS: 1227 case DWC3_DEPEVT_RXTXFIFOEVT: 1228 case DWC3_DEPEVT_STREAMEVT: 1229 break; 1230 case DWC3_DEPEVT_EPCMDCMPLT: 1231 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 1232 1233 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 1234 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; 1235 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 1236 } 1237 break; 1238 default: 1239 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event); 1240 break; 1241 } 1242 } 1243