xref: /linux/drivers/usb/dwc3/ep0.c (revision 26b0d14106954ae46d2f4f7eec3481828a210f7d)
1 /**
2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions, and the following disclaimer,
14  *    without modification.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. The names of the above-listed copyright holders may not be used
19  *    to endorse or promote products derived from this software without
20  *    specific prior written permission.
21  *
22  * ALTERNATIVELY, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2, as published by the Free
24  * Software Foundation.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
45 #include <linux/io.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
48 
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
51 #include <linux/usb/composite.h>
52 
53 #include "core.h"
54 #include "gadget.h"
55 #include "io.h"
56 
57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
58 
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
60 {
61 	switch (state) {
62 	case EP0_UNCONNECTED:
63 		return "Unconnected";
64 	case EP0_SETUP_PHASE:
65 		return "Setup Phase";
66 	case EP0_DATA_PHASE:
67 		return "Data Phase";
68 	case EP0_STATUS_PHASE:
69 		return "Status Phase";
70 	default:
71 		return "UNKNOWN";
72 	}
73 }
74 
75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
76 		u32 len, u32 type)
77 {
78 	struct dwc3_gadget_ep_cmd_params params;
79 	struct dwc3_trb			*trb;
80 	struct dwc3_ep			*dep;
81 
82 	int				ret;
83 
84 	dep = dwc->eps[epnum];
85 	if (dep->flags & DWC3_EP_BUSY) {
86 		dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
87 		return 0;
88 	}
89 
90 	trb = dwc->ep0_trb;
91 
92 	trb->bpl = lower_32_bits(buf_dma);
93 	trb->bph = upper_32_bits(buf_dma);
94 	trb->size = len;
95 	trb->ctrl = type;
96 
97 	trb->ctrl |= (DWC3_TRB_CTRL_HWO
98 			| DWC3_TRB_CTRL_LST
99 			| DWC3_TRB_CTRL_IOC
100 			| DWC3_TRB_CTRL_ISP_IMI);
101 
102 	memset(&params, 0, sizeof(params));
103 	params.param0 = upper_32_bits(dwc->ep0_trb_addr);
104 	params.param1 = lower_32_bits(dwc->ep0_trb_addr);
105 
106 	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
107 			DWC3_DEPCMD_STARTTRANSFER, &params);
108 	if (ret < 0) {
109 		dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
110 		return ret;
111 	}
112 
113 	dep->flags |= DWC3_EP_BUSY;
114 	dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
115 			dep->number);
116 
117 	dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118 
119 	return 0;
120 }
121 
122 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
123 		struct dwc3_request *req)
124 {
125 	struct dwc3		*dwc = dep->dwc;
126 	int			ret = 0;
127 
128 	req->request.actual	= 0;
129 	req->request.status	= -EINPROGRESS;
130 	req->epnum		= dep->number;
131 
132 	list_add_tail(&req->list, &dep->request_list);
133 
134 	/*
135 	 * Gadget driver might not be quick enough to queue a request
136 	 * before we get a Transfer Not Ready event on this endpoint.
137 	 *
138 	 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
139 	 * flag is set, it's telling us that as soon as Gadget queues the
140 	 * required request, we should kick the transfer here because the
141 	 * IRQ we were waiting for is long gone.
142 	 */
143 	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
144 		unsigned	direction;
145 
146 		direction = !!(dep->flags & DWC3_EP0_DIR_IN);
147 
148 		if (dwc->ep0state != EP0_DATA_PHASE) {
149 			dev_WARN(dwc->dev, "Unexpected pending request\n");
150 			return 0;
151 		}
152 
153 		ret = dwc3_ep0_start_trans(dwc, direction,
154 				req->request.dma, req->request.length,
155 				DWC3_TRBCTL_CONTROL_DATA);
156 		dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 				DWC3_EP0_DIR_IN);
158 	} else if (dwc->delayed_status) {
159 		dwc->delayed_status = false;
160 
161 		if (dwc->ep0state == EP0_STATUS_PHASE)
162 			dwc3_ep0_do_control_status(dwc, 1);
163 		else
164 			dev_dbg(dwc->dev, "too early for delayed status\n");
165 	}
166 
167 	return ret;
168 }
169 
170 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
171 		gfp_t gfp_flags)
172 {
173 	struct dwc3_request		*req = to_dwc3_request(request);
174 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
175 	struct dwc3			*dwc = dep->dwc;
176 
177 	unsigned long			flags;
178 
179 	int				ret;
180 
181 	spin_lock_irqsave(&dwc->lock, flags);
182 	if (!dep->endpoint.desc) {
183 		dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
184 				request, dep->name);
185 		ret = -ESHUTDOWN;
186 		goto out;
187 	}
188 
189 	/* we share one TRB for ep0/1 */
190 	if (!list_empty(&dep->request_list)) {
191 		ret = -EBUSY;
192 		goto out;
193 	}
194 
195 	dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
196 			request, dep->name, request->length,
197 			dwc3_ep0_state_string(dwc->ep0state));
198 
199 	ret = __dwc3_gadget_ep0_queue(dep, req);
200 
201 out:
202 	spin_unlock_irqrestore(&dwc->lock, flags);
203 
204 	return ret;
205 }
206 
207 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
208 {
209 	struct dwc3_ep		*dep = dwc->eps[0];
210 
211 	/* stall is always issued on EP0 */
212 	__dwc3_gadget_ep_set_halt(dep, 1);
213 	dep->flags = DWC3_EP_ENABLED;
214 	dwc->delayed_status = false;
215 
216 	if (!list_empty(&dep->request_list)) {
217 		struct dwc3_request	*req;
218 
219 		req = next_request(&dep->request_list);
220 		dwc3_gadget_giveback(dep, req, -ECONNRESET);
221 	}
222 
223 	dwc->ep0state = EP0_SETUP_PHASE;
224 	dwc3_ep0_out_start(dwc);
225 }
226 
227 void dwc3_ep0_out_start(struct dwc3 *dwc)
228 {
229 	int				ret;
230 
231 	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
232 			DWC3_TRBCTL_CONTROL_SETUP);
233 	WARN_ON(ret < 0);
234 }
235 
236 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
237 {
238 	struct dwc3_ep		*dep;
239 	u32			windex = le16_to_cpu(wIndex_le);
240 	u32			epnum;
241 
242 	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
243 	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
244 		epnum |= 1;
245 
246 	dep = dwc->eps[epnum];
247 	if (dep->flags & DWC3_EP_ENABLED)
248 		return dep;
249 
250 	return NULL;
251 }
252 
253 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
254 {
255 }
256 /*
257  * ch 9.4.5
258  */
259 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
260 		struct usb_ctrlrequest *ctrl)
261 {
262 	struct dwc3_ep		*dep;
263 	u32			recip;
264 	u32			reg;
265 	u16			usb_status = 0;
266 	__le16			*response_pkt;
267 
268 	recip = ctrl->bRequestType & USB_RECIP_MASK;
269 	switch (recip) {
270 	case USB_RECIP_DEVICE:
271 		/*
272 		 * LTM will be set once we know how to set this in HW.
273 		 */
274 		usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
275 
276 		if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
277 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
278 			if (reg & DWC3_DCTL_INITU1ENA)
279 				usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
280 			if (reg & DWC3_DCTL_INITU2ENA)
281 				usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
282 		}
283 
284 		break;
285 
286 	case USB_RECIP_INTERFACE:
287 		/*
288 		 * Function Remote Wake Capable	D0
289 		 * Function Remote Wakeup	D1
290 		 */
291 		break;
292 
293 	case USB_RECIP_ENDPOINT:
294 		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
295 		if (!dep)
296 			return -EINVAL;
297 
298 		if (dep->flags & DWC3_EP_STALL)
299 			usb_status = 1 << USB_ENDPOINT_HALT;
300 		break;
301 	default:
302 		return -EINVAL;
303 	};
304 
305 	response_pkt = (__le16 *) dwc->setup_buf;
306 	*response_pkt = cpu_to_le16(usb_status);
307 
308 	dep = dwc->eps[0];
309 	dwc->ep0_usb_req.dep = dep;
310 	dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
311 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
312 	dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
313 
314 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
315 }
316 
317 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
318 		struct usb_ctrlrequest *ctrl, int set)
319 {
320 	struct dwc3_ep		*dep;
321 	u32			recip;
322 	u32			wValue;
323 	u32			wIndex;
324 	u32			reg;
325 	int			ret;
326 
327 	wValue = le16_to_cpu(ctrl->wValue);
328 	wIndex = le16_to_cpu(ctrl->wIndex);
329 	recip = ctrl->bRequestType & USB_RECIP_MASK;
330 	switch (recip) {
331 	case USB_RECIP_DEVICE:
332 
333 		switch (wValue) {
334 		case USB_DEVICE_REMOTE_WAKEUP:
335 			break;
336 		/*
337 		 * 9.4.1 says only only for SS, in AddressState only for
338 		 * default control pipe
339 		 */
340 		case USB_DEVICE_U1_ENABLE:
341 			if (dwc->dev_state != DWC3_CONFIGURED_STATE)
342 				return -EINVAL;
343 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
344 				return -EINVAL;
345 
346 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347 			if (set)
348 				reg |= DWC3_DCTL_INITU1ENA;
349 			else
350 				reg &= ~DWC3_DCTL_INITU1ENA;
351 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
352 			break;
353 
354 		case USB_DEVICE_U2_ENABLE:
355 			if (dwc->dev_state != DWC3_CONFIGURED_STATE)
356 				return -EINVAL;
357 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
358 				return -EINVAL;
359 
360 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 			if (set)
362 				reg |= DWC3_DCTL_INITU2ENA;
363 			else
364 				reg &= ~DWC3_DCTL_INITU2ENA;
365 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
366 			break;
367 
368 		case USB_DEVICE_LTM_ENABLE:
369 			return -EINVAL;
370 			break;
371 
372 		case USB_DEVICE_TEST_MODE:
373 			if ((wIndex & 0xff) != 0)
374 				return -EINVAL;
375 			if (!set)
376 				return -EINVAL;
377 
378 			dwc->test_mode_nr = wIndex >> 8;
379 			dwc->test_mode = true;
380 			break;
381 		default:
382 			return -EINVAL;
383 		}
384 		break;
385 
386 	case USB_RECIP_INTERFACE:
387 		switch (wValue) {
388 		case USB_INTRF_FUNC_SUSPEND:
389 			if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
390 				/* XXX enable Low power suspend */
391 				;
392 			if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
393 				/* XXX enable remote wakeup */
394 				;
395 			break;
396 		default:
397 			return -EINVAL;
398 		}
399 		break;
400 
401 	case USB_RECIP_ENDPOINT:
402 		switch (wValue) {
403 		case USB_ENDPOINT_HALT:
404 			dep = dwc3_wIndex_to_dep(dwc, wIndex);
405 			if (!dep)
406 				return -EINVAL;
407 			ret = __dwc3_gadget_ep_set_halt(dep, set);
408 			if (ret)
409 				return -EINVAL;
410 			break;
411 		default:
412 			return -EINVAL;
413 		}
414 		break;
415 
416 	default:
417 		return -EINVAL;
418 	};
419 
420 	return 0;
421 }
422 
423 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
424 {
425 	u32 addr;
426 	u32 reg;
427 
428 	addr = le16_to_cpu(ctrl->wValue);
429 	if (addr > 127) {
430 		dev_dbg(dwc->dev, "invalid device address %d\n", addr);
431 		return -EINVAL;
432 	}
433 
434 	if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
435 		dev_dbg(dwc->dev, "trying to set address when configured\n");
436 		return -EINVAL;
437 	}
438 
439 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
440 	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
441 	reg |= DWC3_DCFG_DEVADDR(addr);
442 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
443 
444 	if (addr)
445 		dwc->dev_state = DWC3_ADDRESS_STATE;
446 	else
447 		dwc->dev_state = DWC3_DEFAULT_STATE;
448 
449 	return 0;
450 }
451 
452 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
453 {
454 	int ret;
455 
456 	spin_unlock(&dwc->lock);
457 	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
458 	spin_lock(&dwc->lock);
459 	return ret;
460 }
461 
462 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
463 {
464 	u32 cfg;
465 	int ret;
466 
467 	dwc->start_config_issued = false;
468 	cfg = le16_to_cpu(ctrl->wValue);
469 
470 	switch (dwc->dev_state) {
471 	case DWC3_DEFAULT_STATE:
472 		return -EINVAL;
473 		break;
474 
475 	case DWC3_ADDRESS_STATE:
476 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
477 		/* if the cfg matches and the cfg is non zero */
478 		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
479 			dwc->dev_state = DWC3_CONFIGURED_STATE;
480 			dwc->resize_fifos = true;
481 			dev_dbg(dwc->dev, "resize fifos flag SET\n");
482 		}
483 		break;
484 
485 	case DWC3_CONFIGURED_STATE:
486 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
487 		if (!cfg)
488 			dwc->dev_state = DWC3_ADDRESS_STATE;
489 		break;
490 	default:
491 		ret = -EINVAL;
492 	}
493 	return ret;
494 }
495 
496 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
497 {
498 	struct dwc3_ep	*dep = to_dwc3_ep(ep);
499 	struct dwc3	*dwc = dep->dwc;
500 
501 	u32		param = 0;
502 	u32		reg;
503 
504 	struct timing {
505 		u8	u1sel;
506 		u8	u1pel;
507 		u16	u2sel;
508 		u16	u2pel;
509 	} __packed timing;
510 
511 	int		ret;
512 
513 	memcpy(&timing, req->buf, sizeof(timing));
514 
515 	dwc->u1sel = timing.u1sel;
516 	dwc->u1pel = timing.u1pel;
517 	dwc->u2sel = timing.u2sel;
518 	dwc->u2pel = timing.u2pel;
519 
520 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
521 	if (reg & DWC3_DCTL_INITU2ENA)
522 		param = dwc->u2pel;
523 	if (reg & DWC3_DCTL_INITU1ENA)
524 		param = dwc->u1pel;
525 
526 	/*
527 	 * According to Synopsys Databook, if parameter is
528 	 * greater than 125, a value of zero should be
529 	 * programmed in the register.
530 	 */
531 	if (param > 125)
532 		param = 0;
533 
534 	/* now that we have the time, issue DGCMD Set Sel */
535 	ret = dwc3_send_gadget_generic_command(dwc,
536 			DWC3_DGCMD_SET_PERIODIC_PAR, param);
537 	WARN_ON(ret < 0);
538 }
539 
540 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
541 {
542 	struct dwc3_ep	*dep;
543 	u16		wLength;
544 	u16		wValue;
545 
546 	if (dwc->dev_state == DWC3_DEFAULT_STATE)
547 		return -EINVAL;
548 
549 	wValue = le16_to_cpu(ctrl->wValue);
550 	wLength = le16_to_cpu(ctrl->wLength);
551 
552 	if (wLength != 6) {
553 		dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
554 				wLength);
555 		return -EINVAL;
556 	}
557 
558 	/*
559 	 * To handle Set SEL we need to receive 6 bytes from Host. So let's
560 	 * queue a usb_request for 6 bytes.
561 	 *
562 	 * Remember, though, this controller can't handle non-wMaxPacketSize
563 	 * aligned transfers on the OUT direction, so we queue a request for
564 	 * wMaxPacketSize instead.
565 	 */
566 	dep = dwc->eps[0];
567 	dwc->ep0_usb_req.dep = dep;
568 	dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
569 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
570 	dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
571 
572 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
573 }
574 
575 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
576 {
577 	u16		wLength;
578 	u16		wValue;
579 	u16		wIndex;
580 
581 	wValue = le16_to_cpu(ctrl->wValue);
582 	wLength = le16_to_cpu(ctrl->wLength);
583 	wIndex = le16_to_cpu(ctrl->wIndex);
584 
585 	if (wIndex || wLength)
586 		return -EINVAL;
587 
588 	/*
589 	 * REVISIT It's unclear from Databook what to do with this
590 	 * value. For now, just cache it.
591 	 */
592 	dwc->isoch_delay = wValue;
593 
594 	return 0;
595 }
596 
597 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
598 {
599 	int ret;
600 
601 	switch (ctrl->bRequest) {
602 	case USB_REQ_GET_STATUS:
603 		dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
604 		ret = dwc3_ep0_handle_status(dwc, ctrl);
605 		break;
606 	case USB_REQ_CLEAR_FEATURE:
607 		dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
608 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
609 		break;
610 	case USB_REQ_SET_FEATURE:
611 		dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
612 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
613 		break;
614 	case USB_REQ_SET_ADDRESS:
615 		dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
616 		ret = dwc3_ep0_set_address(dwc, ctrl);
617 		break;
618 	case USB_REQ_SET_CONFIGURATION:
619 		dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
620 		ret = dwc3_ep0_set_config(dwc, ctrl);
621 		break;
622 	case USB_REQ_SET_SEL:
623 		dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
624 		ret = dwc3_ep0_set_sel(dwc, ctrl);
625 		break;
626 	case USB_REQ_SET_ISOCH_DELAY:
627 		dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
628 		ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
629 		break;
630 	default:
631 		dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
632 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
633 		break;
634 	};
635 
636 	return ret;
637 }
638 
639 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
640 		const struct dwc3_event_depevt *event)
641 {
642 	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
643 	int ret;
644 	u32 len;
645 
646 	if (!dwc->gadget_driver)
647 		goto err;
648 
649 	len = le16_to_cpu(ctrl->wLength);
650 	if (!len) {
651 		dwc->three_stage_setup = false;
652 		dwc->ep0_expect_in = false;
653 		dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
654 	} else {
655 		dwc->three_stage_setup = true;
656 		dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
657 		dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
658 	}
659 
660 	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
661 		ret = dwc3_ep0_std_request(dwc, ctrl);
662 	else
663 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
664 
665 	if (ret == USB_GADGET_DELAYED_STATUS)
666 		dwc->delayed_status = true;
667 
668 	if (ret >= 0)
669 		return;
670 
671 err:
672 	dwc3_ep0_stall_and_restart(dwc);
673 }
674 
675 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
676 		const struct dwc3_event_depevt *event)
677 {
678 	struct dwc3_request	*r = NULL;
679 	struct usb_request	*ur;
680 	struct dwc3_trb		*trb;
681 	struct dwc3_ep		*ep0;
682 	u32			transferred;
683 	u32			length;
684 	u8			epnum;
685 
686 	epnum = event->endpoint_number;
687 	ep0 = dwc->eps[0];
688 
689 	dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
690 
691 	r = next_request(&ep0->request_list);
692 	ur = &r->request;
693 
694 	trb = dwc->ep0_trb;
695 	length = trb->size & DWC3_TRB_SIZE_MASK;
696 
697 	if (dwc->ep0_bounced) {
698 		unsigned transfer_size = ur->length;
699 		unsigned maxp = ep0->endpoint.maxpacket;
700 
701 		transfer_size += (maxp - (transfer_size % maxp));
702 		transferred = min_t(u32, ur->length,
703 				transfer_size - length);
704 		memcpy(ur->buf, dwc->ep0_bounce, transferred);
705 		dwc->ep0_bounced = false;
706 	} else {
707 		transferred = ur->length - length;
708 	}
709 
710 	ur->actual += transferred;
711 
712 	if ((epnum & 1) && ur->actual < ur->length) {
713 		/* for some reason we did not get everything out */
714 
715 		dwc3_ep0_stall_and_restart(dwc);
716 	} else {
717 		/*
718 		 * handle the case where we have to send a zero packet. This
719 		 * seems to be case when req.length > maxpacket. Could it be?
720 		 */
721 		if (r)
722 			dwc3_gadget_giveback(ep0, r, 0);
723 	}
724 }
725 
726 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
727 		const struct dwc3_event_depevt *event)
728 {
729 	struct dwc3_request	*r;
730 	struct dwc3_ep		*dep;
731 
732 	dep = dwc->eps[0];
733 
734 	if (!list_empty(&dep->request_list)) {
735 		r = next_request(&dep->request_list);
736 
737 		dwc3_gadget_giveback(dep, r, 0);
738 	}
739 
740 	if (dwc->test_mode) {
741 		int ret;
742 
743 		ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
744 		if (ret < 0) {
745 			dev_dbg(dwc->dev, "Invalid Test #%d\n",
746 					dwc->test_mode_nr);
747 			dwc3_ep0_stall_and_restart(dwc);
748 		}
749 	}
750 
751 	dwc->ep0state = EP0_SETUP_PHASE;
752 	dwc3_ep0_out_start(dwc);
753 }
754 
755 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
756 			const struct dwc3_event_depevt *event)
757 {
758 	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];
759 
760 	dep->flags &= ~DWC3_EP_BUSY;
761 	dep->res_trans_idx = 0;
762 	dwc->setup_packet_pending = false;
763 
764 	switch (dwc->ep0state) {
765 	case EP0_SETUP_PHASE:
766 		dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
767 		dwc3_ep0_inspect_setup(dwc, event);
768 		break;
769 
770 	case EP0_DATA_PHASE:
771 		dev_vdbg(dwc->dev, "Data Phase\n");
772 		dwc3_ep0_complete_data(dwc, event);
773 		break;
774 
775 	case EP0_STATUS_PHASE:
776 		dev_vdbg(dwc->dev, "Status Phase\n");
777 		dwc3_ep0_complete_req(dwc, event);
778 		break;
779 	default:
780 		WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
781 	}
782 }
783 
784 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
785 		const struct dwc3_event_depevt *event)
786 {
787 	dwc3_ep0_out_start(dwc);
788 }
789 
790 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
791 		const struct dwc3_event_depevt *event)
792 {
793 	struct dwc3_ep		*dep;
794 	struct dwc3_request	*req;
795 	int			ret;
796 
797 	dep = dwc->eps[0];
798 
799 	if (list_empty(&dep->request_list)) {
800 		dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
801 		dep->flags |= DWC3_EP_PENDING_REQUEST;
802 
803 		if (event->endpoint_number)
804 			dep->flags |= DWC3_EP0_DIR_IN;
805 		return;
806 	}
807 
808 	req = next_request(&dep->request_list);
809 	req->direction = !!event->endpoint_number;
810 
811 	if (req->request.length == 0) {
812 		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
813 				dwc->ctrl_req_addr, 0,
814 				DWC3_TRBCTL_CONTROL_DATA);
815 	} else if ((req->request.length % dep->endpoint.maxpacket)
816 			&& (event->endpoint_number == 0)) {
817 		ret = usb_gadget_map_request(&dwc->gadget, &req->request,
818 				event->endpoint_number);
819 		if (ret) {
820 			dev_dbg(dwc->dev, "failed to map request\n");
821 			return;
822 		}
823 
824 		WARN_ON(req->request.length > dep->endpoint.maxpacket);
825 
826 		dwc->ep0_bounced = true;
827 
828 		/*
829 		 * REVISIT in case request length is bigger than EP0
830 		 * wMaxPacketSize, we will need two chained TRBs to handle
831 		 * the transfer.
832 		 */
833 		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
834 				dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
835 				DWC3_TRBCTL_CONTROL_DATA);
836 	} else {
837 		ret = usb_gadget_map_request(&dwc->gadget, &req->request,
838 				event->endpoint_number);
839 		if (ret) {
840 			dev_dbg(dwc->dev, "failed to map request\n");
841 			return;
842 		}
843 
844 		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
845 				req->request.dma, req->request.length,
846 				DWC3_TRBCTL_CONTROL_DATA);
847 	}
848 
849 	WARN_ON(ret < 0);
850 }
851 
852 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
853 {
854 	struct dwc3		*dwc = dep->dwc;
855 	u32			type;
856 
857 	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
858 		: DWC3_TRBCTL_CONTROL_STATUS2;
859 
860 	return dwc3_ep0_start_trans(dwc, dep->number,
861 			dwc->ctrl_req_addr, 0, type);
862 }
863 
864 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
865 {
866 	struct dwc3_ep		*dep = dwc->eps[epnum];
867 
868 	if (dwc->resize_fifos) {
869 		dev_dbg(dwc->dev, "starting to resize fifos\n");
870 		dwc3_gadget_resize_tx_fifos(dwc);
871 		dwc->resize_fifos = 0;
872 	}
873 
874 	WARN_ON(dwc3_ep0_start_control_status(dep));
875 }
876 
877 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
878 		const struct dwc3_event_depevt *event)
879 {
880 	dwc->setup_packet_pending = true;
881 
882 	/*
883 	 * This part is very tricky: If we has just handled
884 	 * XferNotReady(Setup) and we're now expecting a
885 	 * XferComplete but, instead, we receive another
886 	 * XferNotReady(Setup), we should STALL and restart
887 	 * the state machine.
888 	 *
889 	 * In all other cases, we just continue waiting
890 	 * for the XferComplete event.
891 	 *
892 	 * We are a little bit unsafe here because we're
893 	 * not trying to ensure that last event was, indeed,
894 	 * XferNotReady(Setup).
895 	 *
896 	 * Still, we don't expect any condition where that
897 	 * should happen and, even if it does, it would be
898 	 * another error condition.
899 	 */
900 	if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
901 		switch (event->status) {
902 		case DEPEVT_STATUS_CONTROL_SETUP:
903 			dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
904 			dwc3_ep0_stall_and_restart(dwc);
905 			break;
906 		case DEPEVT_STATUS_CONTROL_DATA:
907 			/* FALLTHROUGH */
908 		case DEPEVT_STATUS_CONTROL_STATUS:
909 			/* FALLTHROUGH */
910 		default:
911 			dev_vdbg(dwc->dev, "waiting for XferComplete\n");
912 		}
913 
914 		return;
915 	}
916 
917 	switch (event->status) {
918 	case DEPEVT_STATUS_CONTROL_SETUP:
919 		dev_vdbg(dwc->dev, "Control Setup\n");
920 
921 		dwc->ep0state = EP0_SETUP_PHASE;
922 
923 		dwc3_ep0_do_control_setup(dwc, event);
924 		break;
925 
926 	case DEPEVT_STATUS_CONTROL_DATA:
927 		dev_vdbg(dwc->dev, "Control Data\n");
928 
929 		dwc->ep0state = EP0_DATA_PHASE;
930 
931 		if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
932 			dev_vdbg(dwc->dev, "Expected %d got %d\n",
933 					dwc->ep0_next_event,
934 					DWC3_EP0_NRDY_DATA);
935 
936 			dwc3_ep0_stall_and_restart(dwc);
937 			return;
938 		}
939 
940 		/*
941 		 * One of the possible error cases is when Host _does_
942 		 * request for Data Phase, but it does so on the wrong
943 		 * direction.
944 		 *
945 		 * Here, we already know ep0_next_event is DATA (see above),
946 		 * so we only need to check for direction.
947 		 */
948 		if (dwc->ep0_expect_in != event->endpoint_number) {
949 			dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
950 			dwc3_ep0_stall_and_restart(dwc);
951 			return;
952 		}
953 
954 		dwc3_ep0_do_control_data(dwc, event);
955 		break;
956 
957 	case DEPEVT_STATUS_CONTROL_STATUS:
958 		dev_vdbg(dwc->dev, "Control Status\n");
959 
960 		dwc->ep0state = EP0_STATUS_PHASE;
961 
962 		if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
963 			dev_vdbg(dwc->dev, "Expected %d got %d\n",
964 					dwc->ep0_next_event,
965 					DWC3_EP0_NRDY_STATUS);
966 
967 			dwc3_ep0_stall_and_restart(dwc);
968 			return;
969 		}
970 
971 		if (dwc->delayed_status) {
972 			WARN_ON_ONCE(event->endpoint_number != 1);
973 			dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
974 			return;
975 		}
976 
977 		dwc3_ep0_do_control_status(dwc, event->endpoint_number);
978 	}
979 }
980 
981 void dwc3_ep0_interrupt(struct dwc3 *dwc,
982 		const struct dwc3_event_depevt *event)
983 {
984 	u8			epnum = event->endpoint_number;
985 
986 	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
987 			dwc3_ep_event_string(event->endpoint_event),
988 			epnum >> 1, (epnum & 1) ? "in" : "out",
989 			dwc3_ep0_state_string(dwc->ep0state));
990 
991 	switch (event->endpoint_event) {
992 	case DWC3_DEPEVT_XFERCOMPLETE:
993 		dwc3_ep0_xfer_complete(dwc, event);
994 		break;
995 
996 	case DWC3_DEPEVT_XFERNOTREADY:
997 		dwc3_ep0_xfernotready(dwc, event);
998 		break;
999 
1000 	case DWC3_DEPEVT_XFERINPROGRESS:
1001 	case DWC3_DEPEVT_RXTXFIFOEVT:
1002 	case DWC3_DEPEVT_STREAMEVT:
1003 	case DWC3_DEPEVT_EPCMDCMPLT:
1004 		break;
1005 	}
1006 }
1007