1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver 4 * 5 * Authors: Manish Narani <manish.narani@xilinx.com> 6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 #include <linux/firmware/xlnx-zynqmp.h> 23 #include <linux/io.h> 24 25 #include <linux/phy/phy.h> 26 27 /* USB phy reset mask register */ 28 #define XLNX_USB_PHY_RST_EN 0x001C 29 #define XLNX_PHY_RST_MASK 0x1 30 31 /* Xilinx USB 3.0 IP Register */ 32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C 33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1 34 35 /* USB 2.0 IP Register */ 36 #define XLNX_USB2_TRAFFIC_ROUTE_CONFIG 0x0044 37 38 #define XLNX_USB_FPD_PIPE_CLK 0x7c 39 #define PIPE_CLK_DESELECT 1 40 #define PIPE_CLK_SELECT 0 41 #define XLNX_USB_FPD_POWER_PRSNT 0x80 42 #define FPD_POWER_PRSNT_OPTION BIT(0) 43 44 struct dwc3_xlnx { 45 int num_clocks; 46 struct clk_bulk_data *clks; 47 struct device *dev; 48 void __iomem *regs; 49 int (*pltfm_init)(struct dwc3_xlnx *data); 50 struct phy *usb3_phy; 51 }; 52 53 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask) 54 { 55 u32 reg; 56 57 /* 58 * Enable or disable ULPI PHY reset from USB Controller. 59 * This does not actually reset the phy, but just controls 60 * whether USB controller can or cannot reset ULPI PHY. 61 */ 62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); 63 64 if (mask) 65 reg &= ~XLNX_PHY_RST_MASK; 66 else 67 reg |= XLNX_PHY_RST_MASK; 68 69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); 70 } 71 72 static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_offset) 73 { 74 struct device *dev = priv_data->dev; 75 u32 reg; 76 77 /* 78 * This routes the USB DMA traffic to go through FPD path instead 79 * of reaching DDR directly. This traffic routing is needed to 80 * make SMMU and CCI work with USB DMA. 81 */ 82 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { 83 reg = readl(priv_data->regs + coherency_offset); 84 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD; 85 writel(reg, priv_data->regs + coherency_offset); 86 } 87 } 88 89 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data) 90 { 91 struct device *dev = priv_data->dev; 92 struct reset_control *crst; 93 int ret; 94 95 crst = devm_reset_control_get_exclusive(dev, NULL); 96 if (IS_ERR(crst)) 97 return dev_err_probe(dev, PTR_ERR(crst), "failed to get reset signal\n"); 98 99 dwc3_xlnx_mask_phy_rst(priv_data, false); 100 101 /* Assert and De-assert reset */ 102 ret = reset_control_assert(crst); 103 if (ret < 0) { 104 dev_err_probe(dev, ret, "failed to assert Reset\n"); 105 return ret; 106 } 107 108 ret = reset_control_deassert(crst); 109 if (ret < 0) { 110 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); 111 return ret; 112 } 113 114 dwc3_xlnx_mask_phy_rst(priv_data, true); 115 dwc3_xlnx_set_coherency(priv_data, XLNX_USB2_TRAFFIC_ROUTE_CONFIG); 116 117 return 0; 118 } 119 120 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) 121 { 122 struct device *dev = priv_data->dev; 123 struct reset_control *crst, *hibrst, *apbrst; 124 struct gpio_desc *reset_gpio; 125 int ret = 0; 126 127 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy"); 128 if (IS_ERR(priv_data->usb3_phy)) { 129 ret = PTR_ERR(priv_data->usb3_phy); 130 dev_err_probe(dev, ret, 131 "failed to get USB3 PHY\n"); 132 goto err; 133 } 134 135 /* 136 * The following core resets are not required unless a USB3 PHY 137 * is used, and the subsequent register settings are not required 138 * unless a core reset is performed (they should be set properly 139 * by the first-stage boot loader, but may be reverted by a core 140 * reset). They may also break the configuration if USB3 is actually 141 * in use but the usb3-phy entry is missing from the device tree. 142 * Therefore, skip these operations in this case. 143 */ 144 if (!priv_data->usb3_phy) { 145 /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ 146 writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); 147 goto skip_usb3_phy; 148 } 149 150 crst = devm_reset_control_get_exclusive(dev, "usb_crst"); 151 if (IS_ERR(crst)) { 152 ret = PTR_ERR(crst); 153 dev_err_probe(dev, ret, 154 "failed to get core reset signal\n"); 155 goto err; 156 } 157 158 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst"); 159 if (IS_ERR(hibrst)) { 160 ret = PTR_ERR(hibrst); 161 dev_err_probe(dev, ret, 162 "failed to get hibernation reset signal\n"); 163 goto err; 164 } 165 166 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst"); 167 if (IS_ERR(apbrst)) { 168 ret = PTR_ERR(apbrst); 169 dev_err_probe(dev, ret, 170 "failed to get APB reset signal\n"); 171 goto err; 172 } 173 174 ret = reset_control_assert(crst); 175 if (ret < 0) { 176 dev_err(dev, "Failed to assert core reset\n"); 177 goto err; 178 } 179 180 ret = reset_control_assert(hibrst); 181 if (ret < 0) { 182 dev_err(dev, "Failed to assert hibernation reset\n"); 183 goto err; 184 } 185 186 ret = reset_control_assert(apbrst); 187 if (ret < 0) { 188 dev_err(dev, "Failed to assert APB reset\n"); 189 goto err; 190 } 191 192 ret = phy_init(priv_data->usb3_phy); 193 if (ret < 0) { 194 phy_exit(priv_data->usb3_phy); 195 goto err; 196 } 197 198 ret = reset_control_deassert(apbrst); 199 if (ret < 0) { 200 dev_err(dev, "Failed to release APB reset\n"); 201 goto err; 202 } 203 204 /* Set PIPE Power Present signal in FPD Power Present Register*/ 205 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT); 206 207 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ 208 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); 209 210 ret = reset_control_deassert(crst); 211 if (ret < 0) { 212 dev_err(dev, "Failed to release core reset\n"); 213 goto err; 214 } 215 216 ret = reset_control_deassert(hibrst); 217 if (ret < 0) { 218 dev_err(dev, "Failed to release hibernation reset\n"); 219 goto err; 220 } 221 222 ret = phy_power_on(priv_data->usb3_phy); 223 if (ret < 0) { 224 phy_exit(priv_data->usb3_phy); 225 goto err; 226 } 227 228 skip_usb3_phy: 229 /* ulpi reset via gpio-modepin or gpio-framework driver */ 230 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 231 if (IS_ERR(reset_gpio)) { 232 return dev_err_probe(dev, PTR_ERR(reset_gpio), 233 "Failed to request reset GPIO\n"); 234 } 235 236 if (reset_gpio) { 237 usleep_range(5000, 10000); 238 gpiod_set_value_cansleep(reset_gpio, 0); 239 usleep_range(5000, 10000); 240 } 241 242 dwc3_xlnx_set_coherency(priv_data, XLNX_USB_TRAFFIC_ROUTE_CONFIG); 243 err: 244 return ret; 245 } 246 247 static const struct of_device_id dwc3_xlnx_of_match[] = { 248 { 249 .compatible = "xlnx,zynqmp-dwc3", 250 .data = &dwc3_xlnx_init_zynqmp, 251 }, 252 { 253 .compatible = "xlnx,versal-dwc3", 254 .data = &dwc3_xlnx_init_versal, 255 }, 256 { /* Sentinel */ } 257 }; 258 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match); 259 260 static int dwc3_set_swnode(struct device *dev) 261 { 262 struct device_node *np = dev->of_node, *dwc3_np; 263 struct property_entry props[2]; 264 int prop_idx = 0, ret = 0; 265 266 dwc3_np = of_get_compatible_child(np, "snps,dwc3"); 267 if (!dwc3_np) { 268 ret = -ENODEV; 269 dev_err(dev, "failed to find dwc3 core child\n"); 270 return ret; 271 } 272 273 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props)); 274 if (of_dma_is_coherent(dwc3_np)) 275 props[prop_idx++] = PROPERTY_ENTRY_U16("snps,gsbuscfg0-reqinfo", 276 0xffff); 277 of_node_put(dwc3_np); 278 279 if (prop_idx) 280 ret = device_create_managed_software_node(dev, props, NULL); 281 282 return ret; 283 } 284 285 static int dwc3_xlnx_probe(struct platform_device *pdev) 286 { 287 struct dwc3_xlnx *priv_data; 288 struct device *dev = &pdev->dev; 289 struct device_node *np = dev->of_node; 290 const struct of_device_id *match; 291 void __iomem *regs; 292 int ret; 293 294 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL); 295 if (!priv_data) 296 return -ENOMEM; 297 298 regs = devm_platform_ioremap_resource(pdev, 0); 299 if (IS_ERR(regs)) 300 return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n"); 301 302 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node); 303 304 priv_data->pltfm_init = match->data; 305 priv_data->regs = regs; 306 priv_data->dev = dev; 307 308 platform_set_drvdata(pdev, priv_data); 309 310 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks); 311 if (ret < 0) 312 return ret; 313 314 priv_data->num_clocks = ret; 315 316 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks); 317 if (ret) 318 return ret; 319 320 ret = priv_data->pltfm_init(priv_data); 321 if (ret) 322 goto err_clk_put; 323 324 ret = dwc3_set_swnode(dev); 325 if (ret) 326 goto err_clk_put; 327 328 ret = of_platform_populate(np, NULL, NULL, dev); 329 if (ret) 330 goto err_clk_put; 331 332 pm_runtime_set_active(dev); 333 ret = devm_pm_runtime_enable(dev); 334 if (ret < 0) 335 goto err_pm_set_suspended; 336 337 pm_suspend_ignore_children(dev, false); 338 ret = pm_runtime_resume_and_get(dev); 339 if (ret < 0) 340 goto err_pm_set_suspended; 341 342 return 0; 343 344 err_pm_set_suspended: 345 of_platform_depopulate(dev); 346 pm_runtime_set_suspended(dev); 347 348 err_clk_put: 349 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 350 351 return ret; 352 } 353 354 static void dwc3_xlnx_remove(struct platform_device *pdev) 355 { 356 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev); 357 struct device *dev = &pdev->dev; 358 359 of_platform_depopulate(dev); 360 361 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 362 priv_data->num_clocks = 0; 363 364 pm_runtime_put_noidle(dev); 365 pm_runtime_set_suspended(dev); 366 } 367 368 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev) 369 { 370 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 371 372 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 373 374 return 0; 375 } 376 377 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev) 378 { 379 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 380 381 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 382 } 383 384 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev) 385 { 386 pm_runtime_mark_last_busy(dev); 387 pm_runtime_autosuspend(dev); 388 389 return 0; 390 } 391 392 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev) 393 { 394 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 395 396 phy_exit(priv_data->usb3_phy); 397 398 /* Disable the clocks */ 399 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 400 401 return 0; 402 } 403 404 static int __maybe_unused dwc3_xlnx_resume(struct device *dev) 405 { 406 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 407 int ret; 408 409 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 410 if (ret) 411 return ret; 412 413 ret = phy_init(priv_data->usb3_phy); 414 if (ret < 0) 415 return ret; 416 417 ret = phy_power_on(priv_data->usb3_phy); 418 if (ret < 0) { 419 phy_exit(priv_data->usb3_phy); 420 return ret; 421 } 422 423 return 0; 424 } 425 426 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = { 427 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume) 428 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend, 429 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle) 430 }; 431 432 static struct platform_driver dwc3_xlnx_driver = { 433 .probe = dwc3_xlnx_probe, 434 .remove = dwc3_xlnx_remove, 435 .shutdown = dwc3_xlnx_remove, 436 .driver = { 437 .name = "dwc3-xilinx", 438 .of_match_table = dwc3_xlnx_of_match, 439 .pm = &dwc3_xlnx_dev_pm_ops, 440 }, 441 }; 442 443 module_platform_driver(dwc3_xlnx_driver); 444 445 MODULE_LICENSE("GPL v2"); 446 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver"); 447 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>"); 448 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>"); 449