1 /** 2 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms 3 * 4 * This is a small driver for the dwc3 to provide the glue logic 5 * to configure the controller. Tested on STi platforms. 6 * 7 * Copyright (C) 2014 Stmicroelectronics 8 * 9 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 * Contributors: Aymen Bouattay <aymen.bouattay@st.com> 11 * Peter Griffin <peter.griffin@linaro.org> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * Inspired by dwc3-omap.c and dwc3-exynos.c. 19 */ 20 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/kernel.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/slab.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/usb/of.h> 35 36 #include "core.h" 37 #include "io.h" 38 39 /* glue registers */ 40 #define CLKRST_CTRL 0x00 41 #define AUX_CLK_EN BIT(0) 42 #define SW_PIPEW_RESET_N BIT(4) 43 #define EXT_CFG_RESET_N BIT(8) 44 /* 45 * 1'b0 : The host controller complies with the xHCI revision 0.96 46 * 1'b1 : The host controller complies with the xHCI revision 1.0 47 */ 48 #define XHCI_REVISION BIT(12) 49 50 #define USB2_VBUS_MNGMNT_SEL1 0x2C 51 /* 52 * For all fields in USB2_VBUS_MNGMNT_SEL1 53 * 2’b00 : Override value from Reg 0x30 is selected 54 * 2’b01 : utmiotg_<signal_name> from usb3_top is selected 55 * 2’b10 : pipew_<signal_name> from PIPEW instance is selected 56 * 2’b11 : value is 1'b0 57 */ 58 #define USB2_VBUS_REG30 0x0 59 #define USB2_VBUS_UTMIOTG 0x1 60 #define USB2_VBUS_PIPEW 0x2 61 #define USB2_VBUS_ZERO 0x3 62 63 #define SEL_OVERRIDE_VBUSVALID(n) (n << 0) 64 #define SEL_OVERRIDE_POWERPRESENT(n) (n << 4) 65 #define SEL_OVERRIDE_BVALID(n) (n << 8) 66 67 /* Static DRD configuration */ 68 #define USB3_CONTROL_MASK 0xf77 69 70 #define USB3_DEVICE_NOT_HOST BIT(0) 71 #define USB3_FORCE_VBUSVALID BIT(1) 72 #define USB3_DELAY_VBUSVALID BIT(2) 73 #define USB3_SEL_FORCE_OPMODE BIT(4) 74 #define USB3_FORCE_OPMODE(n) (n << 5) 75 #define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) 76 #define USB3_FORCE_DPPULLDOWN2 BIT(9) 77 #define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) 78 #define USB3_FORCE_DMPULLDOWN2 BIT(11) 79 80 /** 81 * struct st_dwc3 - dwc3-st driver private structure 82 * @dev: device pointer 83 * @glue_base: ioaddr for the glue registers 84 * @regmap: regmap pointer for getting syscfg 85 * @syscfg_reg_off: usb syscfg control offset 86 * @dr_mode: drd static host/device config 87 * @rstc_pwrdn: rest controller for powerdown signal 88 * @rstc_rst: reset controller for softreset signal 89 */ 90 91 struct st_dwc3 { 92 struct device *dev; 93 void __iomem *glue_base; 94 struct regmap *regmap; 95 int syscfg_reg_off; 96 enum usb_dr_mode dr_mode; 97 struct reset_control *rstc_pwrdn; 98 struct reset_control *rstc_rst; 99 }; 100 101 static inline u32 st_dwc3_readl(void __iomem *base, u32 offset) 102 { 103 return readl_relaxed(base + offset); 104 } 105 106 static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value) 107 { 108 writel_relaxed(value, base + offset); 109 } 110 111 /** 112 * st_dwc3_drd_init: program the port 113 * @dwc3_data: driver private structure 114 * Description: this function is to program the port as either host or device 115 * according to the static configuration passed from devicetree. 116 * OTG and dual role are not yet supported! 117 */ 118 static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data) 119 { 120 u32 val; 121 int err; 122 123 err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val); 124 if (err) 125 return err; 126 127 val &= USB3_CONTROL_MASK; 128 129 switch (dwc3_data->dr_mode) { 130 case USB_DR_MODE_PERIPHERAL: 131 132 val &= ~(USB3_DELAY_VBUSVALID 133 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) 134 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 135 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); 136 137 /* 138 * USB3_PORT2_FORCE_VBUSVALID When '1' and when 139 * USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input 140 * of the pico PHY to 1. 141 */ 142 143 val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; 144 break; 145 146 case USB_DR_MODE_HOST: 147 148 val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID 149 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) 150 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 151 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); 152 153 /* 154 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus, 155 * when set to ‘0‘, it can delay the arrival of VBUSVALID 156 * information to VBUSVLDEXT2 input of the pico PHY. 157 * We don't want to do that so we set the bit to '1'. 158 */ 159 160 val |= USB3_DELAY_VBUSVALID; 161 break; 162 163 default: 164 dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n", 165 dwc3_data->dr_mode); 166 return -EINVAL; 167 } 168 169 return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val); 170 } 171 172 /** 173 * st_dwc3_init: init the controller via glue logic 174 * @dwc3_data: driver private structure 175 */ 176 static void st_dwc3_init(struct st_dwc3 *dwc3_data) 177 { 178 u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); 179 180 reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; 181 reg &= ~SW_PIPEW_RESET_N; 182 st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); 183 184 /* configure mux for vbus, powerpresent and bvalid signals */ 185 reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1); 186 187 reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | 188 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | 189 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); 190 191 st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg); 192 193 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); 194 reg |= SW_PIPEW_RESET_N; 195 st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); 196 } 197 198 static int st_dwc3_probe(struct platform_device *pdev) 199 { 200 struct st_dwc3 *dwc3_data; 201 struct resource *res; 202 struct device *dev = &pdev->dev; 203 struct device_node *node = dev->of_node, *child; 204 struct platform_device *child_pdev; 205 struct regmap *regmap; 206 int ret; 207 208 dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL); 209 if (!dwc3_data) 210 return -ENOMEM; 211 212 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg-glue"); 213 dwc3_data->glue_base = devm_ioremap_resource(dev, res); 214 if (IS_ERR(dwc3_data->glue_base)) 215 return PTR_ERR(dwc3_data->glue_base); 216 217 regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg"); 218 if (IS_ERR(regmap)) 219 return PTR_ERR(regmap); 220 221 dma_set_coherent_mask(dev, dev->coherent_dma_mask); 222 dwc3_data->dev = dev; 223 dwc3_data->regmap = regmap; 224 225 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg"); 226 if (!res) { 227 ret = -ENXIO; 228 goto undo_platform_dev_alloc; 229 } 230 231 dwc3_data->syscfg_reg_off = res->start; 232 233 dev_vdbg(&pdev->dev, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n", 234 dwc3_data->glue_base, dwc3_data->syscfg_reg_off); 235 236 dwc3_data->rstc_pwrdn = 237 devm_reset_control_get_exclusive(dev, "powerdown"); 238 if (IS_ERR(dwc3_data->rstc_pwrdn)) { 239 dev_err(&pdev->dev, "could not get power controller\n"); 240 ret = PTR_ERR(dwc3_data->rstc_pwrdn); 241 goto undo_platform_dev_alloc; 242 } 243 244 /* Manage PowerDown */ 245 reset_control_deassert(dwc3_data->rstc_pwrdn); 246 247 dwc3_data->rstc_rst = 248 devm_reset_control_get_shared(dev, "softreset"); 249 if (IS_ERR(dwc3_data->rstc_rst)) { 250 dev_err(&pdev->dev, "could not get reset controller\n"); 251 ret = PTR_ERR(dwc3_data->rstc_rst); 252 goto undo_powerdown; 253 } 254 255 /* Manage SoftReset */ 256 reset_control_deassert(dwc3_data->rstc_rst); 257 258 child = of_get_child_by_name(node, "dwc3"); 259 if (!child) { 260 dev_err(&pdev->dev, "failed to find dwc3 core node\n"); 261 ret = -ENODEV; 262 goto undo_softreset; 263 } 264 265 /* Allocate and initialize the core */ 266 ret = of_platform_populate(node, NULL, NULL, dev); 267 if (ret) { 268 dev_err(dev, "failed to add dwc3 core\n"); 269 goto undo_softreset; 270 } 271 272 child_pdev = of_find_device_by_node(child); 273 if (!child_pdev) { 274 dev_err(dev, "failed to find dwc3 core device\n"); 275 ret = -ENODEV; 276 goto undo_softreset; 277 } 278 279 dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev); 280 281 /* 282 * Configure the USB port as device or host according to the static 283 * configuration passed from DT. 284 * DRD is the only mode currently supported so this will be enhanced 285 * as soon as OTG is available. 286 */ 287 ret = st_dwc3_drd_init(dwc3_data); 288 if (ret) { 289 dev_err(dev, "drd initialisation failed\n"); 290 goto undo_softreset; 291 } 292 293 /* ST glue logic init */ 294 st_dwc3_init(dwc3_data); 295 296 platform_set_drvdata(pdev, dwc3_data); 297 return 0; 298 299 undo_softreset: 300 reset_control_assert(dwc3_data->rstc_rst); 301 undo_powerdown: 302 reset_control_assert(dwc3_data->rstc_pwrdn); 303 undo_platform_dev_alloc: 304 platform_device_put(pdev); 305 return ret; 306 } 307 308 static int st_dwc3_remove(struct platform_device *pdev) 309 { 310 struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev); 311 312 of_platform_depopulate(&pdev->dev); 313 314 reset_control_assert(dwc3_data->rstc_pwrdn); 315 reset_control_assert(dwc3_data->rstc_rst); 316 317 return 0; 318 } 319 320 #ifdef CONFIG_PM_SLEEP 321 static int st_dwc3_suspend(struct device *dev) 322 { 323 struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); 324 325 reset_control_assert(dwc3_data->rstc_pwrdn); 326 reset_control_assert(dwc3_data->rstc_rst); 327 328 pinctrl_pm_select_sleep_state(dev); 329 330 return 0; 331 } 332 333 static int st_dwc3_resume(struct device *dev) 334 { 335 struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); 336 int ret; 337 338 pinctrl_pm_select_default_state(dev); 339 340 reset_control_deassert(dwc3_data->rstc_pwrdn); 341 reset_control_deassert(dwc3_data->rstc_rst); 342 343 ret = st_dwc3_drd_init(dwc3_data); 344 if (ret) { 345 dev_err(dev, "drd initialisation failed\n"); 346 return ret; 347 } 348 349 /* ST glue logic init */ 350 st_dwc3_init(dwc3_data); 351 352 return 0; 353 } 354 #endif /* CONFIG_PM_SLEEP */ 355 356 static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume); 357 358 static const struct of_device_id st_dwc3_match[] = { 359 { .compatible = "st,stih407-dwc3" }, 360 { /* sentinel */ }, 361 }; 362 363 MODULE_DEVICE_TABLE(of, st_dwc3_match); 364 365 static struct platform_driver st_dwc3_driver = { 366 .probe = st_dwc3_probe, 367 .remove = st_dwc3_remove, 368 .driver = { 369 .name = "usb-st-dwc3", 370 .of_match_table = st_dwc3_match, 371 .pm = &st_dwc3_dev_pm_ops, 372 }, 373 }; 374 375 module_platform_driver(st_dwc3_driver); 376 377 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 378 MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer"); 379 MODULE_LICENSE("GPL v2"); 380