xref: /linux/drivers/usb/dwc3/dwc3-st.c (revision 55d0969c451159cff86949b38c39171cab962069) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
4  *
5  * This is a small driver for the dwc3 to provide the glue logic
6  * to configure the controller. Tested on STi platforms.
7  *
8  * Copyright (C) 2014 Stmicroelectronics
9  *
10  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11  * Contributors: Aymen Bouattay <aymen.bouattay@st.com>
12  *               Peter Griffin <peter.griffin@linaro.org>
13  *
14  * Inspired by dwc3-omap.c and dwc3-exynos.c.
15  */
16 
17 #include <linux/cleanup.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/regmap.h>
30 #include <linux/reset.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/usb/of.h>
33 
34 #include "core.h"
35 #include "io.h"
36 
37 /* glue registers */
38 #define CLKRST_CTRL		0x00
39 #define AUX_CLK_EN		BIT(0)
40 #define SW_PIPEW_RESET_N	BIT(4)
41 #define EXT_CFG_RESET_N		BIT(8)
42 /*
43  * 1'b0 : The host controller complies with the xHCI revision 0.96
44  * 1'b1 : The host controller complies with the xHCI revision 1.0
45  */
46 #define XHCI_REVISION		BIT(12)
47 
48 #define USB2_VBUS_MNGMNT_SEL1	0x2C
49 /*
50  * For all fields in USB2_VBUS_MNGMNT_SEL1
51  * 2’b00 : Override value from Reg 0x30 is selected
52  * 2’b01 : utmiotg_<signal_name> from usb3_top is selected
53  * 2’b10 : pipew_<signal_name> from PIPEW instance is selected
54  * 2’b11 : value is 1'b0
55  */
56 #define USB2_VBUS_REG30		0x0
57 #define USB2_VBUS_UTMIOTG	0x1
58 #define USB2_VBUS_PIPEW		0x2
59 #define USB2_VBUS_ZERO		0x3
60 
61 #define SEL_OVERRIDE_VBUSVALID(n)	(n << 0)
62 #define SEL_OVERRIDE_POWERPRESENT(n)	(n << 4)
63 #define SEL_OVERRIDE_BVALID(n)		(n << 8)
64 
65 /* Static DRD configuration */
66 #define USB3_CONTROL_MASK		0xf77
67 
68 #define USB3_DEVICE_NOT_HOST		BIT(0)
69 #define USB3_FORCE_VBUSVALID		BIT(1)
70 #define USB3_DELAY_VBUSVALID		BIT(2)
71 #define USB3_SEL_FORCE_OPMODE		BIT(4)
72 #define USB3_FORCE_OPMODE(n)		(n << 5)
73 #define USB3_SEL_FORCE_DPPULLDOWN2	BIT(8)
74 #define USB3_FORCE_DPPULLDOWN2		BIT(9)
75 #define USB3_SEL_FORCE_DMPULLDOWN2	BIT(10)
76 #define USB3_FORCE_DMPULLDOWN2		BIT(11)
77 
78 /**
79  * struct st_dwc3 - dwc3-st driver private structure
80  * @dev:		device pointer
81  * @glue_base:		ioaddr for the glue registers
82  * @regmap:		regmap pointer for getting syscfg
83  * @syscfg_reg_off:	usb syscfg control offset
84  * @dr_mode:		drd static host/device config
85  * @rstc_pwrdn:		rest controller for powerdown signal
86  * @rstc_rst:		reset controller for softreset signal
87  */
88 
89 struct st_dwc3 {
90 	struct device *dev;
91 	void __iomem *glue_base;
92 	struct regmap *regmap;
93 	int syscfg_reg_off;
94 	enum usb_dr_mode dr_mode;
95 	struct reset_control *rstc_pwrdn;
96 	struct reset_control *rstc_rst;
97 };
98 
99 static inline u32 st_dwc3_readl(void __iomem *base, u32 offset)
100 {
101 	return readl_relaxed(base + offset);
102 }
103 
104 static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value)
105 {
106 	writel_relaxed(value, base + offset);
107 }
108 
109 /**
110  * st_dwc3_drd_init: program the port
111  * @dwc3_data: driver private structure
112  * Description: this function is to program the port as either host or device
113  * according to the static configuration passed from devicetree.
114  * OTG and dual role are not yet supported!
115  */
116 static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data)
117 {
118 	u32 val;
119 	int err;
120 
121 	err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val);
122 	if (err)
123 		return err;
124 
125 	val &= USB3_CONTROL_MASK;
126 
127 	switch (dwc3_data->dr_mode) {
128 	case USB_DR_MODE_PERIPHERAL:
129 
130 		val &= ~(USB3_DELAY_VBUSVALID
131 			| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
132 			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
133 			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
134 
135 		/*
136 		 * USB3_PORT2_FORCE_VBUSVALID When '1' and when
137 		 * USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input
138 		 * of the pico PHY to 1.
139 		 */
140 
141 		val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
142 		break;
143 
144 	case USB_DR_MODE_HOST:
145 
146 		val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
147 			| USB3_SEL_FORCE_OPMODE	| USB3_FORCE_OPMODE(0x3)
148 			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
149 			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
150 
151 		/*
152 		 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus,
153 		 * when set to ‘0‘, it can delay the arrival of VBUSVALID
154 		 * information to VBUSVLDEXT2 input of the pico PHY.
155 		 * We don't want to do that so we set the bit to '1'.
156 		 */
157 
158 		val |= USB3_DELAY_VBUSVALID;
159 		break;
160 
161 	default:
162 		dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n",
163 			dwc3_data->dr_mode);
164 		return -EINVAL;
165 	}
166 
167 	return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val);
168 }
169 
170 /**
171  * st_dwc3_init: init the controller via glue logic
172  * @dwc3_data: driver private structure
173  */
174 static void st_dwc3_init(struct st_dwc3 *dwc3_data)
175 {
176 	u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
177 
178 	reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
179 	reg &= ~SW_PIPEW_RESET_N;
180 	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
181 
182 	/* configure mux for vbus, powerpresent and bvalid signals */
183 	reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1);
184 
185 	reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
186 		SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
187 		SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
188 
189 	st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg);
190 
191 	reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
192 	reg |= SW_PIPEW_RESET_N;
193 	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
194 }
195 
196 static int st_dwc3_probe(struct platform_device *pdev)
197 {
198 	struct st_dwc3 *dwc3_data;
199 	struct resource *res;
200 	struct device *dev = &pdev->dev;
201 	struct device_node *node = dev->of_node;
202 	struct platform_device *child_pdev;
203 	struct regmap *regmap;
204 	int ret;
205 
206 	dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL);
207 	if (!dwc3_data)
208 		return -ENOMEM;
209 
210 	dwc3_data->glue_base =
211 		devm_platform_ioremap_resource_byname(pdev, "reg-glue");
212 	if (IS_ERR(dwc3_data->glue_base))
213 		return PTR_ERR(dwc3_data->glue_base);
214 
215 	regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg");
216 	if (IS_ERR(regmap))
217 		return PTR_ERR(regmap);
218 
219 	dwc3_data->dev = dev;
220 	dwc3_data->regmap = regmap;
221 
222 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg");
223 	if (!res)
224 		return -ENXIO;
225 
226 	dwc3_data->syscfg_reg_off = res->start;
227 
228 	dev_vdbg(dev, "glue-logic addr 0x%pK, syscfg-reg offset 0x%x\n",
229 		 dwc3_data->glue_base, dwc3_data->syscfg_reg_off);
230 
231 	struct device_node *child __free(device_node) = of_get_compatible_child(node,
232 										"snps,dwc3");
233 	if (!child) {
234 		dev_err(dev, "failed to find dwc3 core node\n");
235 		return -ENODEV;
236 	}
237 
238 	dwc3_data->rstc_pwrdn =
239 		devm_reset_control_get_exclusive(dev, "powerdown");
240 	if (IS_ERR(dwc3_data->rstc_pwrdn))
241 		return dev_err_probe(dev, PTR_ERR(dwc3_data->rstc_pwrdn),
242 				     "could not get power controller\n");
243 
244 	/* Manage PowerDown */
245 	reset_control_deassert(dwc3_data->rstc_pwrdn);
246 
247 	dwc3_data->rstc_rst =
248 		devm_reset_control_get_shared(dev, "softreset");
249 	if (IS_ERR(dwc3_data->rstc_rst)) {
250 		ret = dev_err_probe(dev, PTR_ERR(dwc3_data->rstc_rst),
251 				    "could not get reset controller\n");
252 		goto undo_powerdown;
253 	}
254 
255 	/* Manage SoftReset */
256 	reset_control_deassert(dwc3_data->rstc_rst);
257 
258 	/* Allocate and initialize the core */
259 	ret = of_platform_populate(node, NULL, NULL, dev);
260 	if (ret) {
261 		dev_err(dev, "failed to add dwc3 core\n");
262 		goto undo_softreset;
263 	}
264 
265 	child_pdev = of_find_device_by_node(child);
266 	if (!child_pdev) {
267 		dev_err(dev, "failed to find dwc3 core device\n");
268 		ret = -ENODEV;
269 		goto depopulate;
270 	}
271 
272 	dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev);
273 	platform_device_put(child_pdev);
274 
275 	/*
276 	 * Configure the USB port as device or host according to the static
277 	 * configuration passed from DT.
278 	 * DRD is the only mode currently supported so this will be enhanced
279 	 * as soon as OTG is available.
280 	 */
281 	ret = st_dwc3_drd_init(dwc3_data);
282 	if (ret) {
283 		dev_err(dev, "drd initialisation failed\n");
284 		goto depopulate;
285 	}
286 
287 	/* ST glue logic init */
288 	st_dwc3_init(dwc3_data);
289 
290 	platform_set_drvdata(pdev, dwc3_data);
291 	return 0;
292 
293 depopulate:
294 	of_platform_depopulate(dev);
295 undo_softreset:
296 	reset_control_assert(dwc3_data->rstc_rst);
297 undo_powerdown:
298 	reset_control_assert(dwc3_data->rstc_pwrdn);
299 	return ret;
300 }
301 
302 static void st_dwc3_remove(struct platform_device *pdev)
303 {
304 	struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev);
305 
306 	of_platform_depopulate(&pdev->dev);
307 
308 	reset_control_assert(dwc3_data->rstc_pwrdn);
309 	reset_control_assert(dwc3_data->rstc_rst);
310 }
311 
312 #ifdef CONFIG_PM_SLEEP
313 static int st_dwc3_suspend(struct device *dev)
314 {
315 	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
316 
317 	reset_control_assert(dwc3_data->rstc_pwrdn);
318 	reset_control_assert(dwc3_data->rstc_rst);
319 
320 	pinctrl_pm_select_sleep_state(dev);
321 
322 	return 0;
323 }
324 
325 static int st_dwc3_resume(struct device *dev)
326 {
327 	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
328 	int ret;
329 
330 	pinctrl_pm_select_default_state(dev);
331 
332 	reset_control_deassert(dwc3_data->rstc_pwrdn);
333 	reset_control_deassert(dwc3_data->rstc_rst);
334 
335 	ret = st_dwc3_drd_init(dwc3_data);
336 	if (ret) {
337 		dev_err(dev, "drd initialisation failed\n");
338 		return ret;
339 	}
340 
341 	/* ST glue logic init */
342 	st_dwc3_init(dwc3_data);
343 
344 	return 0;
345 }
346 #endif /* CONFIG_PM_SLEEP */
347 
348 static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume);
349 
350 static const struct of_device_id st_dwc3_match[] = {
351 	{ .compatible = "st,stih407-dwc3" },
352 	{ /* sentinel */ },
353 };
354 
355 MODULE_DEVICE_TABLE(of, st_dwc3_match);
356 
357 static struct platform_driver st_dwc3_driver = {
358 	.probe = st_dwc3_probe,
359 	.remove_new = st_dwc3_remove,
360 	.driver = {
361 		.name = "usb-st-dwc3",
362 		.of_match_table = st_dwc3_match,
363 		.pm = &st_dwc3_dev_pm_ops,
364 	},
365 };
366 
367 module_platform_driver(st_dwc3_driver);
368 
369 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
370 MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer");
371 MODULE_LICENSE("GPL v2");
372